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February 2004 MSDS Bus Solutions

User’s Guide

SLLU020A

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Running Title—Attribute Reference

iii Chapter Title—Attribute Reference

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1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 8052 Embedded Microcontroller Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 USB Transfers 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 USB Transfers 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Control Read Transfer 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Control Write Transfer Without Data 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Control Write Transfer With Data 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Irregular Control Transfers 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Bulk IN Transfer 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Bulk OUT Transfer 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Interrupt IN Transfer 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Application Firmware Programming Examples 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 System Initialization Routine 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 USB Reset Routine 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 USB ISR Routine 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 USB Setup Packet Routine 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 USB Data Endpoint 0 Routine 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 USB Data Endpoint 1 Routine 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


iv

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2−1 Control Read Transfer 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 Interrupts in Control Read Transfer 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 Control Write Transfer Without Data 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4 Interrupt in Control Write Transfer Without Data 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5 Control Write Transfer With Data 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−6 Interrupt in Control Write Transfer With Data 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7 Back-to-Back Setup 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−8 Interrupt Back-to-Back Setup 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−9 Incomplete Transfer 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−10 Interrupt Incomplete Transfer 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−11 Interrupt/NAK in Bulk IN Transfer 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−12 Single Buffer Bulk IN Transfer 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−13 Double Buffer Bulk IN Transfer 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−14 Interrupt/NAK in Single Buffer Bulk OUT Transfer 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−15 Single Buffer Bulk OUT Transfer 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−16 Double Buffer Bulk OUT Transfer 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

� ��

1−1 Device Feature 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1 Chapter Title—Attribute Reference

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This chapter discusses the features of the 8052 embedded microcontroller.

Topic Page

1.1 8052 Embedded Microcontroller Features 1-2. . . . . . . . . . . . . . . . . . . . . . .

Chapter 1


1-2

1.1 8052 Embedded Microcontroller Features

The 8052 embedded microcontroller is a high-performance 8-bitmicrocontroller. It is binary/instruction-execute-time compatible with theindustry standard 8052AH and 8752BH discrete devices. Several features arelisted below and Table 1−1 illustrates the features of TUSB2136/3210/5052devices in normal operation.

� 256-byte internal data memory� Three 16-bit timer/counters� Full-duplex serial port� Power-down mode� I2C support� Up to 48 MHz operation at 12 clocks per instruction cycle� Supports SUSP and PUR pins

Table 1−1.Device Feature

Features/Device TUSB2136 TUSB3210 TUSB5052

8052 clock 12/48 MHz 12/48 MHz 12/24 MHz

USB interrupt INT3 INT3 INT3

Code memory size (bytes) 8K 8K 16K

Serial port (RS232) 1 1 3§

USB downstream port 2 0 5

Available I/O pins† 32 32 28‡

External interrupt pins 8 8 1

External interrupt source P2[7:0], P3.3 P2[7:0], P3.3 Wake-up

† P0 to P3 are embedded in 8052 while all others are in memory-mapped register (MMR).‡ Some are output or input only.§ Including 8052 embedded serial port


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This chapter provides details of the three types of supported USB transfers.

Topic Page

2.1 USB Transfers 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Control Read Transfer 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Control Write Transfer Without Data 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Control Write Transfer With Data 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Irregular Control Transfers 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Bulk IN Transfer 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Bulk OUT Transfer 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Interrupt IN Transfer 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2


2-2

2.1 USB Transfers

Four types of USB transfer are: control, interrupt, bulk, and isochronoustransfer. Control transfer allows the host to send USB requests to the device.Interrupt transfer allows the device to report its status back to the host in aspecified period. Bulk transfer allows the host and the device to send/receivedata when data arrival time is not important, while isochronous transferensures the data packet is delivered to the destination within a predefinedperiod. Any USB device is capable of supporting at least a control transfersince standard USB requests use control transfers.

Only interrupt programming flow is discussed, even though polling program-ming flow is feasible, but not sufficient, to utilize microcontroller processingpower.

Application firmware sets up control endpoint 0 before it connects to USB. Thefollowing registers are interrelated to control endpoint 0.

� FUNADR: Function Address RegisterThis register resets to zero before the device connects to the bus.

� IEPCNFG_0: Input Endpoint-0 Configuration RegisterUSBIE and UBME are set to 1 to enable the endpoint and correspondinginterrupt. The STALL bit is clear in normal operation. If the STALL bit is set,the device stalls the IN transaction. Therefore, the device does not sendany data back to the host.

� IEPBCNT_0: Input Endpoint-0 Byte Count RegisterDefault value is zero with the NAK bit set. If application firmware sends0x05 bytes of data back to the host, the firmware sets the register to 0x05with the NAK bit clear. The maximum is 8 bytes per IN transaction.

� OEPCNFG_0: Output Endpoint-0 Configuration RegisterUSBIE and UBME are set to 1 in order to enable the endpoint and corre-sponding interrupt. The STALL bit is clear in normal operation. If STALLis set, the device stalls the OUT transaction. Therefore, the device doesnot receive any data from the host.

� OEPBCNT_0: Output Endpoint-0 Byte Count RegisterDefault value is zero with the NAK bit clear. If the device receives 0x05bytes from the host, it sets the byte count to 0x05 and clears the NAK. Ifthe interrupt is enabled, it generates an interrupt to notify applicationfirmware that an OUT transaction is completed and data is in the buffer.

� USBMSK: USB Interrupt Mask RegisterSTPOW and SETUP are set to 1. If there is a setup packet coming fromthe host, the device generates a SETUP interrupt to the application firm-ware and sets the SETUP bit in the USBSTA register. If more than one set-up packet is received before the application firmware is able to respondto the command, the STPOW bit is set.

� USBCTL: USB Control RegisterCONT is set to 1 when the device is ready.

� EA: Global Interrupt Enable BitThis is a global interrupt in the 8052 microcontroller. This bit is set if anyinterrupt is used.



� EX0: Internal INT 3This bit is set to 1. Application firmware uses this interrupt to handle all in-ternal interrupts including a USB interrupt.

2.2 Control Read Transfer

Control read transfer has three stages: setup, data and status stage. Eachstage represents a single USB transaction. As shown in Figure 2−1, the hostsends out a setup packet to the device. The device returns an ACK to showthat it received the setup packet. Once the host receives an ACK from thedevice, it then sends an IN token to get data from the device. If the device isready, it sends data back to the host (the first data in the data stage is alwaysDATA1). The host sends an ACK showing it received the data packet. If thedevice is not ready or still processing the setup request, NAK runs until the datais ready. Once the host receives enough data from the device, it sends an OUTtoken indicating it is ready to finish (or terminate, if all the data is not yet sentback to the host) the current transfer. This is a zero-length out packet. Thedevice returns an ACK to finish or terminate the current transfer.

Figure 2−1. Control Read Transfer

SETUP ADDR CRC5Token packet

ENDP DATA0 8 bytes setup data CRC16Data packet

ACKHandshake packet

Setup stage

ACKHandshake packet

IN ADDR CRC16Token packet

ENDP DATA1 Data payload CRC16Data packet

Data stage

ACKHandshake packet



Data stage

ACKHandshake packet

OUT ADDR CRC16Token packet

ENDP DATA1 CRC16Data packet

Status stage

Host Device

An interrupt is generated at the end of each transaction as shown inFigure 2−1. Interrupt 0x03 is captured in the application firmware. Once theroutine takes control from the hardware, it disables the global interrupt (EA =0) and then processes the interrupt vector. Once it knows the interrupt source,it clears the source before it notifies the respective interrupt handling routine.After the service routine is finished, it enables the global interrupt (EA = 1) thenreleases control to the interrupted routine. Some real-time systems requirethat global interrupt always be enabled. In this case, disable global interruptis removed. However, interrupt routines check for other setup-packet arrivals


2-4

before processing the current one. If there is another setup packet and thecurrent one is still being processed, application firmware abandons the currentone and processes the next setup packet.

Figure 2−2. Interrupts in Control Read Transfer

SETUP(0) IN(1) IN(0) IN(0/1) OUT(1)

INT INT INT INT

Morepackets

Setup stage Data stage Status stage

1.Hardware generates interrupt to MCU.

2.Set NAK on both endpoints.3.Set DIR bit in USBCTL to indicate the data direction and SIR bit to indicate setup interrupt is being served.

4.Decode the setup packet.5.If another setup packet arrives, abandon this one.

6.Execute appropriate routines. a) Clear NAK bit in OUT endpoint.

b) Copy data to IN endpoint buffer and set byte count.


2.Copy data to IN buffer.3.Clear the NAK bit.4.If all data has been sent out, stall input endpoint.

1.Hardware handles this but does not generate interrupt to MCU.

In some cases, early termination takes place if the host does not get any moredata from the device. Therefore, interrupt routine handing input/outputendpoint keeps tracking if the current stage is the data or status stage. If thetransfer reaches the status stage, firmware stalls the IN endpoint, so anyfurther IN tokens become stalled. A new setup packet arrival forces internallogic to clear the STALL bit on both endpoints.

Additional registers related to this transfer are:

� VECINT: Vector Interrupt RegisterA 0x32 value represents a SETUP packet received. A 0x30 represents aSTPOW packet received.

� USBCTL: USB Control RegisterThe DIR bit in the USBCTL register is set to 1 for control read transfer.

� USBSTA: USB Status RegisterThe SETUP/STPOW bit is set when setup(s) is/are received. Applicationfirmware writes a 1 to clear this bit.

� IEPCNFG_0: Input Endpoint-0 Configuration RegisterThe STALL bit in the IEPCNFG register is set to 1 at the end of data andstatus stages. This prevents application firmware from receiving anirregular request from the host.

� OEPCNFG_0: Output Endpoint-0 Configuration RegisterThe STALL bit in the OEPCNFG register is set to 1 at the end of data andstatus stages. This prevents application firmware from receiving anirregular request from the host.



2.3 Control Write Transfer Without Data

The control write transfer without data has only two stages: setup and status.In this type of transfer, application firmware processes the request and clearsNAK bit for the status stage.

Figure 2−3. Control Write Transfer Without Data



ACKHandshake packet

Setup stage

ACKHandshake packet



Status stage

Host Device

As shown in Figure 2−4, application firmware retains a note in the setup stage.At the end of status stage, the application firmware processes the request.

Figure 2−4. Interrupt in Control Write Transfer Without Data

SETUP(0) IN(1)

INT

Setup stage Status stage


2.Set NAK on both endpoints.3.Clear DIR bit in USBCTL to indicate the data direction and SIR bit to indicate setup interrupt is being served.


6.Execute appropriate routine. a) Clear NAK bit in IN endpoint.

.



2-6

2.4 Control Write Transfer With Data

Control write transfer with data has the following three stages: setup, data, andstatus. As shown in Figure 2−5, the host sends a setup packet along with adata packet to the device. The device returns an ACK showing it received thesetup packet. Once the host receives an ACK from the device, it transmits anOUT token and data to the device. If the device is ready to receive data, itreturns an ACK. If the device is not ready or still processing the setup request,it continues to NAK until it is ready to receive data. Once the host sendsenough data to the device, it transmits an IN token indicating it is set to finish(terminate if all the data has not been transmitted to the device) the currenttransfer. The device returns a zero-length packet, concluding the transfer.

Figure 2−5. Control Write Transfer With Data



ACKHandshake packet

Setup stage

ACKHandshake packet



Data stage

ACKHandshake packet



Data stage

ACKHandshake packet



Status stage

Host Device



As shown in Figure 2−6, application firmware clears both NAKs in the IN/OUTendpoints for the data and status stages. The host is capable of terminatingthe current transfer by sending an IN token. If this happens, applicationfirmware should terminate the current transfer and prepare for the next setuppacket.

Figure 2−6. Interrupt in Control Write Transfer With Data

SETUP(0) OUT(1) OUT(0) OUT(0/1) IN(1)

INT INT INT INT

Morepackets



2.Set NAK on both endpoints.3.Set DIR bit in USBCTL to indicate

indicate setup interrupt is being served.


6.Execute appropriate routines.a) Clear NAK bit in IN endpoint.

b) Copy data from OUT buffer and


2.Copy data data from OUT buffer.3.Clear the NAK bit.4.If all data has been received, stall output endpoint.


clear NAK bit in OUT endpoint.

the data direction and SIR bit to

2.5 Irregular Control Transfers

As shown in Figure 2−7 and Figure 2−8, application firmware processes thefirst setup packet while the second setup packet is being received. If thesecond setup packet is received before the application firmware can respondto the setup packet, the application firmware abandons the first one andprocesses the second one.

As shown in Figure 2−9 and Figure 2−10, application firmware clears the dataand status stages once it receives another setup in the previous transfer. Thisis a simple process for the application firmware, since it discards the data andserves a new setup request.


2-8

Figure 2−7. Back-to-Back Setup

Host Device



ACKHandshake packet



ACKHandshake packet

STPOW bit set inUSBSTA register

MCU is reading newcommand data

STPOW interruptgenerated

SETUP bit set inUSBSTA register

MCU is readingcommand data

SETUP interruptgenerated

MCU

Figure 2−8. Interrupt Back-to-Back Setup

SETUP(0) SETUP(0) IN(0)/OUT(0) IN(0/1)/OUT(0/1) OUT(1)/IN(1)

INT INT

Morepackets




4.Decode the setup packet.

1.Firmware discards previous setup packet.

2.Perform normal procedure for setup stage.


Setup stage

1.Hardware generates interrupt to MCU.2.Read/write data from/to IN/OUT buffer.

INT INT



Figure 2−9. Incomplete Transfer



ACKHandshake packet

Setup stage


MCU is readingcommand data


MCU configures USBinterface for data stage

ACKHandshake packet



Data stage



ACKHandshake packet

New setup stage


MCU is busy processingprevious data packet


MCU sets IN and OUTEP0 STALL bits

MCU responds to newSETUP interrupt

MCU clears STALL bits

ACKHandshake packet



New data stage

ACKHandshake packet



Host Device MCU

Status stage


2-10

Figure 2−10. Interrupt Incomplete Transfer

SETUP(0) OUT(1)/IN(1) SETUP(0) OUT(1)/IN(1)

INT INT INT

Nostatusstage

Setup stage Data stage Data stage



4.Decode the setup packet.


2.Prepare for data and status stage.

3.Decode the setup packet.4.Execute appropriate routines.

OUT(0)/IN(0)

INT

Setup stage

1.Hardware generates interrupt toMCU.

2.Set NAK on both endpoints.3.Set DIR bit in USBCTL to indicate the data directory andSIR bit to indicate setup

interrupt is being served.4.Decode the setup packet

INT

2.6 Bulk IN Transfer

As shown in Figure 2−11 and Figure 2−12, after the hardware receives an INtoken on IEP1, it either transmits a NAK or data to the host depending onwhether the hardware has data or not. If the hardware transmits data to thehost, it generates an interrupt to the MCU at the end of data transmission.Therefore, the application firmware senses data has been sent and it updatesthe IN buffer with new data.

Figure 2−13 shows dual buffer bulk in transfer. The toggle bit in the IEPCNF_1register indicates which buffer the application firmware accesses.

Figure 2−11. Interrupt/NAK in Bulk IN Transfer

IN(1) IN(0)

NAK INT

Data stage

1.Hardware does not generate interrupt to MCU if NAK is set.

2.Application is still copying data to input endpoint.

IN(1)

1.Hardware generate interrupt to MCU once data is transmitted.

2.Application copy data to input endpoint buffer.


2.Application is still copying data to input endpoint.

NAK

IN(0)

INT



Figure 2−12. Single Buffer Bulk IN Transfer

ACKHandshake packet

10. Host PC


8. Host PC


9. UBM

Responds tointerrupt

13. MCU

Starts writing data toX buffer

14. MCU

IEP1 interrupt

12. UBM

X NAK bit is set

11. UBM

Bus enumeration

2. MCU

Configure USB

1. MCU

IEP1 Interrupt

23. UBM

X NAK bit is set

22. UBM

NAKHandshake packet

5. UBM


4. Host PC

ENDP

Starts writing datato X buffer

3. MCU

NAKHandshake packet

16. UBM


15. Host PC

ENDP

Completed writingdata to X buffer

6. MCU

Updates byte count andclears NAK bit

7. MCU

Completed writingdata to X buffer

17. MCU

Updates byte count andclears X buffer NAK bit

18. MCU

ACKHandshake packet

21. Host PC


19. Host PC


20. UBM


2-12

Figure 2−13. Double Buffer Bulk IN Transfer

ACKHandshake packet

12. Host PC


10. Host PC


11. UBM


15. MCU

Starts writing data toX buffer

16. MCU

IN EP2 interruptTOGLE = 1

14. UBM

X NAK bit is set

13. UBM

Bus enumeration

2. MCU

Configure USB

1. MCU

NAKHandshake packet

6. UBM


5. Host PC

ENDP

ACKHandshake packet

26. Host PC


24. Host PC


25. UBM

Starts writing datato Y buffer

7. MCU

Completed writing data to Y buffer,updates Y byte count

8. MCU

Clears X and Y NAK bits

9. MCU

ACKHandshake packet

19. Host PC


17. Host PC


18. UBM

Starts writing data toY buffer

24. MCU


23. MCU

Completes writingdata to X buffer

22. MCU

IN EP2 interruptTOGLE = 0

21. UBM

Y NAK bit is set

20. UBM

Starts writing datato X buffer

3. MCU

Completed writing data to X buffer,updates X byte count, X NAK is still set

4. MCU



2.7 Bulk OUT Transfer

As shown in Figure 2−14 and Figure 2−15, after the hardware receives anOUT token on IEP2, it either transmits a NAK, if the NAK bit is not cleared, orgenerates an interrupt to the application firmware.

Figure 2−16 shows dual buffer bulk out transfer. The toggle bit in theIEPCNF_2 register indicates which buffer the application firmware accesses.

Figure 2−14. Interrupt/NAK in Single Buffer Bulk OUT Transfer

OUT(1) OUT(0)

NAK INT

Data stage


2.Application is preparing for receiving data from host.

OUT(1)

1.Hardware generates interrupt to MCU once data is transmitted.

2.Application receives data from host.


2.Application is preparing for receiving data from host.

NAK

OUT(0)

INT


2-14

Figure 2−15. Single Buffer Bulk OUT Transfer

NAKHandshake packet

12. UBM

OUT ADDR CRC16Data packet

10. Host PC


11. Host PC

Data moved andNAK bit cleared

16. MCU

OUT EP2 interrupt

20. UBM

ACKHandshake packet

5. UBM


3. Host PC


4. Host PC


8. MCU

Starts moving dataout of X EP buffer

9. MCU

OUT EP2 interrupt

7. UBM

NAK bit is set

6. UBM

NAKHandshake packet

15. UBM


13. Host PC


14. Host PC

ACKHandshake packet

19. UBM


17. Host PC


18. Host PC

Bus enumeration

2. MCU

Configure USB

1. MCU



Figure 2−16. Double Buffer Bulk OUT Transfer

ACKHandshake packet

12. UBM


10. Host PC


11. Host PC

ACKHandshake packet

5. UBM


3. Host PC


4. Host PC

NAKHandshake packet

19. UBM


17. Host PC


18. Host PC

ACKHandshake packet

24. UBM


22. Host PC


23. Host PC

Bus enumeration

2. MCU

Configure USB

1. MCU


27. MCU

Still moving datafrom Y buffer

28. MCU

OUT EP2 interrupt

26. UBM

X NAK bit is set

25. UBM


15. MCU

Still moving datafrom X buffer

16. MCU

OUT EP2 interrupt

14. UBM

Y NAK bit is set

13. UBM


8. MCU

Starts moving datafrom X buffer

9. MCU

OUT EP2 interrupt

7. UBM

X NAK bit is set

6. UBM

Data moved and XNAK bit cleared

20. MCU

Starts moving datafrom Y buffer

21. MCU

2.8 Interrupt IN Transfer

Interrupt IN transfer is similar to bulk IN transfer except the interrupt transferensures reception of an IN token from the host within a period of time, specifiedin the endpoint descriptor. The interrupt handling routine is the same as thebulk interrupt handling routine. Application firmware uses this type of interrupttransfer to provide status of the device or application related information. Thewait time between two consecutive interrupts is also specified in the endpointdescriptor in 1 ms increments.


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The step-by-step examples show how the application sets up the USBenvironment and responds to various USB transfers.

Topic Page

3.1 System Initialization Routine 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 USB Reset Routine 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 USB ISR Routine 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 USB Setup Packet Routine 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 USB Data Endpoint 0 Routine 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 USB Data Endpoint 1 Routine 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3


3-2

3.1 System Initialization Routine

Application firmware does not rely fully on the default register value afterpower on or warm boot since the application can not determine the previousstatus. Registers like bUSBCTL, bFUNADR are especially critical. They mustbe set to the proper value prior to USB enumeration. If the application firmwareprefers a hardware reset (MCU reset is tied to USB reset) instead of thefirmware control, the FRSTE bit in bUSBCTL register is not cleared. Thefollowing example shows that the device is disconnected from the USB andapplication firmware handles the USB reset as well as I2C and MCU speed.

VOID SystemInitialization(VOID)

{

EA = DISABLE;

// disconnect from USB, firmware handles USB reset

bUSBCTL = 0x00;

// set i2c speed

i2cSetBusSpeed(I2C_400KHZ);

// set to 48Mhz

bMCNFG = MCNFG_48MHZ;

// Enable the USB−specific Interrupts; SETUP, RESET and STPOW

bUSBMSK = USBMSK_STPOW | USBMSK_SETUP | USBMSK_RSTR | USBMSK_RESR | USBMSK_FSPR;

// Enable global and USB interrupt

EA = ENABLE;

EX0 = ENABLE;

// Enable Embedded Function

// Enable port 3 for TUSB2136/TUSB3210

// Enable port 6 for TUSB5052

// connect to USB

bUSBCTL = USB_CONT;

}



3.2 USB Reset Routine

Because application firmware handles USB reset, all endpoints and internalUSB-related variables are initialized in the usbReset() routine. If a hardwarereset is preferred, the routine can be changed to a usbInitialization() routine.

VOID usbReset(VOID)

{

bFUNADR = 0x00; // no device address

// this register needs to be

// cleared before enumeration

wBytesRemainingOnIEP0 = NO_MORE_DATA;

wBytesRemainingOnOEP0 = NO_MORE_DATA;

bStatusAction = STATUS_ACTION_NOTHING;

pbIEP0Buffer = (PBYTE)0x0000;

pbOEP0Buffer = (PBYTE)0x0000;

bConfigurationNumber = 0x00; // device unconfigured

bInterfaceNumber = 0x00;

// enable endpoint 0 interrupt

tEndPoint0DescriptorBlock.bIEPCNFG = EPCNF_USBIE | EPCNF_UBME;

tEndPoint0DescriptorBlock.bOEPCNFG = EPCNF_USBIE | EPCNF_UBME;

// enable all necessary endpoints here…

tOutputEndPointDescriptorBlock[0].bEPCNF = EPCNF_USBIE | EPCNF_UBME | EPCNF_DBUF;

tOutputEndPointDescriptorBlock[0].bEPBBAX = (BYTE)(OEP1_X_BUFFER_ADDRESS >> 3 & 0x00ff);

tOutputEndPointDescriptorBlock[0].bEPBCTX = 0x0000;

tOutputEndPointDescriptorBlock[0].bEPBBAY = (BYTE)(OEP1_Y_BUFFER_ADDRESS >> 3 & 0x00ff);

tOutputEndPointDescriptorBlock[0].bEPBCTY = 0x0000;

tOutputEndPointDescriptorBlock[0].bEPSIZXY = EP_MAX_PACKET_SIZE;

}

3.3 USB ISR Routine

With the device connected to the USB, the first event is USB RESET. Thisinstructs the MCU to execute a usbISR() routine. Generally, any USB eventtriggers an interrupt.

It is possible to disable the interrupt globally during the interrupt serviceroutine. The following example clears the global interrupt first. The interruptsource and bVECINT register must be cleared prior to or after executingappropriate subroutines. This allows the hardware to detect any new USBevents. Be aware that some events have the same interrupt source as thebVECINT register. If this is the case, the application firmware only needs toclear the bVECINT register. This is especially important when the applicationfirmware needs more time to process the USB request.


3-4

interrupt [0x03] VOID usbISR(VOID)

{

EA = DISABLE; // Disable any further interrupts

switch (bVECINT){ // Identify Interrupt ID

case VECINT_OUTPUT_ENDPOINT0:

bVECINT = 0x00;

OEP0InterruptHandler();

break;

case VECINT_INPUT_ENDPOINT0:

bVECINT = 0x00;

IEP0InterruptHandler();

break;

case VECINT_OUTPUT_ENDPOINT1:

bVECINT = 0x00;

OEP1InterruptHandler();

break;

case VECINT_STPOW_PACKET_RECEIVED:

// hardware clears STALL in both data endpoints once valid setup packet is

// received

// NAK data endpoints

tEndPoint0DescriptorBlock.bIEPBCNT = EPBCNT_NAK;

tEndPoint0DescriptorBlock.bOEPBCNT = EPBCNT_NAK;

// clear setup packet flag

bUSBSTA = USBSTA_STPOW;

bVECINT = 0x00;

SetupPacketInterruptHandler();

break;

case VECINT_SETUP_PACKET_RECEIVED:

// hardware clears STALL in both data endpointsonce valid setup packet is

// received

// NAK data endpoints

tEndPoint0DescriptorBlock.bIEPBCNT = EPBCNT_NAK;

tEndPoint0DescriptorBlock.bOEPBCNT = EPBCNT_NAK;

SetupPacketInterruptHandler();

break;

case VECINT_RSTR_INTERRUPT:

// clear reset flag

bUSBSTA = USBSTA_RSTR;

bVECINT = 0x00;

UsbReset();

break;

default:break; // unknown interrupt ID

}

EA = ENABLE; // Enable the interrupts again

}



3.4 USB Setup Packet Routine

If the device receives a setup packet from the host, it generates an interruptand assigns VECINT_SETUP_PACKET_RECEIVED to the bVECINTregister. As shown in the previous program, the SetupPacketInterruptHandler() routine was requested. During this routine the NAK sets bothendpoints in case the host attempts to get data from the IN buffer with obsoletedata. It also sets the direction of the current transfer and action in the statusstage before requesting the usbDecodeAndProcessUsbRequest() routine.

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

VOID SetupPacketInterruptHandler(VOID)

{

// copy the MSB of bmRequestType to DIR bit of USBCTL

if((tSetupPacket.bmRequestType & USB_REQ_TYPE_INPUT) == USB_REQ_TYPE_INPUT)

bUSBCTL |= USBCTL_DIR;

else bUSBCTL &= ~USBCTL_DIR;

// SET SIR bit

bUSBCTL |= USBCTL_SIR;

bStatusAction = STATUS_ACTION_NOTHING;

usbDecodeAndProcessUsbRequest();

}

The usbDecodeAndProcessUsbRequest() routine compares the setuppacket buffer with a predefined setup packet list. If any item in the list matchesthe setup packet in the buffer, it executes the routine assigned in the list. Ifthere is not a match in the list and the setup packet is not a vendor or classspecific request, the routine delays the setup packet due to an unsupportedrequest.

VOID usbDecodeAndProcessUsbRequest(VOID)

{

BYTE bMask,bResult,bTemp;

BYTE *pbUsbRequestList;

pbUsbRequestList = (PBYTE)&tUsbRequestList[0];

while(1){

bResult = 0x00;

bMask = 0x80;

// compare all the fields first

for(bTemp = 0; bTemp < 8; bTemp++){

if(*(pbEP0_SETUP_ADDRESS+bTemp) == *(pbUsbRequestList+bTemp)) bResult |=bMask;

bMask = bMask >> 1;

}

// now we have the result

if((*(pbUsbRequestList+bTemp) & bResult) == *(pbUsbRequestList+bTemp)) break;

// advance to next one


3-6

pbUsbRequestList += sizeof(tDEVICE_REQUEST_COMPARE);

}

// check if any more setup packet(s) is in

if(bUSBSTA & (USBSTA_SETUP | USBSTA_STPOW) != 0x00) return;

// now we found the match and jump to the function accordingly.

((ptDEVICE_REQUEST_COMPARE)pbUsbRequestList)−>pUsbFunction();

}

3.5 USB Data Endpoint 0 Routine

If the device receives a data packet from the host, it generates an interrupt andassigns VECINT_INPUT_ENDPOINT0 to the bVECINT register. This samerule applies to send a data packet to the host. Firmware gets an interrupt afterdata is sent to the host.

VOID IEP0InterruptHandler(VOID)

{

tEndPoint0DescriptorBlock.bOEPBCNT = 0x00; // will be set by the hardware

if(bStatusAction == STATUS_ACTION_DATA_IN) usbSendNextPacketOnIEP0();

else tEndPoint0DescriptorBlock.bIEPCNFG |= EPCNF_STALL; // no more data

}

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

VOID OEP0InterruptHandler(VOID)

{

tEndPoint0DescriptorBlock.bIEPBCNT = 0x00; // will be set by the hardware

if(bStatusAction == STATUS_ACTION_DATA_OUT) usbReceiveNextPacketOnOEP0();

else tEndPoint0DescriptorBlock.bOEPCNFG |= EPCNF_STALL; // no more data

}

3.6 USB Data Endpoint 1 Routine

For the OUT endpoint, the application firmware receives data then clears theNAK if more data is required from the host. For the IN endpoint, the applicationfirmware copies data to the IN endpoint buffer, sets buffer size, and clears theNAK bit. The device sends the data back to the host after receiving an IN tokenfrom the host. When the device finishes sending the data, it generates aninterrupt. The application firmware then either sends more data back to thehost or does nothing if data is not available.

tusb2136/tusb3210/tusb5052 usb firmware · pdf filebytes from the host, it sets the byte count...

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