vlsi testing - ece:course pageece322/lectures/lecture25/lecture25.pdfvlsi testing author: radu...
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VLSI Testing
Lecture 2518-322 Fall 2003
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Announcement
Homework 9 is due next Thursday (11/20)
Exam II is on Tuesday (11/18) in class
Review Session:When: Next Monday (11/17) afternoon, 4pm – 6pmWhere: B131, HH
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Outline
Defects and FaultsReasons for IC malfunctioning
Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open)Automatic Test Pattern GenerationPath Delay Fault
Design for Testability
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Why Testing?
Manufacturing is imperfect
Yield (Y) depends on technology, chip area and layout⌧Y decreases as the area of chip is increased⌧Defect density (D)
• Modern technologies yield a value of 1-5 defects/cm2
Yield starts out low (~10%) moves up (95%)
High quality expectationThe earlier you detect a fault, the cheaper it is to fix
chipsofno.TotalwaferonchipsgoodofNo.Y =
5
Reasons for IC Malfunction - Contamination, Defects and Faults
Contamination / Instabilities - Process induced impurities and random fluctuations of process conditions
Defects - Permanent deformation in IC layer which may but does not have to result in fault
Faults - Functional misbehaviors i.e. IC malfunctions
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Reasons for IC Malfunction -Defects and Faults
M10
M9
VDD
13CB
C
13
A
M11
M12
M13
M14
OUTC Contact
P
N1
N2
N13
N13 GND
VDD
BA
Metal
Poly
N+
N
13CB
M28M27
M26
M25
M24M23
GND
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Reasons for IC Malfunction -Defects and Faults
M9M10
M11N1 M12
M13
N3
VDD
M14
M28
M27
N4
GND
M26M25
M24M23
N2
B
A
OUTC
N13
C
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Reasons for IC Malfunction -Defects and Faults
M10
M9
VDD
13CB
13CB
C
13
A
M11
M12
M13
M14
M28M27
M26
M25
M24M23
Metal
Poly
N+
N
Contact
P
GND
OUTC
N1
N2
N13
N13 GND
VDD
BA
M9
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Reasons for IC Malfunction -Defects and Faults
M9
M11 M12 M14
M10
M28
M27
M26M25
M24M23 GND
VDDB
GND
C
M13
A
OUTC
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
00010111
A B C
00010001
yesno
N1 - N13 short
C out
Defect
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Outline
Defects and FaultsReasons for IC malfunctioning
Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open)Automatic Test Pattern GenerationPath Delay Fault
Design for Testability
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Test Complexity
DQ DQ DQ DQ
Combinational Logic
Exhaustive test 2n + mIn“n”
Out
Circuit with n = 25 and m = 501µsec/testExhaustive test time is over 1 billion years!(Registers make life harder!)
clock
Registers“m”
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Testing Strategies
Functional Test: (go/no go)Does the part work?Do this fast & cheap
Diagnostic Test:What in the chip is broken?
Parametric Test:What is:⌧max clock frequency⌧min supply voltage⌧max operating temp
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Test Implementation
Runs Test Vectors/Programs on Device Under Test (DUT)
Goal: Find a SMALL set of test vectors that has a BIG fault coverage
TestersClock rate in the range of GHzResolutions measured in psecLarge very fast memoryCost 1 - 5 million dollars
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Fault Models
• Modeling physical faults is complex
• Need models that simplify the behavior of faults
ab
e
fh
gx
cd
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Stuck-At Fault
ab
e
fh
gx
cd
S-A-1
ab
e
fh
gx
cd
S-A-0Stuck-at-0
Stuck-at-1
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Bridge & Stuck Open
ab
e
fh
gx
cd Bridging
fault
ab
e
fh
gx
cd Open
fault
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Automatic Test Pattern Generation (ATPG)
Given a logic circuit:Generate test program to cover all SA faults
The D-AlgorithmThe D-Calculus⌧Problem: Reconvergent Fanouts
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D-Algorithm
Step 1: Choose a fault to “insert”Select from a fault dictionary
Step 2: Activate (excite) the faultDrive the faulty node to the opposite value of the faultExample: for SA-1, drive the node to 0
Step 3: Sensitize a path to an outputPropagate the fault so that it can be observed at the output pin
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Path Sensitization
Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes)
Out
sa011
0
11 1
0
1Fault enabling
Fault propagation
Techniques Used: D-algorithm, Podem
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D-Algorithm
ab
e
fh
gx
cd
D = 1/0
value ingood ckt
value infaulty ckt
ab
e
fh
gx
cd
S-A-0
D = 0/1
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D-Algorithm
0 1 X D D
1 0 X D D
A X
X =NOT(A)
0 1 X D D
0 0 0 0 0
0 1 X D D
0 X X X X
0 D X D 0
0 D X 0 D
0 1 X D DB
A
X = AB
Five value logic simulation
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D-Algorithm
0 1 X D D
1 1 1 1 1
0 1 X D D
X 1 X X X
D 1 X D 1
D 1 X 1 D
0 1 X D DB
A
X = A + B
Five value logic simulation
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D-Algorithm
ab
e
fh
gx
cd
S-A-0
1/0 = D1
1
11
1
1
D
0
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D-Algorithm
fh
g
1/0 = D1
1
11
1
1
0
Conflict !Need backtracks
ab
xcd
Reconvergent Fanoutx
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Fault Simulation
Fault Free
Circuit
Circuit w/
One Fault
Test Program
Compare
Random Number Generator, Genetic Algorithm, etc.
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Path Delay Fault
A defect can affect the speed of a path in the circuit
Let’s see a Path Delay Fault example
ab
c
de
slow slow
slow11 11
T0 T1+∆T
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Path Delay Fault
Path c-g2-g4-g5-x
g1
g2
g3
g4 g5
00
00
11
00ab xcd
e
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Outline
Defects and FaultsReasons for IC malfunctioning
Fault Modeling Types of faults (Stuck-At, bridge, Stuck Open)Automatic Test Pattern GenerationPath Delay Fault
Design for Testability
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Scan-based Test
Logic
Combinational
Logic
Combinational
Register
Register
OutIn
ScanOutScanIn
A B
Modified to support two operation modes
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Scan Based Methods
Logic Logic LogicR R R R
Level Sensitive Scan Design (LSSD) - IBM
Test Mode: OFF Test Mode: ON
R L R L R R R
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Boundary Scan (JTAG: IEEE 1149.1b)Printed-circuit board
Logic
scan path
normal interconnect
Packaged IC
Bonding Pad
Scan-in
Scan-out
si so
Board testing becomes as problematic as chip testing
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Built-In Self-Testing (BIST)
(Sub)-Circuit
Under
Test
Stimulus Generator Response Analyzer
Test Controller
Rapidly becoming more important with increasingchip-complexity and larger modules
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Linear-Feedback Shift Register (LFSR)
S0 S1 S2
R R R
1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0
Pseudo-Random Pattern Generator