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What is DSA?
Design Goals and Paradigms
The Future
Distributed Swit h Ar hite ture
A.K.A. DSA
Andrew Lunn
1
Vivien Didelot
2
Florian Fainelli
3
1
andrew�lunn. h
2
vivien.didelot�savoirfairelinux. om
3
f.fainelli�gmail. om
Netdev 2.1, 2017
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
Outline
1
What is DSA?
DSA in one Slide
Users of DSA
2
Design Goals and Paradigms
History
Design Goals
Paradigms
The D in DSA
3
The Future
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
DSA in one Slide
Users of DSA
1
What is DSA?
DSA in one Slide
Users of DSA
2
Design Goals and Paradigms
History
Design Goals
Paradigms
The D in DSA
3
The Future
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
DSA in one Slide
Users of DSA
DSA in one Slide
Ethernet switch
Ethernet controller
Port 0
Port 1
Port 2
Port 8
Port 3
Port 4
Port 5
I2C controller
MDIO controller
SPI controller
RJ45
RJ45
RJ45
FiberRJ45
RGMII
CPU
DRAM
RGMII RJ45
RJ45
Data path
Control path
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
DSA in one Slide
Users of DSA
The D in DSA
Switch 2
Switch 1
Switch 0
Ethernet MAC
CPU
MDIO controller
cpu
dsa
dsa dsa
eth0
sw0p1
dsa
sw0p1
sw0p2
sw0p3
sw0p4 sw0p5
sw1p0
sw1p1 sw1p2
sw2p0
sw2p1
sw2p0
sw2p2 sw2p3 sw2p4
Marvell tagged frames
User frames (normal, 802.1q)
Control interface (MDIO, SPI, I2C..)
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
DSA in one Slide
Users of DSA
Wi-Fi A ess Point, Set-top Boxes
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
DSA in one Slide
Users of DSA
Industrial Swit hes/Routers, mostly Transport Industry
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
DSA in one Slide
Users of DSA
Supported Swit hes
Marvell 88E6xxx
Broad om B53 (Roboswit h) and Star Fighter 2
Qual omm QCA8K
Mediatek MT7530 (under review)
Mi ro hip LAN9303 (under review)
WIP driver for Mi ro hip KSZ, not yet ontributed
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
1
What is DSA?
DSA in one Slide
Users of DSA
2
Design Goals and Paradigms
History
Design Goals
Paradigms
The D in DSA
3
The Future
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Added to the kernel in 2008
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Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
History
2008
First ommit, support for some Marvell SOHO swit hes
2014
Broad om SF2, EEPROM, Temperature sensor, EEE, WoL, better PHYLIB
integration, 88E6352
2015
Devi e tree, Hardware bridging, VLANs, Fixup module unload/load, Swit h reset
via GPIO, net onsole
2016
New devi e tree binding, Swit hes as Linux devi es, SPI, MMIO, Broad om B53,
Qual omm QCA8K, 88E6240
2017
88E6390, Se ond generation Star�ghter 2 (BCM7278), TC o�oads, port mirroring
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Alternative approa hes
OpenWrt/LEDE's sw on�g:
Generi netlink based on�guration
Does not make use of swit h tags, uses VLAN tags for tra� segregation
No per-port network interfa es
Ea h swit h driver is allowed to extend the ontrol API: no onsisten y a ross
devi e drivers
Proposed as a solution in O tober 2013: https://lwn.net/Arti les/571390/
Dis ussion starting point that led to swit hdev!
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Other approa hes
Other approa hes:
Qui k-n-dirty /pro , /sys/, debugfs, io tl() interfa es from various SoC vendors
Vendor spe i� and proprietary swit h SDK in user spa e
Have the bootloader on�gure the swit h!
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
The Swit h as a Hardware A elerator
During various onferen e orridor side dis ussions around 2014 it was de ided how to
model Swit hes
Swit h ports are Linux network interfa es
Standard Linux tools used to on�gure interfa es, ip(8), if on�g(8)
Linux bridge on ept used for bridging interfa es, ip(8), bridge(8), brt tl(8)
Linux team/bonding on ept for port trunks,
The swit h just a elerates what Linux an already do
DSA has been doing this sin e 2008!
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
The Data Plane
DSA provides the data plane
Linux slave Interfa e for ea h port
Tagging proto ols, to dire t frames from the SoC to a spe i� port
Taggers for Marvell DSA & EDSA, Broad om and Qual om, plus generi trailer
TX: Slave interfa e -> tagger -> master interfa e -> Swit h
RX: master interfa e netif_re eive_skb() -> tag parser, slave interfa e sele tion
-> netif_re eive_skb
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Ethernet frame pro essing
M�� �� M�� �� Ether type Payload FCS
MAC DA MAC SA Ether type Payload FCSSwitch tag
Source portMetadataEgress type
Destination portsMetadataIngress type
Normal Ethernet frame
Ingress tagged (CPU towards switch) frame
MAC DA MAC SA Ether type Payload FCSSwitch tag
Egress tagged (switch towards CPU) frame
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Network sta k �ow
Network driverRX path
skb�dev = eth0
netif_receive_skb()
eth_type_trans()
netdev_uses_dsa()?
ip_rcv()
XX_tag_rcv()
Switch port valid?
skb�dev = sw0p0
Driver/HW layer Layer agnostic
Ethernet layer
Layer 3
DSA tag layer
Discard
Yes
Yes
No
No
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
The Control Plane
About SWITCHDEV:
Stateless framework in the kernel under net/swit hdev/
Provides the ontrol knobs within the networking sta k to push o�oads towards
spe ialized devi es (swit hdev_ops)
Provides an abstra t model of obje ts (VLANs, FDBs, MDBs,) to be pushed to
these devi es (swit hdev_obj)
Is not a devi e driver model: no stri t de�nition of what a swit h devi e is
Only operates at the network devi e (net_devi e) layer
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
The Control Plane
DSA vs. SWITCHDEV:
Stateful framework under net/dsa/
Colle tion of vendor-spe i� swit h tags: Marvell, Broad om, Qual omm, Mediatek
Provides an abstra ted model of a swit h: dsa_swit h and a olle tion of
swit hes: dsa_swit h_tree
Binds network devi es (netdev_ops), ethtool (ethtool_ops) and swit h drivers
together
Well de�ned devi e (Devi e Tree) and driver model (dsa_swit h_ops)
Implements swit hdev_ops for supported o�oads: bridge, VLAN, FDB, MDB
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Cross- hip on�guration
Switch 2Switch 1Switch 0
CPU
sw0p0 sw0p1 sw0p2 sw1p0 sw1p1 sw1p2 sw2p1sw2p0 sw2p2
Marvell tagged frames
Bridge membership
Bridge br0
sw2p3sw2p4sw1p3sw1p4sw0p3sw0p4
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Cross- hip on�guration
Current behavior:
Inter onne ted swit h hips reate a swit h fabri
DSA drivers manage single hip (stru t dsa_swit h)
DSA links on�gured to pass frames to any port
Problem?
br0 bridging? Swit hes an potentially leak ross- hip frames!
br0 VLAN 42? Swit h 1 won't pass tra� !
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
History
Design Goals
Paradigms
The D in DSA
Cross- hip on�guration
Solutions?
Cross- hip bridging (DONE):
DSA ore noti�es drivers about fabri bridge events ( ross hip_bridge_{join,leave}
ops)
mv88e6xxx on�gure Cross- hip Port Based VLAN Table (PVT, Marvell spe i� )
Cross- hip VLAN (WIP):
DSA ore noti�es drivers about swit hdev port obje ts (VLAN, FDB, MDB) so that
drivers allow tra� to pass
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
1
What is DSA?
DSA in one Slide
Users of DSA
2
Design Goals and Paradigms
History
Design Goals
Paradigms
The D in DSA
3
The Future
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
Hopefully oming soon
Multiple CPU ports
Often seen in Wi-Fi devi es to double SoC <-> Swit h Bandwidth
Often one CPU port stati ally mapped to �WAN� port
Depends on hipset features, we an do better, load balan ing
IGMP snooping on bridges
Better distributed swit h support for Marvell devi es
Better support for Fiber interfa es
Mediatek driver merged
Mi ro hip drivers merged
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
Maybe Later???
Team/bonding?
TCAM support for o�oading part of the �rewall?
Qual omm Hardware NAT?
More Vendor supported development?
Metering, broad ast storm suppression, QoS (priorities, maps) o�oads again
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA
What is DSA?
Design Goals and Paradigms
The Future
Questions
Questions???
Andrew Lunn, Vivien Didelot, Florian Fainelli DSA