01 verilog introduction

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Digital System Design

VerilogHDL

Maziar Goudarzi


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2005 Verilog HDL 2

Today program

History of VerilogHDL

Overview of Digital Design with VerilogHDL

Hello World!

Hierarchical Modeling Concepts


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2005 Verilog HDL 3

History of VerilogHDL

Beginning: 1983

Gateway Design Automation company

Simulation environment

Comprising various levels of abstraction

Switch (transistors), gate, register-transfer, and higherlevels


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2005 Verilog HDL 4

History of VerilogHDL (contd)

Three factors to success of Verilog

Programming Language Interface (PLI)

Extend and customize simulation environment

Close attention to the needs of ASIC foundries

Gateway Design Automation partnership with

Motorola, National, and UTMC in 1987-89

Verilog-based synthesis technology

Gateway Design Automation licensed Verilog to

Synopsys

Synopsys introduced synthesis from Verilog in 1987


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2005 Verilog HDL 5


VHDL

VHSIC (Very High Speed Integrated Circuit)

Hardware Description Language

Developed under contract from DARPA

IEEE standard

Public domain

Other EDA vendors adapted VHDLGateway put Verilog in public domain


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2005 Verilog HDL 6


TodayMarket divided between Verilog & VHDLVHDL mostly in Europe

Verilog dominant in USVHDLMore general language

Not all constructs are synthesizable

Verilog:Not as general as VHDL

Most constructs are synthesizable


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VerilogHDL

Overview of Digital DesignUsing Verilog


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2005 Verilog HDL 8

Overview of Digital Design Using Verilog

Evolution of Computer-Aided Digital Design

Emergence of HDLs

Typical Design Flow

Importance of HDLs

Popularity of Verilog HDL

Trends in HDLs


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2005 Verilog HDL 9

Evolution of Computer-Aided DigitalDesign

SSI: Small scale integrationA few gates on a chip

MSI: Medium scale integration

Hundreds of gates on a chip LSI: Large scale integrationThousands of gates on a chip

CAD: Computer-Aided Design

CAD vs. CAE

Logic and circuit simulators

Prototyping on bread board

Layout by hand (on paper or a computer terminal)


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Evolution of Computer-Aided DigitalDesign (contd)

VLSI: Very Large Scale IntegrationHundred thousands of gates

Not feasible anymore:

Bread boarding

Manual layout design

Simulator programs

Automatic place-and-route

Bottom-Up design

Design small building blocksCombine them to develop bigger ones

More and more emphasis on logic simulation


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2005 Verilog HDL 11

Emergence of HDLs

The need to a standardized language forhardware description

Verilogand VHDL

Simulators emergedUsage: functional verification

Path to implementation: manual translation into gates

Logic synthesis technology

Late 1980s

Dramatic change in digital design

Design at Register-Transfer Level (RTL) using an HDL


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2005 Verilog HDL 12

Typical Design Flow (in 1996)

1. Design specification

2. Behavioral description

3. RTL description

4. Functional verification and testing

5. Logic synthesis

6. Gate-level netlist

7. Logical verification and testing

8. Floor planning, automatic place & route

9. Physical layout

10. Layout verification

11. Implementation


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2005 Verilog HDL 13

Typical Design Flow (contd)

Most design activity

In 1996:

Manually optimizing the RTL design

CAD tools take care of generating lower-level details

Reducing design time to months from years

Today

Still RTL is used in many cases

But, synthesis from behavioral-level also possible

Digital design now resembles high-level computerprogramming


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2005 Verilog HDL 14

Typical Design Flow (contd)

NOTE:

CAD tools help, but the designer still has the

main role

GIGO (Garbage-In Garbage-Out) concept

To obtain an optimized design, the designer needs toknow about the synthesis technology

Compare to software programming and compilation


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2005 Verilog HDL 15

Importance of HDLs

Retargeting to a new fabricationtechnology

Functional verification earlier in the designcycle

Textual concise representation of thedesign

Similar to computer programs

Easier to understand


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2005 Verilog HDL 16

Popularity of Verilog HDL

Verilog HDL

General-purpose

Easy to learn, easy to use

Similar in syntax to CAllows different levels of abstraction and mixing them

Supported by most popular logic synthesis tools

Post-logic-synthesis simulation libraries by all fabrication

vendorsPLI to customize Verilog simulators to designers needs


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2005 Verilog HDL 17

Trends in HDLs

Design at behavioral level

Formal verification techniques

Very high speed and time critical circuitse.g. microprocessors

Mixed gate-level and RTL designs

Hardware-Software Co-designSystem-level languages: SystemC, SpecC,


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VerilogHDL

Hello World!


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2005 Verilog HDL 19

Basics of Digital Design Using HDLs

Circuit Under Design(CUD)

84

Generatinginputsto CUD

Checkingoutputsof CUD

Test bench

Stimulus block


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2005 Verilog HDL 20

ModelSimSimulation Environment

Youll see in the laboratory


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2005 Verilog HDL 21

Verilog Basic Building Block

Module

module not_gate(in, out); // module name+ports

// comments: declaring port typeinput in;

output out;

// Defining circuit functionality

assign out = ~in;

endmodule


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2005 Verilog HDL 22

uselessVerilog Example

module useless;

initial

$display(Hello World!);

endmodule

Note the message-display statementCompare to printf() in C


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VerilogHDL

Hierarchical Modeling Concepts


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2005 Verilog HDL 24

Design Methodologies


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2005 Verilog HDL 25

4-bit Ripple Carry Counter


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T-flipflop and the Hierarchy


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Modules

module();

...

...

endmodule

Example:module T_ff(q, clock, reset);

...

...

endmodule


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Modules (contd)

Verilog supported levels of abstraction Behavioral (algorithmic) level

Describe the algorithm used

Very similar to C programming

Dataflow level

Describe how data flows between registers and is processed

Gate level

Interconnect logic gates

Switch level

Interconnect transistors (MOS transistors)

Register-Transfer Level (RTL)Generally known as a combination of behavioral+dataflow that is

synthesizable by EDA tools


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Instances

module ripple_carry_counter(q, clk, reset);

output [3:0] q;

input clk, reset;

//4 instances of the module TFF are created.

TFF tff0(q[0],clk, reset);

TFF tff1(q[1],q[0], reset);



endmodule


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Instances (contd)

module TFF(q, clk, reset);output q;

input clk, reset;

wire d;

DFF dff0(q, d, clk, reset);

not n1(d, q); // not is a Verilog provided primitive.

endmodule

// module DFF with asynchronous reset

module DFF(q, d, clk, reset);

output q;

input d, clk, reset;

reg q;

always @(posedge reset or negedge clk)

if (reset)

q = 1'b0;

else

q = d;

endmodule


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2005 Verilog HDL 31

Instances (contd)

Illegal instantiation example: Nestedmodule definition not allowed Note the difference between module definitionand module instantiation

// Define the top level module called ripple carry

// counter. It is illegal to define the module T_FF inside

// this module.module ripple_carry_counter(q, clk, reset);

output [3:0] q;

input clk, reset;

module T_FF(q, clock, reset);// ILLEGAL MODULE NESTING

:

:

endmodule // END OF ILLEGAL MODULE NESTING

endmodule


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Simulation- Test Bench Styles


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Example

Design block was shown before

ripple_carry_counter, T_FF, and D_FF modules

Stimulus block


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Example (contd)

module stimulus;reg clk; reg reset; wire[3:0] q;

// instantiate the design block

ripple_carry_counter r1(q, clk, reset);

// Control the clk signal that drives the design block.

initial clk = 1'b0;always #5 clk = ~clk;

// Control the reset signal that drives the design block

initial

begin

reset = 1'b1;

#15 reset = 1'b0;

#180 reset = 1'b1;#10 reset = 1'b0;

#20 $stop;

end

initial // Monitor the outputs

$monitor($time, " Output q = %d", q);

endmodule


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What we learned today

History of Verilog HDL

Principles of digital design using HDLs

Our first Verilog design example


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Other Notes

Course web-page

http://ce.sharif.edu/courses

Exercise 1

Install and use ModelSim in the lab. to simulateripple_carry_counter example

Chapter 2 exercises

01 verilog introduction

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