AT91SAMARM-basedEmbedded MPU

Application Note

11127A–ATARM–23-Sep-11

MLC NAND Flash Support inSAM9G15/G25/G35/X25/X35

Microcontrollers with PMECC Controller

1. IntroductionThe purpose of this application note is to introduce the NAND Flash technology and todescr ibe how to in te r face NAND Flash memory to Atme lSAM9G15/G25/G35/X25/X35 microcontrollers. The SAM9G15/G25/G35/X25/X35microcontroller family features an External Bus Interface (EBI) providing NAND Flashprotocol support via the Static Memory Controller (SMC) and integrated logic circuitry.It also contains a Programmable Multi-bit ECC Controller (PMECC) which is used togenerate redundancy information for both Single-Level Cell (SLC) and Multi-level Cell(MLC) NAND Flash devices. In addition, read bandwidth has been measured accord-ing to the number of data errors that have voluntarily been inserted into the NANDFlash memory device in order to estimate the impact of the PMECC correction algo-rithm on the read performance.

2. ReferencesFor any details on NAND Flash programming with SAM-BA tool, refer to AT91 ISP/SAM-BAUser Guide.

3. NAND Flash Device Overview

3.1 Internal Array ArchitectureThe NAND Flash array is organized in a series of blocks which are divided in several pages.Data is stored either in byte (8 bits) or half-word (16 bits) format depending on the device type.Each page consists of a main area for storing data and a spare area (physically similar) typicallyused for data error identification and correction, wear levelling, etc.

One particularity of NAND Flash devices is that they may contain a percentage of invalid blocksin the memory array. The NAND Flash manufacturer identifies and marks the bad blocks as"Invalid blocks". This information is stored in the block spare area (1st or 2nd page of the block).The existence of bad blocks does not affect the good ones because each block is independentand individually isolated from the bit lines by block select transistors. As NAND Flash deviceshave a finite lifetime (approximately 100 000 write/erase cycles), additional invalid blocks maydevelop while being used. Storing data requires bad-block management and data error identifi-cation and correction.

3.2 SLC and MLC NAND FlashThere are two primary types of NAND Flash technologies: Single-Level Cell (SLC) and Multi-Level Cell (MLC). Multi-Level Cell was developed more recently to achieve a higher bit density inorder to create a flash chip with a greater capacity, for a given die size.

• SLC (Single-Level Cell)

– One bit of information is held in each memory cell.

– SLC devices are used in the majority of high-performance media-card and wireless-processor applications.

• MLC (Multi-Level Cell)

– Devices store two or more bits per cell.

– MLC can produce the same storage capacity as SLC but using a smaller die, andtherefore at a lower cost.

– MLC lacks the speed.

– MLC devices are typically used in consumer and other low-cost products.

The error rate for MLC Flash is very high as compared to that of the SLC, so at least 2- or 4-bitECC is required vs. 1-bit ECC for SLC. Most of software ECC algorithms are too slow; however,the built-in PMECC module is sufficient to support MLC.

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Application Note

Application Note

4. Hardware Interface

4.1 EBI for NAND Flash

4.1.1 NAND Flash SignalsThe NAND Flash hardware interface requires a maximum of 24 pins for 16-bit devices.

Table 4-1. Pin Description for Nand Flash Device

Pin Symbol Pin Description Explanation

CE Chip Enable

CE is active when asserted LOW to enable or select thedevice. CE pin must remain LOW during busy periods in orderto prevent the device from entering standby mode, thusstopping the read operation in mid cycle. A subset of NANDFlash devices supports the CE# “Don’t Care” option whichallows deselecting the device without terminating the operationin progress. Other devices on the same memory bus can thenbe accessed while the NAND Flash is busy with internaloperations.

WE Write EnableThe WE input controls writes to the I/O port. Commands,address and data are latched on the rising edge of the WEpulse.

RE Read Enable RE enables the output data buffers.

CLECommand LatchEnable

When CLE is HIGH, commands are latched into the NANDFlash command register on the rising edge of the WE signal.

ALEAddress LatchEnable

When ALE is HIGH, addresses are latched into the NANDFlash address register on the rising edge of the WE signal.

I/O[7:0]orI/O[15:0]

Input/Output Bus

The I/O pins are used for input commands, address and data,and to output data during read operations. The I/O pins float tohigh-z when the chip is deselected or when the outputs aredisabled. I/O[15:8] are used only in an X16 organizationdevice. Since command input and address input are X8operations, I/O[15:8] are not used to input command andaddress. I/O[15:8] are used only for data input and output.

WP Write ProtectThe WP pin provides inadvertent write/erase protection duringpower transitions. The internal high voltage generator is resetwhen the WP pin is active low.

R/B Ready/Busy

If the NAND Flash device is busy with an ERASE, PROGRAM,or READ operation, the R/B signal is asserted LOW. The R/Bsignal is an open drain output and requires a pull-up resistor tobe correctly read.

PRE

Power-on readenable(used for systemboot)

The PRE pin controls auto read operations executed duringpower on. The power-on auto read is enabled when the PREpin is tied to high level.

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4.1.2 Standard and “CE don’t care” NAND Flash

4.1.2.1 Chip Select SignalCE# is used to enable the device. When CE# is low and the device is not in the busy state, theFlash memory accepts command, data, and address information. When the device is not per-forming an operation, the CE# pin is typically driven HIGH and the device enters standby mode.The memory enters standby mode if CE# goes HIGH while data is being transferred and thedevice is not busy.

4.1.2.2 Standard NANDFor standard NAND, the CE signal remains asserted even when NANDCS is not selected, pre-venting the device from returning to standby mode. In this case, a PIO line should be dedicatedto drive the Chip Enable signal.

4.1.2.3 CE# “Don’t Care” NANDA subset of NAND Flash supports the CE# “Don’t Care” operation allowing the NAND Flash toreside on the same asynchronous memory bus as other Flash or SRAM devices. Other deviceson the memory bus can then be accessed while the NAND Flash is busy with internal opera-tions. For “CE don’t care” NAND, the chip enable state is “don’t care” during the busy periodpreceding the data read cycle. This capability is important for designs that require multiple mem-ory devices on the same bus. One device can be programmed while another is being read.

4.1.3 External Bus InterfaceThe External Bus Interface (EBI) is designed to ensure successful data transfer between severalexternal devices such as DDR, SDRAM, PMECC and NAND Flash and the embedded MemoryController of an ARM-based device. The EBI supports NAND Flash protocols thanks to inte-grated circuitry that greatly reduces the requirements for external components.

The NAND Flash logic is driven by the Static Memory Controller (SMC) on the NCS3 addressspace. Programming the CS3A field in the EBI_CSA Register in the Bus Matrix User Interface tothe appropriate value enables the NAND Flash logic. For details on this register, refer to the BusMatrix User Interface section in the product datasheet. Access to an external NAND Flashdevice is then made by accessing the address space reserved to NCS3 (i.e., between0x40000000 and 0x4FFFFFFF).

The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOEand NANDWE signals when the NCS3 signal is active. (Refer to the Static Memory Controllersection in the product datasheet). The Address Latch Enable and Command Latch Enable sig-nals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus.The command, address or data words on the data bus of the NAND Flash device are distin-guished by using their address within the NCS3 address space. The Chip Enable (CE) signal ofthe device and the Ready/Busy (R/B) signal are connected to PIO lines.

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Application Note

Application Note

4.2 HW Pin Connection Examples

4.2.1 NAND Flash Signals Connection to EBIThe pins used for interfacing the Static Memory Controller may be multiplexed with the PIOlines. The programmer must first program the PIO controller to assign the Static Memory Con-troller pins to their peripheral functions.

Notes: 1. A switch, NFD0_ON_D16, enables the user to select NAND Flash path on D0-D7 orD16-D23 depending on memory power supplies. This switch is located in theEBICSA register in the Bus Matrix user interface.

2. For standard NAND Flash, since the Static Memory Controller (SMC) asserts theNANDCS signal High when NANDOE and NANDWE are invalidated, it is necessaryto connect the CE pin of the NAND Flash device to a GPIO line in order to hold it lowduring the busy period preceding data read out. For “CE don’t care” NAND Flash,NANDCS signal can be directly connected to the CE pin of the NAND Flash device.

3. Ready/Busy (R/B) signals are connected to PIO lines, or disconnected; in this case,The READ STATUS (70h) command can be used to determine when the device isready.

4.2.2 NAND Flash Databus SelectionNAND Flash data bus can be connected to D0-D7 or D16-D23 depending on memory powersupplies. This switch is located in the EBICSA register in the Bus Matrix user interface.

4.2.2.1 8-bit NAND Flash with NFD0_ON_D16 = 0NAND Flash I/Os are connected to D0-D7 in case VDDIOM is equal to VDDNF. This is done byclearing NFD0_ON_D16 bit in EBI Chip Select Assignment Register (CCFG_EBICSA). At reset,NFD0_ON_D16 = 0 and NAND Flash bus is connected to D0-D7.

4.2.2.2 8-bit NAND Flash with NFD0_ON_D16 = 1NAND Flash I/Os are connected to D16-D23 in case VDDIOM is not equal to VDDNF. This isdone by setting NFD0_ON_D16 bit in EBI Chip Select Assignment Register (CCFG_EBICSA).

NAND Flash I/Os are connected to D16-D31 in case VDDIOM is different from or equal toVDDNF. This can be used if the SMC connects to the NAND Flash only.

Using this function with another device on the SMC will lead to an unpredictable behavior of thatdevice. In that case, the default value must be selected.

Table 4-2. EBI Signals Example for SAM9G15/G25/G35/X25/X35 connection toMT29F2G08AAD NAND Flash

Signal Name Function Type Active LevelNANDSignal

NFD0-NFD15 (1) NAND Flash I/O I/O I/O 0-7

NANDCS (2) NAND Flash Chip Select Output Low CE

NANDOE NAND Flash Output Enable Output Low RE

NANDWE NAND Flash Write Enable Output Low WE

A22/NANDCLE Command Latch Enable Output High CLE

A21/NANDALE Address Latch Enable Output High ALE

PIO (3) Ready/Busy Input Low R/B

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4.2.3 DDR2 with NAND Flash (Multi-port)The product embeds a multi-port DDR2SDR Controller. This allows to use three additional portson DDR2SDRC to lessen the EBI load from a part of DDR2 or LP-DDR accesses. Thisincreases the bandwidth when DDR2 and NAND Flash devices are used. This feature is NOTcompatible with SDR or LP-SDR Memory.

Figure 4-1. Clear EBICSA.DDR_MP_EN (bit 25) to disable multi-port.

Figure 4-2. Set EBICSA.DDR_MP_EN (bit 25) to enable multi-port, and performance isincreased.

4.3 Basic Operation Principle (Introduce raw data access)NAND Flash operations are fully controlled through a multiplexed I/O interface and additionalcontrol signals. Commands, addresses and data are transferred through the external input/out-put bus (8-bit or 16-bit) to the dedicated internal registers. In 16-bit devices, commands,addresses and data use the lower 8 bits (7-0). The upper 8 bits are only used during data-trans-fer cycles. Read and program operations are performed on a per page basis whereas eraseoperations are performed on a block basis. To read or write from NAND Flash, a commandsequence is issued to select a block and a page. After this selection, the entire page can be reador written. The command sequence normally consists of a Command Latch Cycle, an AddressLatch Cycle and a Data Cycle - either read or write.

BusMatrix

DDR2SDRC

not used

not used

Port 0

EBI

(LP-)SDRDevice

NAND FlashDevice

not used

BusMatrix

DDR2SDRC

Port 2

Port 1

Port 0

EBI

DDR2 or LP-DDRDevice

NAND FlashDevice

Port 3

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Application Note

Application Note

5. PMECC and PMERRLOC Module

5.1 What is ECC?NAND devices are subject to data failures that occur during device operation. To ensure dataread/write integrity, system error-checking and correction (ECC) algorithms must be imple-mented. The embedded ECC controller and related decoding software are capable ofgenerating redundancy for correction of single or multiple bits of data.

5.2 BCH AlgorithmBinary BCH codes were first discovered by A. Hocquenghem in 1959 and independently by R.C.Bose and D.K. Ray-Chaudhuri in 1960. BCH codes are a family of cyclic codes, with an alge-braic structure which is useful to simplify the encoding and decoding procedures. Binary BCHcodes with minimum distance 3 are better known as Hamming codes. BCH codes are a general-ization of Hamming codes for multiple error correction, which have been a very popular choice inmemory devices, because of their simple and fast encoding and decoding procedures.

The PMECC Controller embedded in SAM9G15/G25/G35/X25/X35 microcontroller is a pro-grammable binary BCH encoder/decoder.

5.3 Programmable Multi-bit ECC Controller (PMECC)

5.3.1 PMECC Preliminary Parameters Configuration

5.3.1.1 Programmable Sector Size & Number of Sectors Per PageOnly 8-bit data bus NF is supported. The NAND Flash sector size is programmable and can beset to 512 bytes or 1024 bytes by writing the SECTORSZ field in the PMECC_CFG register. TheECC computation is based on this configuration. Number of sectors per page can be 1, 2, 4 or 8sectors depending on page size of NAND Flash device. It can be set by writing the PAGESIZEfield in PMECC_CFG.

Table 5-1 gives an overview of all supported PAGESIZE & SECTORSZ configurations on differ-ent page size (512/1024/2048/4096/8192 bytes). Some paths are forbidden and shown as “-” inthe table.

Table 5-1. Supported PAGESIZE & SECTORSZ Configuration on Different Page Size(512/1024/2048/4096/8192 bytes)

Sector Size 512 Bytes Sector Size 1024 Bytes

Sectors Per Page 1 2 4 8 1 2 4 8

Page Size 512 X - - - - - - -

Page Size 1024 - X - - X - - -

Page Size 2048 - - X - - X - -

Page Size 4096 - - - X - - X -

Page Size 8192 - - - - - - - X

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5.3.1.2 Programmable Error Correcting Capability and Spare SizePMECC supports 2, 4, 8, 12 and 24 bits of errors per sector correcting. It can be set by writingthe BCH_ERR field in the PMECC_CFG register. The PMECC module generates redundancy atencoding time. The PMECC redundancy value can be read in PMECC_ECCx.

Table 5-2 shows the number of relevant ECC bytes per sector with different correctingcapability.

When a NAND write page operation is performed, the N-byte redundancy should be appendedto the page and written in the spare area. The size of the spare area should be preliminarily con-figured in the PMECC_SAREA register.

N = Number of ECC bytes x Sectors Per Page

For example, NAND Flash page size is 2048 bytes. Configure 512-byte sector size, correct 4-biterrors, and then the number of ECC bytes is 7 (See Table 5-2).

N = 7 x 4 = 28

Table 5-3 gives an example of the supported correcting capability configuration on differentpage sizes (512/1024/2048/4096/8192 bytes). However, some cases are not supported, such as12-bit error correction on 2048 page size NAND Flash. The size of ECC redundancy is 80 bytes,and there is not enough space in the spare area (total 64 bytes) to be written. In such a case, itis shown as “-” in the table.

5.3.1.3 Programmable ECC Area Start Address and End AddressECC Area contains the redundancy value which is generated by PMECC and is appended to thepage and written in ECC area by the processor.

The Start address indicates the first byte address of the ECC area. Location 0 matches the firstbyte of the spare area. It is programmable by writing PMECC_SADDR register. And the Endaddress indicates the last byte address of the ECC area. It is programmable by writingPMECC_EADDR register.

End Address = Start Address + Total number of ECC bytes

Table 5-2. Number of Relevant ECC Bytes Per Sector

Sector Size 512 Bytes Sector Size 1024 Bytes

Correcting Capability 2 4 8 12 24 2 4 8 12 24

Number of ECC Bytes 4 7 13 20 39 4 7 14 21 42

Table 5-3. Example of Correcting Capability Configuration on Different Page Size(512/1024/2048/4096/8192 bytes)

Sector Size 512 Bytes Sector Size 1024 Bytes

Correcting Capability 2 4 8 12 24 2 4 8 12 24

Page Size 512 + 16 4 7 13 - - - - - - -

Page Size 1024 + 32 8 14 26 - - 4 7 14 21 -

Page Size 2048 + 64 16 28 52 - - 8 14 28 42 -

Page Size 4096 + 224 32 56 104 160 - 16 28 56 84 168

Page Size 8192 + 256 - - - - - 32 56 112 168 -

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Application Note

Application Note

For example, NAND Flash page size is 2048 bytes. Sector size is 512 bytes. Correct 4-bit errors,and the number of ECC bytes is 7 (See Table 5-2), and the total number of ECC bytes is 28bytes (See Table 5-3). If the Start address of ECC area is set as 2, the End address of ECC areais 2 + 28 = 30.

Note: If the End address value is larger than the spare area size of NAND Flash device, it will lead to anunpredictable behavior.

5.3.2 How Does PMECC Work?

5.3.2.1 Write Page with PMECC Enable

• PMECC Preliminary Parameters Configuration (see details in Section 5.3.1)

– Configure sector size

– Configure number of sectors per page

– Configure Error Correcting Capability

– Configure Start and End address of ECC area and spare size

• Enable PMECC Module

– Set the ENABLE bit in PMECC_CTRL (PMECC module must always be configuredbefore being activated)

– Set the NANDWR bit in PMECCFG to enable a NAND write access

– When the NAND spare area contains file system information and redundancy(PMECCx), the spare area is error protected, and then the SPAREEN bit inPMECCFG is set to one.

• Perform NAND Flash Write Page Operation

– Issue PROGRAM PAGE command (0x80)

– Issue address

– Turn to DATA phase by setting the DATA field in PMECC_CTRL

– Move the NAND Page to external Memory whether using DMA or Processor

– The PMECC calculation starts once the required address cycles are performed tothe NAND Flash

– The PMECCx (x depends on BCH_ERR and SECTORSZ) is refreshed at each writeaccess of the sector (depends on the sector size and number of sectors per page)until the last byte of the main area is written

– Wait for the BUSY bit to be cleared in the PMECC_SR register to make sure allredundancy in PMECCx is ready

– Copy redundancy from PMECCx to user-defined spare area using DMA orProcessor

– Retrieve all redundancy in PMECCx

– Issue RANDOM DATA INPUT command (0x85)

– Issue address (Page size + Start address of ECC area)

– Issue PROGRAM (10h) command after the data input is complete

– Wait until NAND Flash operation is completed

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Figure 5-1. ECC Calculation During Page Write Sequence with Random Write Spare Area

5.3.2.2 Read Page with PMECC Enable

• PMECC Preliminary Parameters Configuration (see details in Section 5.3.1)

– Configure sector size

– Configure number of sectors per page

– Configure Error Correcting Capability

– Configure Start and End address of ECC area and spare size

• PMERRLOC Preliminary Parameters Configuration (see details in Section 5.4.1)

– Configure sector size

• Enable PMECC Module

– Set ENABLE bit in PMECC_CTRL (PMECC module must always be configuredbefore being activated)

– Clear the NANDWR bit in PMECCFG to enable a NAND read access

– When the NAND spare area contains file system information and redundancy(PMECCx), the spare area is error protected, and then the SPAREEN bit inPMECCFG is set to one.

– Set the AUTO bit in PMECCFG (if the SPAREEN bit is cleared)

• Perform NAND Flash Read Page Operation

– Issue READ command (0x00)

– Issue address and command (0x30)

– If the READ STATUS command is used to monitor the data transfer, the user mustre-issue the READ PAGE (0x00) command to receive data output from the NANDdevice.

– Turn to DATA phase by setting the DATA field in PMECC_CTRL

– Move the NAND Page from external Memory whether using DMA or Processor

– If the spare area is protected, when the page has been fully retrieved from theNAND, the ECC area is read using the user mode by writing one to the USER field inPMECC_CTRL.

– If the spare area is not protected, the data size to be read should be the size of themain page plus x (x = End address of ECC area).

– If the spare area is protected, the data size to be read should be the size of the mainpage plus the size of the spare area.

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Application Note

Application Note

– The PMECC Remainder computation starts once the required address cycles areperformed to the NAND Flash

– The PMECC_REMx (x depends on BCH_ERR and SECTORSZ) is generated(depends on the sector size and the number of sectors per page)

– Retrieve the whole sectors in a page from the NAND

– Wait for the BUSY bit to be cleared in PMECC_SR to make sure all remainder inPMECCx is ready

– When all polynomial remainders for a given sector are set to zero, no error occurs.

– When the polynomial remainders are different from zero, the codeword is corruptedand further processing is required.

– Read the PMECCISR to indicate which sector is corrupted

– When set to one, bit i of the PMECCISR register indicates that sector i is corrupted.

– When ECC error is corrupted, how to find the error position can be very software-intensive (see introduction in Section 5.5)

Figure 5-2. ECC Remainder Generation during Page Read

5.4 Programmable Multi-bit ECC Error Location (PMERRLOC)The PMECC Error Location Controller provides hardware acceleration for determining roots ofpolynomials over two finite fields: GF(2^13) and GF(2^14).

5.4.1 PMERRLOC Preliminary Parameters Configuration

5.4.1.1 Programmable Sector SizeThe NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes by writ-ing the SECTORSZ field in PMERRLOC_ELCFG. It must be the same as the configuration ofSECTORSZ field in PMECC_CFG in order to have the same ECC computation base for ECCredundancy generation and error correction.

5.4.1.2 Primitive PolynomialThe primitive polynomial value can be retrieved from RLOC_ELPRIM register. After reset, theprimitive polynomial value is 0x201B, and at that time the sector size is 512 bytes (useGF(2^13)). if the SECTORSZ bit is set in PMERRLOC_ELCFG to configure the sector size as1024 bytes (use GF(2^14)), the primitive polynomial value is 0x4443.

5.4.1.3 What is a Primitive Polynomial?There is a primitive element , so that every nonzero element in can beexpressed as . This element is the root of an irreducible polynomial,called a primitive polynomial, over {0, 1}, that is, . A primitive element of the

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field GF(2m) satisfies the equation , and is the smallest positive integer,so that .

5.4.1.4 Why does PMERRLOC Provide the Value of the Primitive Polynomial?The primitive polynomial in is not always a unique value. In order to sync with the BCHalgorithm of HW PMECC, the software must use the same primitive polynomial in algorithm.

5.4.1.5 What’s the Meaning of 0x201B and 0x4443?0x201B = 0010000000011011b = .This is a primitive polynomial for .

0x4443 = 0110011001100011b = .This is a primitive polynomial for .

All primitive elements in can be constructed from the primitive polynomial.

For example, use primitive polynomial to construct

or

use primitive polynomial to construct .

5.4.1.6 What are gf_log and gf_antilog Tables in the Datasheet?gf_log and gf_antilog are two lookup tables, which help the software to implement complexexponent operations.

Let be the primitive element of .

If , then and .

Consider with primitive polynomial , and . The gf_log andgf_antilog tables are as follows:

The PMECC library contains 2 sets of lookup tables named pmecc_gf_512[2] andpmecc_gf_1024[2]. pmecc_gf_512 can be used for 512 bytes BCH algorithm in GF(213) Galoisfield, and pmecc_gf_1024 can be used for 1024 bytes BCH algorithm in GF(214) Galois field.These two tables are generated from two primitive polynomials, as mentioned above.

x gf_antilog(x) gf_log(x)

0 1 -1

1 2 0

2 4 1

3 3 3

4 6 2

5 7 6

6 5 4

7 1 5

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Application Note

Application Note

5.5 BCH Code Encoding and DecodingThe encoder computes the redundancy in programming time. The decoder computes the syn-drome polynomial and syndrome values. To find the error-locator polynomial, apply theBerlekamp iterative algorithm. Finally, finding the root of the error location polynomial, this stepcan be done by PMERRLOC hardware accelerator. For details on this topic, refer to Section“Software Implementation” of PMECC Datasheet.

In addition, this section introduces some basic knowledge of BCH code and how to implement itby PMECC and PMERRLOC module mixed with related software.

5.5.1 Basic Concepts of Error Correcting CodingAll error correcting codes are based on the same basic principle: redundancy is added to infor-mation in order to correct any errors that may occur in the process of transmission or storage. Ina basic (and practical) form, redundant symbols are appended to information symbols to obtaina coded sequence or codeword. For illustration purposes, a codeword obtained by encodingwith a block code is shown in Figure 5-3. Such an encoding is said to be systematic. Systematicencoding means that the information symbols always appear in the first (leftmost) k positions ofa codeword.

Figure 5-3. A Systematic Block Encoding for Error Correction

5.5.2 Encoding

5.5.2.1 What Are Information Symbols in the NAND?

• Information symbols can, of course, be data written in sectors of a page:

– For example, the NAND Flash page size is 2048 bytes, the sector size is 512 bytes,and the information symbols are the data (length is 512 x 8 bits) stored in one sector.

• Redundancy symbol and PMECC module

– The PMECC module generates redundancy at encoding time, when a NAND writepage operation is performed.

– The PMECCx (x depends on BCH_ERR and SECTORSZ) is refreshed at each writeaccess of the sector (depends on the sector size and the number of sectors perpage) until the last byte of the main area is written.

– For example, the NAND Flash page size is 2048 bytes, the sector size is 512 bytes,correct 4-bit errors, and the PMECC generates 7-byte redundancy (PMECC_ECC0,PMECC_ECC1, …, and PMECC_ECC6).

• Codeword

– The PMECC encoder takes the information symbols from the NAND and redundantsymbols as input. Thus, the codeword is made of information symbols plusredundant symbols.

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– Take the above for example, the codeword in the first sector is the data in the firstsector plus PMECC_ECC0, PMECC_ECC1, …, and PMECC_ECC6.

5.5.2.2 Generator PolynomialBCH codes are cyclic codes that are constructed by specifying their zeros, that is, the roots oftheir generator polynomials. The generator polynomial g(x) of a t-error-correcting primitive BCHcodes of length is given by

where is the minimal polynomial and LCM represents the least common multiple.

5.5.3 Decoding

5.5.3.1 Syndrome PolynomialLet be the information codeword, as mentioned above,

, where is the minimal polynomial of .

• What is ?

– It is the PMECC remainder indicated in the datasheet.

– The syndrome polynomial s(x) is used to determine the error polynomial.

– If all syndromes are zero, then the data in the NAND sector is a codeword, anddecoding finishes. Otherwise, an error occurs.

• How to get ?

– Be implemented in hardware PMECC.

– The PMECC_REMx (x depends on BCH_ERR and SECTORSZ) is generated(depends on the sector size and the number of sectors per page) until the last byteof the main area is written.

– For example, the remainder in PMECC_REM0 is 0x1C31, the syndrome polynomials(x) = x12 + x11 + x10 + x5 +x 4+ 1.

– See related function genSyn() in pmecc.c.

– Remainder substitution.

– The substitute function evaluates the polynomial remainder, with different values ofthe field primitive elements.

– See related function substitute () in pmecc.c.

– Find the Error Location Polynomial Sigma(x).

– It is detailed in Section “Software Implementation” in the datasheet.

– See related function get_sigma() in pmecc.c.

5.5.3.2 Berlekamp Iterative ProcedureThe code in the software package gives a Berlekamp iterative procedure to find the value of theerror location polynomial. The Berlekamp procedure computes with the known 2t syndromesequence (substituted in function substitute()). It skips the even steps since the dis-crepancy in even steps is always zero. Thus, in this way only t iterations are needed instead of2t iterations. The goal of the Berlekamp is to find a (connection) polynomial of min-imal degree.

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Application Note

Application Note

First, make a table:

The Berlekamp Iterative algorithm is as follows:

1. Initialize the table as above. Set .

2. if , then . Let .

3. If , then find a preceding row (row ) with the most positive and .Then . If , terminate the algorithm.

4. .

5. , is the coefficient ofthe i-th term in .

6. Increment and repeat from step 2.

5.5.3.3 Find the Error PositionNow, it gets thanks to the Berlekamp Iterative procedure. The degree of this polynomial isvery important information, as it gives the number of errors. The error position is the root of

. This step can be very software-intensive. Indeed, there is no straightforward method ofroot finding, except by evaluating each element of the field in the error location polynomial. How-ever, a hardware accelerator can be used to find the roots of the polynomial. The PMERRLOCmodule provides this kind of hardware acceleration.

• Input to Error Location SIGMAx Register.

• The coefficient programmed in the PMERRLOC_SIGMAx (x=0 to 23) register is thecoefficient of degree x in the polynomial.

• The PMERRLOC search operation is started as soon as a write access is detected in thePMERRLOC_ELEN.ENINIT field.

– The ENINIT field of the ELEN register shall be initialized with the number of Galoisfield elements to test.

– The number is the addition of the bit number of sector and the size of ECC.

• PMERRLOC_ELSR.BUSY=1 during location computation.

• Once PMERRLOC_ELISR.DONE=1 (can be interrupt driven) thePMERRLOC_ELISR.ERR_CNT field indicates the number of errors.

• The error location can be read in the PMERRLOC_ELx (x=0 to 23) registers.

Table 5-4. Example Flow in Berlekamp Iterative Procedure

-1/2 1 1 0 -1

0 1 S1 0 0

1

2

…

t

1511127A–ATARM–23-Sep-11

6. SAM9G15/G25/G35/X25/X35 Software Driver

6.1 SMC TimingsPrior to any Command and Data Transfer, the SMC User Interface must be configured to meetthe device timing requirements.

• Write Enable Configuration

– Use NWE_SETUP, NWE_PULSE and NWE_CYCLE to define the write enablewaveform according to the datasheet of the device.

• Read Enable Configuration

– Use NRD_SETUP, NRD_PULSE and NRD_CYCLE to define the read enablewaveform according to the datasheet of the device.

Table 6-1. NAND Flash (MT29F2G08A) Timing vs. SMC Configuration

SMCRegister Timing Field Definition Timing Comments

SETUP

NWE_SETUPThe setup of address anddata before the NWE fallingedge

tCS tWPtALS tCLS

(1)

NCS_WR_SETUPThe setup time of addressbefore the NCS falling edge

0

NRD_SETUPThe setup of address beforethe NRD falling edge

tAR tCLR (2)

NCS_RD_SETUPThe setup time of addressbefore the NCS falling edge

0

PULSE

NWE_PULSEThe time between NWEfalling edge and NWE risingedge

tWP

NCS_WR_PULSEThe time between NCS fallingedge and NCS rising edge

tALH tCLH

NRD_PULSEThe time between NRD fallingedge and NRD rising edge

tRP

NCS_RD_PULSEThe time between NCS fallingedge and NCS rising edge

tCS tCH tCS + tCH

HOLD

NWE_HOLDThe hold time of address anddata after the NWE risingedge

tALH tCLH Max(tALH,tCLH)

NCS_WR_HOLDThe hold time of address afterthe NCS rising edge

0

NRD_HOLDThe hold time of address afterthe NRD rising edge

= NRD_CYCLE –NRD_SETUP –NRD_PULSE

NCS_RD_HOLDThe hold time of address afterthe NCS rising edge

0

1611127A–ATARM–23-Sep-11

Application Note

Application Note

Notes: 1. Timing tCS, tALS and tCLS all equal NWR Setup + NWR Pulse, so that the NWE_SETUP issatisfied with these values.

2. As CLE and ALE are address lines (A21, A22), an additional setup timing is requiredto respect tAR (10 ns) and tCLR (10 ns) on STATUS or RANDOM DATA READCycle.

A data bus width of 8 bits can be selected for each chip select. This option is controlled by thefield DBW in SMC_MODE (Mode Register) for the corresponding chip select.

6.2 ONFIThis specification defines a standardized NAND Flash device interface which provides themeans to design a system supporting a range of NAND Flash devices without a direct designpre-association. The solution also provides the means for a system to seamlessly make use ofnew NAND devices that may not have existed at the time the system was designed.

The NAND Flash library provides a procedure to check if the NAND Flash is ONFI compliant,sending a Read Id command (0x90) with 0x20 as the address parameter. If the NAND Flash isONFI compliant, it will retrieve the following parameters with the help of the PMECCconfiguration:

• Number of bytes per page (byte 80)

• Number of bytes in the spare zone (byte 84)

CYCLE

NWE_CYCLEThe total duration of the writecycle

tWC Min tWC

NRD_CYCLEThe total duration of the readcycle

tRC Min tRC

TDF TDF_CYCLE The Data Float Time tRHZ

Table 6-2. SMC NCS3 Configuration Example (133MHz MCK)

SMC Configuration NWE_CYCLE

NWE_SETUP 1

5

NWE_PULSE 3

NWE_HOLD 1

NCS_WR_SETUP 0

NCS_WR_PULSE 5

NCS_WR_HOLD 0

NRD_CYCLE

NRD_SETUP 1

6

NRD_PULSE 4

NRD_HOLD 1

NCS_RD_SETUP 0

NCS_RD_PULSE 6

NCS_RD_HOLD 0

Table 6-1. NAND Flash (MT29F2G08A) Timing vs. SMC Configuration (Continued)

SMCRegister Timing Field Definition Timing Comments

1711127A–ATARM–23-Sep-11

• Number of ECC bit correction required (byte 112)

• ECC sector size: by default set to 512 bytes or 1024 bytes if the ECC bit capability above is0xFF.

Table 6-3 lists some routines related to ONFI in NandFlashOnfi.C.

6.3 NAND Flash Library

6.3.1 Layered ArchitectureThe NAND Flash is composed of low-level functions for NAND Flash devices and external APIfunctions that support the unified interface of functions and operations for supported NANDFlash Devices. The NAND Flash drivers can be divided into a set of layers, such as Raw layer,ECC layer and SkipBlock layer.

6.3.2 Raw LayerThe Raw layer drives hardware-specific Bus Read and Bus Write operations to communicatewith the NAND Flash device. It directly interacts with hardware's register to operate NAND Flashinterface. The Raw layer implements procedures to program basic NAND Flash operations. Ittakes care of issuing the correct sequences of write/read operations for each command. All func-tions in the layer are blocked (i.e., they wait for the completion of an operation).

Table 6-4 lists the available routines for Raw layer in NAND Flash driver.

Table 6-3. API List for ONFI

Routine Explanation

NandIsOnficompatible Read ONFI signature to detect if the device is ONFI compatible.

NandGetOnfiPageParam Retrieves some useful data for ONFI for PMECC.

Table 6-4. API list for the Raw layer

Routine Explanation

RawNandFlash_InitializeInitializes a RawNandFlash instance based on the given model andphysical interface.

RawNandFlash_Reset Resets a NAND Flash device.

RawNandFlash_ReadId Reads and returns the identifiers of a NAND Flash chip.

RawNandFlash_EraseBlockErases the specified block of the device, retrying several times if itfails.

RawNandFlash_ReadPageReads the data and/or the spare areas of a page of a NAND Flashinto the given buffers.

RawNandFlash_WritePageWrites the data and/or the spare area of a page on a NAND Flashchip.

RawNandFlash_CopyPageCopies the data in a page of the NAND Flash device to another pageon that same chip. Both pages must be even or odd.

RawNandFlash_CopyBlockCopies the data of one whole block of a NAND Flash device toanother block.

1811127A–ATARM–23-Sep-11

Application Note

Application Note

6.3.3 ECC LayerThe ECC layer is located between the Raw layer and the SkipBlock layer. It provides page writeand read interface with or without ECC computation. If the application needs to access theNAND Flash with the software ECC algorithm, it calculates ECC of data using the Hammingcode algorithm before a page write in the Raw layer, and detects and corrects error bit using theHamming code algorithm after a page read in the Raw layer. If the application needs to accessthe NAND Flash wi th the PMECC algor i thm, fo r page wr i te , i t i nvokesRawNandFlash_WritePage() directly in the Raw layer, when a NAND write page operation isperformed. The redundancy is appended to the page and written in the ECC area. For pageread, it first invokes the RawNandFlash_ReadPage() routine in the Raw layer. After the pagehas been fully retrieved from the NAND, it returns an error status to indicate which sector is cor-rupted. Then, in the ECC layer, it implements the BCH algorithm to correct error bit(s).

Table 6-5 lists the available routines for the ECC layer in the NAND Flash driver.

6.3.4 SkipBlock LayerThe goal of the SkipBlock layer is to skip over the bad blocks and to place the data in the nextgood block. The algorithm starts by reading the entire spare area of the entire memory. Theaddresses of the marked bad blocks are then collected in the programmer RAM. Next, the imageis sequentially programmed (page by page) into the target device. When the target address cor-responds to a bad block address, these pages are stored in the next good block, skipping thebad block. The SkipBlock method is a very generic and well-performing strategy.

Table 6-5. API List for the ECC Layer

Routine Explanation

EccNandFlash_InitializeInitializes an EccNandFlash instance based on the given model andthe physical interface.

EccNandFlash_ReadPageReads the data and/or spare of a page of a NAND Flash chip, andverifies that the data is valid using the ECC information contained inthe spare.

EccNandFlash_WritePageWrites the data and/or spare area of a NAND Flash page, aftercalculating an ECC for the data area and storing it in the spare.

Table 6-6. SkipBlock Layer Function List

Routine Explanation

SkipBlockNandFlash_InitializeInitializes a SkipBlockNandFlash instance. Scans the deviceto retrieve or create block status information.

SkipBlockNandFlash_ReadBlock Reads the data of a whole block.

SkipBlockNandFlash_WriteBlock Writes the data of a whole block.

SkipBlockNandFlash_EraseBlock Erases the specified block of the device.

SkipBlockNandFlash_WritePage Writes the data and/or spare area of a page.

SkipBlockNandFlash_ReadPage Reads the data and/or the spare area of a page.

SkipBlockNandFlash_CheckBlock Returns block status of the given block.

1911127A–ATARM–23-Sep-11

6.3.5 How to Use DMA in Write/Read Operation?DMA can be used to increase the application performance. The read/write operation from/to theNAND and, in particular, the DMA speeds up the data transfer between a device on the systembus and the NAND Flash memory, and decreases the system bus burden as well. When thewrite/read page operation is terminated, the user writes/reads the data to/from the NAND mainor spare area. This operation can be done with the DMA assistance.

6.3.6 DMAC & DMAD DriverThe user can get DMAC and DMAD drivers in “libchip” and “libboard” libraries. All routines areimplemented to comply with the functionality documented in the datasheet related to the DMA.Refer to the DMA application notes to get details of each function.

The DMAC driver contains basic functions which can directly access the DMA controller(DMAC).

The DMAD driver provides an interface to use and take full advantage of the DMA controller.

6.3.6.1 Initialize the DMA Driver

• Initialize the DMA driver instance with the polling mode:

DMAD_Initialize( &dmad, POLLING_MODE );

• Allocate the DMA channel and configure the DMA for a NAND data transfer:

NandFlashConfigureDmaChannels( &dmad );

Table 6-7 lists the available routines for DMA transfer in NandFlashDma

6.3.6.2 Transfer Data from External Memory to NAND Page Using DMA• Check if the DMA channel is available• Launch NandFlashDmaTransferRam2Nand()

– Configure the source address in the external memory to be transferred– Set the size to be transferred (Page size for the Main area or ECC area Size for the

spare area)– Configure the DMA in single transfer mode– Transfer data with DMA immediately

• Example code:if (NandFlashIsDmaActived())

{

NandFlashDmaTransferRam2Nand(buffer, size);

}

}

Table 6-7. API List for NAND Flash with DMA

Routine Explanation

NandFlashConfigureDmaChannels Allocates 2 DMA channels for NAND RX and TX.

NandFlashDmaTransferRam2NandConfigures the DMA TX mode in given source address and size,and starts to transfer immediately.

NandFlashDmaTransferNand2RamConfigures the DMA RX mode in given destination address andsize, and starts to transfer immediately.

NandFlashIsDmaActived Checks if DMA channels for NAND are available.

NandFlashFreeDma Sets DMA channels free in the NAND driver.

2011127A–ATARM–23-Sep-11

Application Note

Application Note

6.3.6.3 Transfer Data from NAND Page to External Memory Using DMA

• Check if the DMA channel is available

• Launch NandFlashDmaTransferNand2Ram()

– Configure the Destination address in the external memory to be received

– Set the size to be received (Page size for the Main area or ECC area Size for thespare area)

– Configure the DMA in single transfer mode

– Transfer data with DMA immediately

• Example code:

if (NandFlashIsDmaActived())

{

NandFlashDmaTransferNand2Ram(buffer, size);

}

}

6.4 PMECC LibraryThe PMECC library named “libpmecc” is implemented to comply with the datasheet documentedfunctionality and pmecc algorithm. It contains:

• Two lookup tables: pmecc_gf_512 and pmecc_gf_1024

• Syndrome polynomial computation

• The Berlekamp Iterative procedure to find the error location polynomial

• A routine to search for error location(s) by hardware acceleration

• Flipping error bit(s)

Table 6-8 lists the available routines in the PMECC library.

Example code:

• Initialize PMECC

– 2048-byte page size

– 64-byte spare size

– 512-byte sector size

– 4-bit error correction per sector

– ECC offset in spare area is 2

– The spare area is skipped in read or write mode

PMECC_Initialize(&pmeccDesc, 0, 4, 2048, 64, 2, 0);

…

Table 6-8. API List for PMECC

Routine Explanation

PMECC_Initialize Initialize the PMECC peripheral with given pmecc parameter.

PMECC_CorrectionAlgo Launch error detection functions and correct corrupted bits.

PMECC_Disable Disable pmecc peripheral.

2111127A–ATARM–23-Sep-11

• Read the NAND flash page at block 100, page 20

• RawNandFlash_ReadPage(Raw(ecc), 100, 20, data, 0)

• Check the PMECC interrupt status register (can be interrupt driven)

– pmeccStatus = PMECC->PMECC_ISR

– When set to one, bit i of the PMECCISR register indicates that sector i is corrupted.

• Launch error detection functions and correct corrupted bits

PMECC_CorrectionAlgo( pPmeccDescriptor, pmeccStatus, data);

6.5 The ROM Code Embeds the PMECC SoftwareThe ROM code embeds the software used in the process of ECC detection/correction.

6.5.1 Galois Field TablesThe Galois field tables are mapped in the ROM just after the ROM code:

• Galois field tables for 512-byte sectors correction at 0x0010_8000

• Galois field tables for 1024-byte sectors correction at 0x0011_0000.

6.5.2 PMECC_CorrectionAlgo() FunctionThe user does not need to embed it in another software. This function can be called by user soft-ware when the PMECC status returns errors after a read page command. Its address can beretrieved by reading the third vector of the ROM Code interrupt vector table, at address0x100008. The API of this function is:

unsigned int PMECC_CorrectionAlgo(AT91PS_PMECC pPMECC,

AT91PS_PMERRLOC pPMERRLOC,

PMECC_paramDesc_struct *PMECC_desc,

unsigned int PMECC_status,

unsigned int pageBuffer)

7. Benchmark of PMECCThis benchmark aims at measuring the read and write bandwidth that can be expected on theNAND Flash memory device with the Static Memory Controller (SMC) of the ATMELSAM9G15/G25/G35/X25/X35 microcontroller series. The read bandwidth has been measuredaccording to the number of data errors that have voluntarily been inserted into the NAND Flashmemory device in order to estimate the impact of the PMECC correction algorithm on the readperformance. Tests have been performed on the ATMEL SAM9G35 microcontroller of the“SAM9GX5 Evaluation Kit”.

7.1 Hardware Features

7.1.1 Frequency ClocksCPU clock = 400 MHz

System clock = 133 MHz

2211127A–ATARM–23-Sep-11

Application Note

Application Note

7.1.2 NAND Flash Memory DevicesThe NAND Flash memory devices implemented on boards are the “MT29F2G08ABD” for theSAM9GX5-EK board. The MT29F2G08AxD is a 2G-bit SLC NAND Flash memory device. Theminimum ECC required is 1-bit ECC per 528 bytes of data. It contains 2,048 blocks. Each blockis subdivided into 64 programmable pages. The page size is 2048 bytes. The spare size is64 bytes.

7.2 Test Result

7.2.1 Benchmark (CPU cycles/ function of BCH Algorithm, Memory cache disable)

Table 7-1. Benchmark (CPU cycles/ function of BCH Algorithm, Memory cache disable)

Number of Errors GetSyn Substitute Get Sigma Error Location Error Correction Number of Cycles

1 1344 38064 52176 8768 224 100576

2 1344 37520 58672 8816 304 106656

3 1360 36864 65312 8864 384 112784

4 1360 37728 72192 8912 464 120656

5 1344 37984 78880 8944 544 127696

6 1360 37600 85792 8976 624 134352

7 1360 37728 92032 9024 704 140848

8 1360 38048 98336 9072 800 147616

9 1344 37664 105376 9120 864 154368

10 1344 39328 111200 9152 960 161984

11 1344 37952 118736 9200 1040 168272

12 1344 38544 124928 9232 1136 175184

13 1344 38176 131424 9280 1216 181440

14 1344 38368 137792 9312 1280 188096

15 1360 36848 143552 9376 1360 192496

16 1360 37040 150384 9408 1440 199632

17 1360 37536 157088 9456 1536 206976

18 1344 39520 163456 9488 1616 215424

19 1360 38432 170176 9536 1696 221200

20 1360 38944 175680 9568 1775 227328

21 1360 37120 181920 9616 1872 231888

22 1344 37664 189056 9664 1936 239664

23 1360 38480 194784 9696 2032 246352

24 1344 37888 201200 9744 2096 252272

2311127A–ATARM–23-Sep-11

7.2.2 Read/Write Bandwidth (1, 2 errors/sector in all sectors)

7.2.3 Read/Write Bandwidth (1 to 8 errors/sector in all sectors)

8. Application Examples (main.c)This smc-nandflash example shows how to access the NAND flash connected to the SMC, andhow to manage block with software ECC and PMECC, meanwhile, the DMA Measure taking intoaccount.

Table 7-2. Read/Write Bandwidth (1, 2 errors/sector in all sectors)

Configuration BandWidth

NA

ND

Fla

shC

ach

eM

od

e

Bu

ffer

Lo

cati

on

PM

EC

CA

UT

OM

od

e

Def

ault

Mas

ter

Wri

te(K

B/s

)

Rea

d(K

B/s

)N

oE

rro

r

Rea

d(K

B/s

)1

Err

or/

Sec

tor

PM

EC

CA

lgo

inD

DR

2P

ME

CC

Tab

les

inD

DR

2

Rea

d(K

B/s

)1

Err

or/

Sec

tor

PM

EC

CA

lgo

inR

OM

PM

EC

CT

able

sin

RO

M

Rea

d(K

B/s

)2

Err

ors

/Sec

tor

PM

EC

CA

lgo

inR

OM

PM

EC

CT

able

sin

RO

M

OFF DDR2 DISABLE NO 7315 15029 - - -

OFF DDR2 DISABLE YES 7315 15029 - - -

OFF DDR2 DISABLE YES 7315 15029 7980 7980 7049

OFF RAM DISABLE NO 7448 15827 - - -

OFF RAM DISABLE YES 7448 15827 - - -

OFF RAM DISABLE YES 7448 15827 8113 8113 7182

ON DDR2 ENABLE YES 11039 17689 8645 8645 7851

ON RAM ENABLE YES 11039 18886 8911 8911 7847

Table 7-3. Read/Write Bandwidth (1 to 8 errors/sector in all sectors)

Configuration BandWidth

NA

ND

Fla

shC

ach

eM

od

e

Bu

ffer

Lo

cati

on

PM

EC

CA

UT

OM

od

e

Def

ault

Mas

ter

Wri

te(K

B/s

)

Rea

d(K

B/s

)N

oE

rro

r

Rea

d(K

B/s

)1

Err

or/

Sec

tor

Rea

d(K

B/s

)2

Err

ors

/Sec

tor

Rea

d(K

B/s

)3

Err

ors

/Sec

tor

Rea

d(K

B/s

)4

Err

ors

/Sec

tor

Rea

d(K

B/s

)5

Err

ors

/Sec

tor

Rea

d(K

B/s

)6

Err

ors

/Sec

tor

Rea

d(K

B/s

)7

Err

ors

/Sec

tor

Rea

d(K

B/s

)8

Err

ors

/Sec

tor

off Ddr2 On Yes 6384 15092 7049 6118 5719 5187 4921 4655 4389 4256

off Ram On Yes 6384 15561 7049 6251 5719 5320 5054 4655 4389 4256

on Ddr2 On Yes 8911 18088 7581 6517 6118 5586 5320 4921 4655 4522

on Ram On Yes 8911 18088 7714 6650 6118 5719 5320 4921 4655 4522

2411127A–ATARM–23-Sep-11

Application Note

Application Note

8.1 Initialize the NAND FlashThe example code starts by configuring the SMC for NAND flash accesses, then by configuringall necessary pins on the SMC NCS3 space. Also, it retrieves some parameters from the NANDFlash by issuing a NandGetOnfiPageParam which can help to configure the PMECC with suit-able values. After that, i t reads the Manufacturer and Device codes by issuing aSkipBlockNandFlash_Initialize and checks if they are correct. If these functions work, the otherfunctions are also likely to work.

Example code:

/* Configure SMC for Nandflash accesses */

BOARD_ConfigureNandFlash(nfBusWidth);

/* Configure Nandflash Pins */

PIO_Configure(pPinsNf, PIO_LISTSIZE(pPinsNf));

SkipBlockNandFlash_Initialize(...) {

printf("-E- Device Unknown\n\r");

return 0;

}

8.2 Raw Access• Erase the block before write and read

• Write a page of data to the given block

• Read the page

• Also, it measures the write and read performance in sample code

Example code for accessing the NAND in the Raw layer:

SkipBlockNandFlash_EraseBlock(&skipBlockNf, block, SCRUB_ERASE);

for ( page = 0; page < numPagesPerBlock; page++)

{

RawNandFlash_WritePage(((struct RawNandFlash *) &skipBlockNf) ,block,page, pageBuffer, 0);

}

for ( page = 0; page < numPagesPerBlock; page++)

{

RawNandFlash_ReadPage(((struct RawNandFlash *) &skipBlockNf) ,block,page, pageBuffer, 0);

}

29B

8.3 Access the NAND Flash in the SkipBlock Layer• Initialize the PMECC parameter

• Erase the block before write and read

• Write a page of data to the given block with PMECC enable

• Read the page with PMECC enable

• Also, it measures the write and read performance in sample code

PMECC_Initialize(&pmeccDesc, 0, 2, pageSize, spareSize, 0, 0 );

2511127A–ATARM–23-Sep-11

SkipBlockNandFlash_EraseBlock(&skipBlockNf, block, SCRUB_ERASE);

for ( page = 0; page < numPagesPerBlock; page++)

{

SkipBlockNandFlash_WritePage(&skipBlockNf, block, page, pageBuffer, 0);

}

for ( page = 0; page < numPagesPerBlock; page++)

{

SkipBlockNandFlash_ReadPage(&skipBlockNf, block, page, pageBuffer, 0);

}

8.4 DMA Enable• Initialize the DMA driver instance

• Configure DMA channels for data transfer

• The write/read performance can be tested with DMA enable or disable

/* Initialize DMA driver instance with polling mode */

DMAD_Initialize( &dmad, POLLING_MODE );

if ( NandFlashConfigureDmaChannels( &dmad ))

{

printf ("-E- Initialize DMA failed !");

return;

}

printf ("-I- Initialize DMA done.\n\r");

2611127A–ATARM–23-Sep-11

Application Note

Application Note

9. Revision History

Document Rev. Comments Change Request Ref.

11127A First issue.

2711127A–ATARM–23-Sep-11

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11127A–ATARM–23-Sep-11