50-200 GHz InP HBT Integrated Circuits for Optical Fiber and mm-Wave Communications

Mark Rodwell

University of California, Santa Barbara

rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax

2002 ECOC Conference, September, Copenhagen

Applications: optical fiber transceivers at 40 Gb/s and higher

Key advantages for:TIA, LIA, Modulator driver

Losing competition with SiGe:MUX/CMU, DMUX/CDRexcessive powerproblems with integration scale

80 & 160 Gb may come in timeworld may not need capacity for some timeWDM might be better use of fiber bandwidth

This presentation: how InP HBT ICs will be able to do 160 Gb/s"If you build it, they will come." (today, this argument is not convincing).

aa

routebuffer

SwitchWideband Optical Transceiver

clockPLL

AD

DMUX

O/E, E/O interfaces

MUX

AD

AD

IQ

I

Q

DMUX

DMUX

mm-wave interfaces

I

Q

DA

DA

IQ

electronicor optical

Wideband mm-Wave Transceiver

Electronics for GigaHertz Communication

poweramplifier

MUX

addressdetect

PLL

Switches:network protocols,digital control, fast ICs,optical, electronic switches

mmWave Transmission UCSB

Atmospheric attenuation is LOW(~4 dB/km) at bands of interest 60-80 GHz, 120-160 GHz, 220-300 GHz

(Weather permitting)

Geometric path losses are LOWdue to short wavelengths.

4 mW transmitter power sufficient for 10 Gb/stransmission over 500 meters range given 20 cm diameter antennas

Bit rate 1.00E+10 1/seccarrier frequency 1.50E+11 HzF 10 dB receiver noise figureDistance 5.00E+02 m transmission rangeatmospheric loss 4.00E-03 dB/m dB loss per unit distanceDant, trans 0.2 m transmit antenna diameterDant, rcvr 0.2 m receive antenna diameterbits/symbol 1kT -173.83 dBm (1Hz)Prec -48.27 dBm received power at 10 {̂-9} B.E.R∆f 1.00E+10 Hz RF channel bandwidth requiredtransmission -51.64 geometric path loss, dBatmospheric loss 2 dB total atmospheric loss, dB

Ptransmitter 3.4 mW required transmitter power

How Do We Improve the Bandwidth of Bipolar Transistors ?

collex

Ebc

Ejecollectorbase RR

qI

kTC

qI

kTC

f

2

1

Thinner base, thinner collector higher f , but higher RbbCcb , RexCcb …

what parameters are really important in HBTs ?how do we improve HBT performance ?

HBT scaling: layer thicknesses

WE

WBC

WEB

x

L E

base

emitter

base

collector

WCreduce Tb by 2:1

b improved 2:1

reduce Tc by 2:1

c improved 2:1

note that Ccb has been doubled ..we had wanted it 2:1 smaller

nbb DT 2/2

satcb vT 2/

2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,

's

EC WW ~ Assume

Rodwell

HBT scaling: lithographic dimensions

WE

WBC

WEB

x

L E

base

emitter

base

collector

WC

Ccb/Area has been doubled ..we had wanted it 2:1 smaller…must make area=LeWe 4:1 smallermust makeWe & Wc 4:1 smaller

Everticalcsheet

contact

contactspreadgapbb

L

R

RRRR

2,

Base Resistance Rbb must remain constant Le must remain ~ constant

reduce collector width 4:1reduce emitter width 4:1keep emitter length constant

2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,

's

EC WW ~ Assume

Rodwell

HBT scaling: emitter resistivity, current density

WE

WBC

WEB

x

L E

base

emitter

base

collector

WC

Emitter Resistance Rex must remain constantbut emitter area=LeWe is 4:1 smallerresistance per unit area must be 4:1 smaller

increase current density 4:1reduce emitter resistivity 4:1

2:1 improved device speed: keep G's, R's, I's, V's constant, reduce 2:1 all C's,

's

Collector current must remain constantbut emitter area=LeWe is 4:1 smallerand collector area=LcWc is 4:1 smallercurrent density must be 4:1 larger

EC WW ~ Assume

Rodwell

Scaling Laws for fast HBTs

22 as scale alsomust )cm-( y resistivitcontact base the

, allnot but ,structures device someFor v

circuitarbitrary an in bandwidth in increase 1: a

obtain order toin parameters HBTin change alproportion Required

Rodwell, IEEE Trans. Electron Devices, Nov. 2001

Optical Transmitters / Receivers are Mixed-Signal ICs

TIA: small-signal

aa

routebuffer

SwitchWideband Optical Transceiver

clockPLL

AD

DMUX

O/E, E/O interfaces

MUX

AD

AD

IQ

I

Q

DMUX

DMUX

mm-wave interfaces

I

Q

DA

DA

IQ

electronicor optical

Wideband mm-Wave Transceiver

Electronics for GigaHertz Communication

poweramplifier

MUX

addressdetect

PLL

Switches:network protocols,digital control, fast ICs,optical, electronic switches

Rf

Rc

Q1

Q2

I1

I2

Rf

Rc

Q1

Q2

I1

I2

  LIA: often limiting MUX/CMU & DMUX/CDR:mostly digital

Small-signal cutoff frequencies (f, fmax) are ~ predictive of analog speedLimiting and digital speed much more strongly determined by (I/C) ratios

InP HBT has been well-optimized for f & fmax, less well for digital speed

How do we improve logic speed ?

clock clock clock clock

inin

out

out

cexLOGIC

LOGIC

Ccb

becb

becbC

LOGIC

IRq

kTV

V

IR

CCR

CCI

V

6

leastat bemust swing logic The

resistance base the through

charge stored

collector base Supplying

resistance base the through

charging ecapacitancDepletion

swing logic the through

charging ecapacitancDepletion

:by DeterminedDelay Gate

bb

depletion,bb

depletion,

max

logic

emitter

collector

min,

depl,

& not speed,clock for design toneed

:SiGen faster thabarely logic InP

high at lowfor low very bemust

22

objective.design HBTkey a is /High

total.of 80%-60% is

. with correlated not wellDelay

ff

JVR

v

T

A

A

V

V

I

VC

CI

CCIV

f

eex

effective

C

CE

LOGIC

C

LOGICcb

cbC

becbCLOGIC

Technology Roadmaps for 40 / 80 / 160 Gb/s

Challenges with Scaling:

Collector-base scaling Mesa HBT: collector under base contacts. Base contacts have nonzero resistivity → sets minimum contact sizeSolution: reduce base contact resistivity Solution: decouple base & collector dimensions

e.g. buried SiO2 in junction (SiGe), undercut-mesa (InP)

Emitter Ohmic Resistivity: must improve in proportion to square of speed improvements

Current Density: increases rapidlydevice heating, current-induced dopant migration, dark-line defect formationSiGe at 5*105 A/cm2, InP at 1*105

Loss of breakdown voltageInP superior to SiGe at equal speed

YieldInP HBT processes must reach yield sufficient for DMUX/CMUprogressively more difficult at submicron dimensions

Low Ccb InP HBT structures

emitterbase contact

collectorcontact

SI substrate

InGaAs subcollector

InP collector

InGaAscollector

InP subcollector

InGaAs base

undercutcollector junction

undercut-collector

transferred-substrate Allows deep submicron collector scaling

high mm-wave gains low yield at deep submicron scalingmm-wave device, not mixed-signal

Pursued by several research groups

Also has uncertain yield at submicron geometries

The conservative III-V device structure

Yet, I assert that even this device is notviable of mass manufacturing if > 3000 transistors per IC are sought

Need improved device structures for high yield at 0.1 m scaling

Narrow-mesa with ~1E20 carbon-doped base

Transferred-Substrate HBTs UCSBONR

140-220 GHz network analysis

HP8510C network analyzer & Oleson Microwave Lab frequency Extenders

GGB waveguide-coupled probes

75-100 GHz network analysis

GGB waveguide-coupled probes HP W-band test set

1-50 GHz network analysis

GGB coax-connectorized probes HP 0.045-50 GHz test set

220 GHz On-Wafer Network AnalysisMiguel Urteaga

Accurate measurements are not easyHBT Ccb is very small (~5 fF)→ S12 easily masked by probe-probe couplingincrease probe separation: reference plane extensionsOn-wafer LRL calibration standardsultra-thin microstrip for reduced mode coupling

Emitter: 0.3 x 18 m2, Collector: 0.7 x 18.6 m2

Ic = 5 mA, Vce = 1.1 V

Submicron InAlAs/InGaAs HBTs: Unbounded (?!?) Unilateral power gain 45-170 GHz

1E10 1E11 1E12

Freq.

-5

0

5

10

15

20

25

30

35

40

RF G

ains

U

MAG/MSG

h21

unbounded U

UCSBONR

emitter

collector

Miguel Urteaga

Urteaga, Int. Journal High Speed Electronics and Systems, to be published

gain resonances likely due to IMPATT effects

Rodwell, Int. Symp. Compound Semiconductors, Tokyo, Oct. 2001

175 GHz Single-Stage AmplifierUCSB

Miguel Urteaga

-20

-15

-10

-5

0

5

10

140 150 160 170 180 190 200 210 220

S21S11S22

dB

Freq. (GHz)

0.2pF

50 301.2ps

50

300.2ps

801.2ps

0.6ps

801.2ps

50

IN

OUT

6.3 dB gain at 175 GHz

Deep Submicron Bipolar Transistors for 140-220 GHz Amplification Miguel Urteaga

0

10

20

30

40

10 100 1000

Tra

nsi

sto

r G

ain

s, d

B

Frequency, GHz

U

U

MSG/MAG

H21

unbounded U

-4

-2

0

2

4

6

8

140 150 160 170 180 190 200 210 220

S2

1,

dB

Frequency, GHz

1-transistor amplifier: 6.3dB @ 175 GHz

-30

-20

-10

0

10

140 150 160 170 180 190 200 210 220

gain

, dB

Frequency (GHz)

3-transistor amplifier: 8 dB @ 195 GHz

raw 0.3 m transistor: 6-11 dB power gain @ 200 GHz

UCSB

0

10

20

30

40

1 10 100 1000

Gai

ns (

dB)

Frequency (GHz)

U

h21 462

395

343

139

0

1

2

0 2 4 6 8

I C (

mA

)

VCE

(V)

Ib step = 20 A

UCSBSangmin Lee

fmax = 462 GHz, ft = 139 GHz

InGaAs/InP DHBT, 3000 Å InP collector

0.5 m x 8 m emitter (mask)0.4 m x 7.5 m emitter (junction)1.0 m x 8.75 m collector

BVCEO = 8 V at JE =5*104 A/cm2

High Current, High Breakdown Voltage InP DHBT

8-finger device8 x ( 1 m x 16 m emitter )8 x ( 2 m x 20 m collector )

W band 128 m2 power amplifier UCSB

common base PA

-5

0

5

10

15

20

0

2

4

6

8

10

-15 -10 -5 0 5 10 15

Po

ut,

dB

m GT , d

B

Pin, dBm

GT Pout

-30

-25

-20

-15

-10

-5

0

5

10

80 90 100 110

S11

, S

21,

S22

frequency, GHz

S21

S22

S11

0.5mm x 0.4 mm, AE=128 m2

ARO MURI

f0=85 GHz, BW3dB=28 GHz,GT=8.5 dB, P1dB=14.5 dBm, Psat=16dBm

Bias: Ic=78 mA, Vce=3.6 V

High Speed Amplifiers

18 dB, DC--50+ GHz

UCSBDino Mensa

PK Sundararajan

8.2 dB, DC-80 GHz

-20

-15

-10

-5

0

5

10

15

20

0 10 20 30 40 50

>397 GHz gain x bandwidth from 2 HBTs

S22

S11

S21

Ultra Wideband Mesa InP/InGaAs/InP DHBTs Mattias Dahlstrom (UCSB)

Amy Liu (IQE)

2000 Å InP collector300 Å InGaAs base8E19 to 5E19 graded C base dopingInAlAs/InGaAs base-collector grade.

500 Ohm/square base sheet resistance< 2*10-7 Ohm-cm2 base contact resistance

7.5 V Breakdown282 GHz f>450 GHz fmax, operation to 500 kA/cm2 at 1.7 volts

0

5

10

15

20

25

30

1010 1011 1012

Gai

n (

dB

) H

21,

U

frequency (GHz)

ft=282 GHz

fmax

=480 GHz

UCSB / IQE

87 GHz HBT master-slave latch

InAlAs /InGaAs/InP MESA DHBT

400 Å base, 2000 Å collector,

9 V BVCEO

200 GHz ft, 180 GHz fmax

2.5 x 105 A/cm2 operation

PK Sundararajan, Zach Griffith

-0.2

-0.18

-0.16

-0.14

-0.12

-0.1

-0.08

-0.06

22 22.02 22.04 22.06 22.08 22.1 22.12 22.14

87 GHz input, 43.5 GHz output

Vo

ut (

Vol

ts)

time (nsec)

UCSB

200 GHz logic program

8 GHz ADC

Technology0.7 um InAlAs /InGaAs/InP MESA DHBT 400 Å base, 2000 Å collector, 9 V BVCEO, 200 GHz ft, 180 GHz fmax2.5 x 105 A/cm2 operation

Designsimple 2nd-order gm-C topologycomparator is 87 GHz MSS latchintegration by capacitive loads 3-stage comparator, RTZ gated DAC

Results133 dB (1 Hz) SNR at 74 MHzequivalent to ~8.8 bits at 200 MS/s

UCSBPK Sundararajan, Zach Griffith

200 GHz logic program

975 kHz FFT bin size8 GHz clock rate65.5 MHz signal64:1 oversampling ratio

InP vs. Si/SiGe HBTs: recent experience at 40 Gb/s

40 Gb/s IC development during internet bubble 7 of my ex-Ph.D. students involved, at 4 different companies personally actively involved as consultant

InP HBT technology 1 m design-rule processes easily developed, good reliability, yield ok for 2000 HBTs (not more), 170 GHz f, fmax , 7 volt Vbr, 3 mA (min) device, 60 GHz clock

Resulting ICs TIA, LIA, 6 V differential modulator driver: quite successful MUX/CMU, DMUX/CDR: limited to 4:1 (yield, power) SiGe necessary for 16:1 standards-compliant MUX & DMUX market is presently very small

InP requires lower NRE than SiGe

InP critically needs: higher integration scales, scaling for speed & power

High current density 10 mA/m2

T-shaped polysilicon emitter 0.25 m junction wide contact low resistance, high yield

Thin intrinsic base: low b

Thick extrinsic base: low Rbb

Low Ccb collector junction collector pedestal CVD/CMP SiO2 planarization regrown poly extrinsic base

High-yield, planar processing high levels of integration LSI and VLSI capabilities

SiGe clock rates up to 65 GHzMuch more complex ICs than feasible in InP HBTInP HBT must reach higher integration scales or will cease to compete

Very strong features of SiGe-bipolar transistors

InP vs. Si/SiGe HBTs: materials vs. scaling advantages

Advantages of InP~20:1 lower base sheet resistance, ~5:1 higher base electron diffusivity~3:1 higher collector electron velocity, ~4:1 higher breakdown-at same f.

Disadvantage of InP: archaic mesa fabrication processPresently only scaled to ~ 1 um (production)large emitters, poor emitter contact:low current density: 2 mA/um2

high collector capacitance nonplanar device - low yieldlow integration scales

InP HBT limits to yield: non-planar processEmitter contact

Etch to base

Liftoff base metal

Failure modes

Yield degrades as emitters arescaled to submicron dimensions

base contact

emittercontact

base contact

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

emitter

S.I. substrate

base

sub collector

Emitter planarization, interconnects

base contact

liftoff failure:emitter-baseshort-circuit

S.I. substrate

base

sub collector

base contact

excessiveemitter undercut

S.I. substrate

base

sub collector

S.I. substrate

base

sub collector

planarization failure: interconnect breaks

MBE growth of Polycrystalline n+ InAs

Polycrystalline InAs grown on SiN:

• Doping = 1.3 1019 cm-3, Mobility = 620 cm2/V•s

• Results in doping-mobility product of 81021 (V •s •cm)-1

InGaAs lattice matched to InP:

• Doping = 1.0 1019 cm-3, Mobility = 2200 cm2/V•s

• Results in doping-mobility product of 221021 (V •s •cm)-1

Polycrystalline InAs has potential as an extrinsic emitter contact.

Dennis Scott

6 1018

8 1018

1 1019

1.2 1019

1.4 1019

1.6 1019

1.8 1019

2 1019

2.2 1019

945 950 955 960 965 970 975 980 985

Poly InAs:Si Doping vs. Temp

Dop

ing

Temp

SiGe HBT process: extensive use of non-selective-area poly-Si regrowth

Can a similar technology be developed for InP ?

Process Flow:Single-poly-regrowthInP HBT

collectorcontact

top view

subcollectorisolationimplantmask

emitterjunction

extrinsicemitterandcontact

basecontact

N- collector

N+ subcollector

S.I. substrate

1) Epitaxial Growth,Fe implant isolation

2) Deposit Pd/W base Ohmics.Encapsulate with Si3N4Etch base-collector junction

base

N- collector

N+ subcollector

S.I. substrate

base

basecontactSi

3N

4

3) Passivate with Si3N4Etch emitter window through baseForm emitter SiN sidewalls

N- collector

N+ subcollector

S.I. substrate

basecontact

Si3

N4

4) Regrow polycrystalline emitter.Deposit emitter metal.Etch through emitter

N- collector

N+ subcollector

S.I. substrate

base contact

Si3

N4

regrownInAlAs/InAsemitter*

*monocrystalline wheregrown on semiconductor,polycrystalline wheregrown on silicon nitride

emitter contact

5) Recess etch and depositcollector contacts

N- collector

N+ subcollector

S.I. substrate

base contact

Si3N

4

regrownInAlAs/InAs emitter*

emitter contact

collector contact

Regrown-Poly-InAs-Emitter HBT

0.0 100

2.0 100

4.0 100

6.0 100

8.0 100

1.0 101

0 1 2 3 4

AE = 0.8 x 15 um 2 I

b = 100uA/step

I c (m

A)

Vce

(V)

Dennis Scott

Submicron Scaling of InP HBTs

InP HBTs are a mixed-signal, not a MIMIC technology for MIMICs, sub-0.1-m InP HEMTs are hard to beat mixed-signal is fiber ICs, ADCs, DACs, digital frequency synthesis these are 1000 -- 40,000 transistor ICs

InP HBTs are struggling to compete with SiGe HBT application demands transistor counts near/beyond yield limits large emitter junctions→ high current → power near acceptable limits no decisive speed advantage in relevant circuits: digital logic materials advantages being squandered by inadequate scaling

InP HBTs can be scaled to operate at 160 Gb/s key is scaling emitter to 0.2 m, collector to 0.4 m contact resistivities challenging but feasible; yield is key concern

Critically needed for InP HBTs highly scaled process: 0.2 m emitters, 0.4 m collectors highly planar and high-yield fabrication processes small emitter junctions (0.2 m x 0.5 m) for acceptable power

In Case of Questions

What HBT parameters determine logic speed ?

exCicex

bbcbc

cbdiffcbje

RIqkTVR

RIV

CCC

/6 as effect,indirect strong very has

from 17% ,)( from 12% ,/ from 68%

:imes transit tand sresistanceby Delays Sorting

) (e.g. charging 18%only , charging 38% , charging 44%

:escapacitancby Delays Sorting

log

logic

Caveats: assumes a specific UCSB InP HBT (0.7 um emitter, 1.2 um collector 2kÅ thick, 400 Å base, 1.5E5 A/cm^2)

ignores interconnect capacitance and delay, which is very significant

Cje Ccbx Ccbi b+c) ( I/V) totalV/ I 33.5% 6.7% 27.8% 68.4%V/ I 12.3% 12.3%(kT/q) I 1.4% 0.1% 0.4% 0.5% 2.5%Rex -1.3% 0.1% 0.3% 0.9% 0.1%Rbb 10.2% 2.8% 3.7% 16.7%total 43.8% 6.8% 31.3% 17.5% 100.0%

38%

Yoram Betser, Raja Pullela

0

5

10

15

20

25

30

35

1 10 100Frequency, GHz

MSG

h21

Mason'sGain, U

• Submicron HBTs have very low Ccb (< 5 fF)

• HBT S12 is very small

• Standard 12-term VNA calibrations do not correct S12 background error due to probe-to-probe coupling

Solution

Embed transistors in sufficient length of transmission line to reduce coupling

Place calibration reference planes at transistor terminals

Line-Reflect-Line Calibration

Standards easily realized on-wafer

Does not require accurate characterization of reflect standards

Characteristics of Line Standards are well controlled in transferred-substrate microstrip wiring environment

Accurate Transistor Measurements Are Not Easy

Transistor in Embedded in LRL Test Structure

230 m 230 m

Corrupted 75-110 GHz measurements due toexcessive probe-to-probe coupling

140 150 160 170 180 190 200 210 220

freq, GHz

-0.15

-0.10

-0.05

0.00

0.05

0.10

0.15

0.20

0.25

0.30

freq (75.00GHz to 110.0GHz)

Can we trust the calibration ?

freq (140.0GHz to 220.0GHz)

S11 of throughAbout –40 dB

140-220 GHz calibration looks OK75-110 GHz calibration looks Great

S11 of openAbout 0.1 dB / 3o error

dBS21 of through line is off by less than 0.05 dB

S11 of openS11 of short S11 of through

75 80 85 90 95 100 105 110

freq, GHz

-70

-65

-60

-55

-50

-45

-40

Probe-Probe couplingis better than –45 dB

Miguel Urteaga

Negative Unilateral Power Gain ???

YES, if denominator is negative

This may occur for device with a negative output conductance (G22) or some positive feedback (G12)

12212211

2

1221

GGGG4

YY

U

1221L2211

2

1221

GGGGG4

YY

U

2-portNetwork G L

Select GL such that denominator is zero:

Can U be Negative?

What Does Negative U Mean?

Device with negative U will have infinite Unilateral Power Gain with the addition of a proper source or load impedance

AFTER Unilateralization• Network would have negative output resistance

• Can support one-port oscillation

• Can provide infinite two-port power gainU

Simple Hybrid- HBT model will NOT show negative U

Scaling Laws, Collector Current Density, Ccb charging time

base

emitter

collector

subcollector

base

emitter

collector

subcollector

Collector Field Collapse (Kirk Effect)

Collector Depletion Layer Collapse

)2/)(/( 2 cdsatcb TqNvJV

)2/)(( 2min, cTqNV dcb

2min,max /)2(2 ccbcbsat TVVvJ

Collector capacitance charging time is reduced by thinning the collector while increasing current

sat

C

CECE

LOGICCLOGICcCLOGICcb v

T

A

A

VV

VIVTAIVC

2/

emitter

collector

min,collector

cecbbe VVV )( hence , that Note

Rodwell

Why isn't base+collector transit time so important ?

reductionsuch no see escapacitancDepletion

1:10~ is which ,/

of ratioby reduced ecapacitancdiffusion signal-Large

)()(Q

:Operation Signal-LargeUnder

/

)()()(Q

:Operation Signal-SmallUnder

base

base

qkT

V

VV

II

VqkT

IV

dV

dII

LOGIC

LOGICLOGIC

dccbCcb

beCcb

bebe

CcbCcb

HBT distributed amplifier UCSBPK Sundararajan11 dB, DC-87 GHz

AFOSR

TWA with internal ft-doubler cells