a temperature compensated triple-path pll for dune
TRANSCRIPT
Ping Gui, Professor
Department of Electrical Engineering
Lyle School of Engineering
Southern Methodist University
Front-End Electronics 2018
May 20-25, 2018, Jouvence, QC, Canada
A Temperature Compensated Triple-path
PLL for DUNE Experiments at 77 K
Introduction and Background
Proposed Temperature Compensated PLL Topology
ASIC Design and Implementation
Measurement Results
Conclusion
Outline
Deep Underground Neutrino Experiment (DUNE) requires the data
links be capable of continuously operating at cryogenic temperature
of 77 K for 20-30 years
Phase locked loops (PLLs) are critical components for data links
Design requirements of PLLs
Functioning and keeping the performance over a large
temperature range (at both 300K and 77 K)
Life time of 20-30 years
Introduction and Background
Issues with Conventional Single-Path PLL (SPPLL) Architecture
Over Large Temperature Range
4
PFD VCO
Divider
RefClk up
dn
LPF
ClkPLL
CP
R1
C1
C2
• On-chip L and C(varactors) are highly sensitive to the temperature variation,
causing VCO frequency to drift
• PLL’s loop characteristics sensitive to large temp. variation
• These two factors would cause PLL unstable or out of lock
LC VCO
VCO Design Consideration –
Low KVCO (Frequency vs. Control Voltage) desirable
5
• Multi-band technique to lower Kvco
• Each band has a smaller Kvco
• Multi bands to cover the frequency range
• Band selection using digital code
KVCO is an important factor determining PLL characteristics and its variation affects
PLL loop bandwidth, phase margin (stability) and phase noise performance,
Desirable to keep the variation of KVCO small over a wide temperature range
VCO Design Consideration (cont.) –
Small KVCO Variation Desirable
KVCO variation
To keep PLL functional and in-lock over large temperature range
Low VCO frequency drift
Using frequency calibration or compensation
Maintaining PLL loop characteristics over temp
Low KVCO , small KVCO variation
For low jitter and low phase noise
Low KVCO , small KVCO variation
Improving circuit lifetime at 77K
Low supply voltage (1.2 V or lower)
Using transistors of longer channel length (90 nm instead of 65nm)
Other desirable feature such as small silicon area, especially saving the area of the
passive loop filter
PLL Design Approaches
VCTL
FVCO
Temperature
IncreaseFop
Vctl Increase
Vdd/2 VCTL
FVCO
Temperature
Increase
Fop
Vctl Increase
Vdd/2
Kvco
Increase
VH
After Kvco
IncreaseStart Point
End Point
Start Point
End Point
Existing VCO Temperature Compensation (#1)
• Using large Kvco to cover wide temp. range– Kvco increased
– Kvco variation with temperature increased
8
• Solution #2: Temperature-dependent control (bias) voltage for main/auxiliary
varactors to offset/compensate the frequency drift
• Open-loop method
– Requiring extensive characterization of the VCO frequency drift
– Under- and over-compensation often occurs
– Drift cancellation only for a relatively narrow frequency range
Existing Approaches for VCO Compensation (#2)
Proposed VCO Temperature Compensation
• Dual-Control VCO
– Kvco_tmp having no impact on high-frequency loop transfer function
– Vctl fixed, hence, Kvco almost fixed
– Cvar2>Cvar1, large temperature compensation capability
10
VCTL_TMP
FVCO
Temperature
Increase
Fop
Vctl_tmp Increase
Vdd/2 VH
Vctl Fixed
Vctl_tmp Tunning
Vctl Tunning
Start Point
End Point
Vctl Vctl_tmp
Cfix CVAR1 CVAR2LpRp
A temp compensation (TC) path with large gain (GM) but low bandwidth (BW) to
compensate for low-frequency temperature variation
Overall KVCO_composit = KVCO (1+GM)
∆Vctrl is much reduced for the main varactor
The TC path with low BW does not affect high-frequency operation of the VCO
Proposed Closed-Loop Temperature Compensating VCO
(TC-VCO)
G
∆Vctrl
∆ f
(1+G▪M) Kvco
G▪∆ f
(1+G▪M) Kvco
Kvco
M▪Kvco
∆ f
Main Varactor
Aux. Kvco
Proposed PLL Architecture with Temp Compensated VCO
12
∆Φ VCTLIcpΦIN
ΦOUT
ΦFB
1
SCR+
KVCOTMP
S
1
N
Icp
2π
LPF
KVCO
S
VCTL_TMPAVref
In steady state, VCTL is fixed at Vref, but VCTRL_TMP tracks temperature changes.
Kvco_tmp larger than Kvco to cover large temp range.
The LPF in the TC path ensures VCTRLTMP does not affect high-frequency loop
characteristics
To Save Silicon Area of the PLL Passive Loop Filter -
Splitting LPF for a Larger Effective CZ
VCTLP
VCTLTMP
Vref
VCTLI
RZ
CI
Cp
G RC LPF
ICPP
ICPI
sC
IRIsV CP
CPCTRL )(
A larger effective zero cap CZ can be implemented by separating the proportional
(R) path and integral (c) path and having separate charge pump for each path
CZ is equivalently amplified by a factor W= (ICPP · KVCOP) / (ICPI·KVCOI)
Saving silicon area occupied by the passive elements
cpi
cpp
eq
IcpiIcpp
I
ICC
CR
1z
Proportional path: CHPP, Resistor RZ,
Integral path: CHPP, capacitor CI,
Temp compensation (TC) path:
G(amplifier) , LPFT
Proposed Triple-Path PLL (TPPLL) with Temperature
Compensation
CHPI
DIV
VCTLPCKREF
CKOUT
CKFB
VCTLTMP
VCTLI
PFD
LPFICPP
ICPI
CHPP
CI
Cp
LPFTG
VCO
VREF
Prop_Var
RZ
Tmp_Var
Int_VarIntegral Control node
Propotional Control node
Each path producing a control
voltage for the corresponding
varactor to tune VCO frequency
The TC path with a large KVCO and a low bandwidth achieves temperature compensation and
keeps small variation of KVCO simultaneously
compensating the frequency drift over temperature
confining the control voltage variation on the integral path
Not affecting PLL high-frequency operation
Proposed Triple-Path PLL with Temperature Compensation
CHPI
DIV
VCTLPCKREF
CKOUT
CKFB
VCTLTMP
VCTLI
PFD
LPFICPP
ICPI
CHPP
CI
Cp
LPFTG
VCO
VREF
Prop_Var
RZ
Tmp_Var
Int_VarIntegral Control node
Propotional Control node
Linear model to find the transfer function, bandwidth, phase margin
Triple-Path PLL (TPPLL) Linear Model
∆Φ VCTLPΦIN
ΦOUTΦFB
KVCOTMP
S
1
N
ICPP
2π
KVCOP
S
VCTLTMP
Vref
ICPI
2π
VCTLI
RZ
CI
KVCOI
S
Cp
G1+S/ωT
1
TPPLL Transfer Function
s
K
CsR
RIA VCOP
PZ
ZCPP
2
12
N
1=(s) PRP
s
K
sC
IA VCOI
I
CPI
21
2
N
1=(s) INT
s
K
ssC
GIA VCOTMP
TI
CPITMP
2
)/1(2
N
1=(s)
)1)(1(
)1)(1()1(
)()()((s)
1
2
10
PT
ZZ
I
VCOICPI
TMPINTPRP
IN
FBTOT
sss
ss
NC
GMKI
sAsAsAA
VCOPZCPPTOT KRIN
BW 2
11
VCOIVCOTMP KKM TZ GM )1(0
)/(11 PZP CR
)()(
11
VCOICPICOPVCPPIZ
ZKIKICR
The TC path adds a pole and zero at low frequencies (around 13 KHz and 60 KHz )
This pole and zero cancel out each other on the phase shift so that the PLL behaves as a
typical 2nd-order system at high frequency.
The stability of the TPPLL is essentially the same as that of a typical 2nd-order system with a
compensating zero created by the resistor RZ.
TPPLL Loop Frequency and Phase Response
Temperature Compensated VCO Implementation
VCTLP
VCTLTMP
VCTLI
Prop_Var
Tmp_Var
Int_Var
Prop_Var tunes the VCO frequency
directly and determines the PLL loop-
bandwidth, together with a digital
switched cap array for the process
variation calibration.
Int_Var introduces a zero to transfer
function to guarantee PLL loop stability
The large sized varactor Tmp_Var
compensates the temperature variation.
KVCO Variation Reduction
0 CTLPV
)1(
1
GMK
f
KMGK
f
KGK
fV
VCOI
VCOIVCOIVCOTMPVCOI
CTLI
)1( GM
G
K
fGVV
VCOI
CTLICTLTMP
The control voltage of the proportional
path is fixed
The control voltage variation of the
integral path is reduced by a factor of
G∙M
The above desensitize the loop transfer
function to the KVCO variation and
stabilize the overall loop bandwidth over
large temp range, resulting in PLL
stability and loop optimization.
The TC path is always activated in the PLL operation
During power-up, the initial phase (frequency) error
between the reference and the VCO would drive the charge
pumps to charge or discharge the loop filter.
The voltage error between the integral path and the
reference voltage, Vref, would activate the TC path to further
update the VCO output phase
After certain time, VCTLP and VCTLI may saturate reaching
the supply rails temporarily. However, the saturated voltage
on the integral path would keep driving the voltage on the
TC path to go up or down.
This back and forth procedure would continue until the TC
path settles down at its final value and the VCO output
phase locks to that of the reference phase.
In lock, VCTLP would be the same as that of the Vref. The
gain stage on the TC path makes VCTLI only vary by a very
small amount.
TPPLL Response to Temperature Change and
Power-Up Process
Charge pump
Other Circuit Implementation
Vcm
Vdd
UP
DN DN
UP UP UP
DN DN
Vbp
sel
sel
Vbn
sel
sel
Icp
D Q
Q
VDD
VSS
Reference
CLK
Feedback
CLK
VDD
D
Reset
Reset
UP
DN
UP
DN
Phase-Frequency Detector
Crystal Oscillator (Reference Clock) Selection
• SiTime 5001 shows good frequency stability over temp (±0.1ppm) and low jitter(<0.5
ps), and a SiTime 5001 40 MHz crystal oscillator is chosen as our reference clock.
23
Parameter SiTime 5001 ASTX-H12 TG2016SAN
Manufacturer Si Time Abracon Seiko Epson
Type Si MEMS Si MEMS NA
Oper. volt (V) 1.8 3.3 1.2
Output type LVCMOS HCMOS Sine
Freq. (MHz) 1 to 80 0.675 to 55 13 to 40
Oper. temp. (°C) -40 to +85 -30 to +75 -30 to +85
Duty cycle (%) 45 to 55 45 to 55 40 to 60
Freq. tol. temp (ppm) ±0.1 ±2.5 ±0.5
Aging (first year @ 25 °C) ±1.5 ±1 ±1
Aging (10 year @ 25 °C) ±3.5 NA NA
Output tR/tF (ns) 1(typ) / 2 (max) 5 (max) NA
www.sitime.com/products/datasheets/sit5001/SiT5001-datasheet.pdf
www.abracon.com/Oscillators/ASTX-H12.pd
www.epsondevice.com/docs/qd/en/DownloadServlet?id=ID000970
Chips Implementation and Test Setup
1 mm
1 m
m
LPF
DIV
CP
VCO
PFD CAP BANK
ICs implemented using 65nm TSMC CMOS process. Core circuit area of the PLL: 250um x 300 um
The vacuum pump evacuates the chamber and the helium compressor cools down the copper plate from
room temperature down to 77 K.
The PLL chip which is mounted on the back of the PCB is directly attached to the copper plate inside the
sealed vacuum chamber. This ensures the temperature of the PLL chip is the same as that of the copper
plate. The temperature on the copper plate is constantly sensed and monitored.
2mm
2m
m
2.5GHz PLL IC (2016)1.25Gbps Serializer IC with PLL (2017)
Measurement and Simulation Results of
TPPLL v.s. SPPLL
TPPLL SPPLL
Very small variation on control voltage (VCTLP, VCTLI )
Only VCTL,TMP varies to track temperature change
Measured 2.5GHz TPPLL Jitter Performance
TPPLL Jitter
Performance
1.2V (300K) 1.2V(77K) 1.1V (300K) 1.1V (77K)
Random Jitter 435 fS 430.8 fS 493 fF 463.9 fS
Determin. Jitter 2.59 pS 3.83 pS 5.10 pS 4.40 pS
Total Jitter 8.67 pS 9.74 pS 12 pS 10.89 oS
Measured TPPLL and SPPLL Performance
Parameters Measured Results
Operation Frequency
2.22 GHz ~ 3.60
GHz
TPPLL VCO Output Random Jitter at 300 K 0.89 ps
TPPLL VCO Output Random Jitter at 77 K 0.42 ps
SPPLL VCO Output Random Jitter at 300 K 0.83 ps
SPPLL VCO Output Random Jitter at 77 K 0.77 ps
TPPLL Proportional VCTRL Variation over (77 K to 300 K) 7 mV
SPPLL VCTRL Variation over (77 K to 300 K) 877 mV
Frequency Drift Reduction 99%
Core Area 0.08 mm2
Power 8.5 mW @1.2V
Supply 1.2-1.05 V
Process 65 nm CMOS
Jitter of TPPLL is much lower than that of SPPLL at 77K
Device thermal noise reduced at low temperature
PLL BW is almost fixed due to the proposed TC TPPLL architecture, thus the effect of the BW on
phase noise and jitter is minimized.
Comparison to the State-of-the-Art
[5] [9] [10] [16] This Work
Process (nm) 130 130 40 90 65
Temperature Variation
(℃)-30~125 -40~85 -25~85 6~62 -196~27
Frequency Drift
without the Proposed
Technique (MHz)
61.6 72 28 N/A 125
Frequency Drift with
the Proposed
Technique (MHz)
10.5 18 4.7 N/A 1.4
Frequency-Drift
Reduction83% 75% 83% 69% 99%
T. Liu, P. Gui, et al., "A Temperature Compensated Triple-Path PLL with KVCO Non-Linearity Desensitization Capable of Operating at 77 K," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), Vol. 64, Iss. 11, 2017.
1.28Gbps 10:1 Serializer Measurement Results @77K
29
Eye Diagram
Eye Mask Fit
BER: 1E-12
Width: 0.82UI
Temperature: 77K
Data Type: PRBS31
Data Rate: 1.28Gbps
TJ: 140.62ps
RJ: 3.831ps
DJ: 87.262ps
1.28Gbps 10:1 Serializer Measurement Results @300K
30
Eye Diagram
Eye Mask Fit BER: 1E-12
Width: 0.84UI
Temperature: 300K
Data Type: PRBS31
Data Rate: 1.28Gbps
TJ: 115.68ps
RJ: 3.273ps
DJ: 71.29ps
Conclusion
• We present a triple-path PLL which can compensate the VCO frequency drift
over a large temperature variation and at the same time maintaining fixed
bandwidth and desensitized KVCO non-linearity for good jitter performance of
the PLL.
• Measurement results show the TPPLL is able to continuously operating and
reduce the frequency drift by 99% when temperature changes from 300 K down
to 77 K, exhibiting low jitter at low temperature.
• The TPPLL can have different gain settings for the separate proportional and
integral paths, which work as a capacitor multiplier, leading to saving on the
silicon area of the loop filter.
31
Acknowledgement
My students: Xiaoran Wang, Tianwei Liu, Tao Zhang, Guoying Wu,
Rui Wang
Fermilab collaborators: Davide Braga, Grzegorz Deptuch, Albert
Dyer, Jim Hoff, Scott Holm, Sandeep Miryala, Terri Shaw, David
Christian
DoE for support of this work
