Ch.5 Logic Design

Standard Cell Design

TAIST ICTES ProgramVLSI Design Methodology

Hiroaki Kunieda

Tokyo Institute of Technology1

Logic Design

Functional Verification

Logic Synthesis

Scan Path Design

RTL SimulationRTL

Synthesis Netlist

Scan Netlist Timing Analysis

Functional Verification

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5.1 Logic Synthesis

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Logic Synthesis Problem Map from logic equations to gate-

level combinational logic Goals

maximize speed minimize power minimize chip/board area

Constraints target technology CAD tool CPU time

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Two-Level vs. Multi-Level

PLAcontrol logicconstrained layouthighly automatictechnology independentmulti-valued logicinput, output, state encodingVery predictable

Multi-level Logicall logicgeneral (e.g. standard cell, regular

blocks,..)automaticpartially technology independentsome ideaspart of multi-level logicVery hard to predict

E.g. Standard Cell LayoutE.g. Standard Cell Layout

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General Logic Structure

• Combinational optimization– keep latches/registers at

current positions, keep their function

– optimize combinational logic in between

• Sequential optimization– change latch

position/function

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Optimization Criteria for Synthesis

The optimization criteria for multi-level logic is to minimize some function of:

1. Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization)

2. Critical path delay of the longest path through the logic3. Degree of testability of the circuit, measured in terms of the

percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g., single or multiple stuck-at faults)

4. Power consumed by the logic gates5. Noise immunity6. Placeability, Wireability7. Manufacturability

while simultaneously satisfying upper or lower bound constraints placed on these physical quantities

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Area-Delay Trade-off

5.2 Two Ｌｅｖｅｌ Ｌｏｇｉｃ Ｓｙｎｔｈｅｓｉｓ

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Example (4 Input & 2 Output ）

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Example (Input Expansion ）

Perform logic simplification for the same output.If output is included by the other output, include theSimplification by adding as * or don’t care.

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Example (Output Reduction ）

(4) Input parts is covered by (2). Output (1 1) is reduced to (0 1).

F = A’B + C’D 　　+ACG= A D + BC’D +AC

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5.3 Ｍｕｌｔｉ Ｌｅｖｅｌ Ｌｏｇｉｃ Ｓｙｎｔｈｅｓｉｓ

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Algebraic Division and Boolean Division

Algebraic DivisionF = g K+r

where no common cube is included in g and K.

F=(a+b)(c+d)+e

The other division is Boolean Division. F=(a+b)(a+c)+e

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Problem of Multi level Logic Synthesis

For several logic functions F[i], try to find common divisors such that

F[i] = g[i] K+r[i]in a sense of algebraic division.---->candidate K is restricted to Kernel, which can divide F[i] in algebraic manner.

Objective function is the number of literals, which corresponds to size of circuit.

F[i]=(ab+a’)(c+d’)+e (#literal =6)

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Kernel

1. Literals: logic variable or its complement such as A, A’, B, B’

2. Cube: logic product of literals such as A, AB, AB’3. Cube free

An expression is cube-free if no cube divides the expression evenly, that is

¬∃ C such that F=QC (no remainder), and C is a cube.

4. KernelThe kernel is a logic sum of product terms, which is a cube free.

5. Co-KernelCo-kernel is a cube, which is a divisor of kernels.

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Kernel

1. Literals: logic variable or its complement such as A, A’, B, B’

2. Cube: logic product of literals such as A, AB, AB’3. Cube free

An expression is cube-free if no cube divides the expression evenly, that is

¬∃ C such that F=QC (no remainder), and C is a cube.

4. KernelThe kernel is a logic sum of product terms, which is a cube free.

5. Co-KernelCo-kernel is a cube, which is a divisor of kernels.

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Logic Design 2

Kernel Example

F=abcd+abce+abef Cofactors={1, ab, abc, abe} Kernels={cd+ce+ef, d+e, c+f}

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Method to find Kernel1. Select literal and divide logic function2. Repeat 1 until cube-free “sum of product” or cube is

derived.[Examples] F=abcd+abce+abef1. select literal a F1=F/a=bcd+bce+bef 1.1 select literal b F2=F1/b=cd+ce+ef: cube-free

(Kernel) 1.1.1 select literal c F3=F2/c=d+e: cube-free (Kernel) 1.1.2 select literal d F3=F2/d=c (cube)

1.1.3 select literal e F3=F2/e=c+f: cube-free (Kernel) 1.1.4 select literal f F3=F2/f=e (cube)

1.2 select other literal x, but F1/x includes cube b2. Select other literal x, but F/x includes cube a

Cofactors={1, ab, abc, abe} Kernels={cd+ce+ef, d+e, c+f}

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Example of State Machine

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a b ｑ1

q0 ｄ 1 ｄ 0

0 0 0 0 0 0

0 1 0 0 0 1

1 0 0 0 １ ０

1 1 0 0 １ 1

0 0 0 1 １ 0

0 1 0 1 1 1

1 0 0 1 0 0

1 1 0 1 0 0

0 0 1 0 1 0

0 1 1 0 1 0

1 0 1 0 1 ０

1 1 1 0 1 １

0 0 1 1 1 0

0 1 1 1 1 0

1 0 1 1 0 0

1 1 1 1 0 0

a b ｑ1

q0

ｄ1

ｄ0

0 0 0 0 0 0

0 1 0 0 0 1

1 0 0 0 0 0

1 1 0 0 0 1

0 0 0 1 0 0

0 1 0 1 1 1

1 0 0 1 0 0

1 1 0 1 1 0

0 0 1 0 1 0

0 1 1 0 1 1

1 0 1 0 1 0

1 1 1 0 1 0

0 0 1 1 1 0

0 1 1 1 1 0

1 0 1 1 0 0

1 1 1 1 1 0

ab∖q1q0

00 01 11

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00

01 1 １ 1

11 1

10ｄ 0=bq1’q0’+a’bq1’+a’ ｂ q0’

d1=q1q0’+a’q1+ ｂ q0

Logic Function I

ab∖q1q0

00

01 11 10

00 1 1

01 1 1 1

11 1 1 １

10 １

21d1=q1q0’+a’q1+ ｂ q0

Logic Function II

Ｄ 0=bq1’q0’+a’bq1’+a‘ ｂ q0’

Ｄ 1=q1q0’+a’q1+ ｂ q0

1) Derivation of Kernel Kernel of d0={q1’q0’+a’q1’+a’q0’, q0’+a’, q1’+q0’ } Co-kernel ={b, bq1’, a’b }

Kernel of d1={q1q0’+a’q1+bq0, q0’+a’} Co-kernel ={1, q1}

2) Step 2 Introducing a new variable c=q0’+a’d0=b(cq1’+a’q0’) =b(cq1’+aq0’)

d1=cq1+bq0

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ｄ 0=bq1’q0’+a’bq1’+a’ ｂ q0’

d1=q1q0’+a’q1+ ｂ q0

Logic Synthesis I

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Technology mapping

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5.4 Scan Path Design

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Scan Path Design

Functional Verification

Logic Synthesis

Scan Path Design

RTL SimulationRTL

Synthesis Netlist

Scan Netlist

Timing Analysis

Functional Verification

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Ｌｏｇｉｃａｌ　Ｆａｕｌｔ　Ｍｏｄｅｌ

1. Stuck-at-0/1 Fault model : Logic value of wire segment is stuck at either logic 0 or logic 1.

2. Single Fault: only one fault happens for each sample.

3. Fault Test: logic circuit is tested by inserting various test input vectors and by observing its output, to check whether any single fault at each wire segment does not occur.

4. ATPG: Automatic Test Pattern Generator is a CAD software to find out necessary input test vectors.

5. Tester: in manufacture factory, tester is implemented so as to check volumes of chips in a short time, automatically.

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Definition Design for testability (DFT) refers to those design

techniques that make test generation and test application cost-effective.

DFT methods for digital circuits: Ad-hoc methods Structured methods:

Scan Partial Scan Built-in self-test (BIST) Boundary scan

DFT method for mixed-signal circuits: Analog test bus

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Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified

design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect

to form one or more shift registers in the test mode. Make input/output of each scan shift register

controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable

faults in the combinational logic. Add shift register tests and convert ATPG tests into

scan sequences for use in manufacturing test.

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Logic Design 4

Scan Path Design

1. Change to Test Mode2. Down load test data to all FF,3. Change to Run Mode4. Run in one clock cycle5. Change to Test Mode6. Outputs result data from all FF to output of LSI.

In test mode, FFs are combined to shift register to set up data of FFsFrom outside of the chip through a test pin. In similar way, FF valuesare outputted to the outside of the chip.

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Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

D

SD

MCK

Q

Q

D flip-flop

Master latch Slave latch

SCK

TCK

Logic

overhead

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Adding Scan Structure

SCANOUT

SFF

SFF

SFF

Combinational

logic

PI PO

SCANINTC or TCK

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Test Pattern Generation

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Fault Table

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　 ① ② ③ ④ ⑤ ⑥ ⑦ ⑧ ⑨ ⑩ ⑪ ⑫ ⑬ ⑭ ⑮ ⑯

0000 ○ ○

0001 ○ ○ ○

0010 ○ ○

0011 　 ○ ○ ○ ○

0100 ○ ○ ○ ○

0101 ○ ○ ○ ○

0110 ○ ○

0111

1000 ○ ○

1001 ○ ○

1010 ○ ○ ○ ○ ○

1011 ○ ○ ○ ○ ○ ○

1100 ○ ○ ○ ○

1101 ○ ○ ○ ○

1110 ○ ○

1111 ○ ○ ○ ○

① ｌ１ /0⑤ ｌ 3/0, l4/1

⑨ ｌ 6/0 ⑬ l8/0

② ｌ１ /1⑥ ｌ 3/1, l4/0

⑩ ｌ 6/1 ⑭ l8/1

③ ｌ 2/0 ⑦ ｌ 5/0 ⑪ l7/0 ⑮ l9/0④ ｌ 2/1 ⑧ ｌ 5/ １ ⑫ l7/1 ⑯ l9/1

Fault Table indicates thecorresponding of test patternsagainst wire faults ① -⑯.The fault ⑤ include stuck-at-0faults for wires l ３ and l4. Theyare called equivalent fault, which cannot be distinguishedby the test at outside.

Five test patterns are selected,which can find inside faultby comparing calculated resultsand measured output againstthe selected test pattern.