ch.9 cpld/fpga design taist ictes program vlsi design methodology hiroaki kunieda tokyo institute of...
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Ch.9 CPLD/FPGA Design
TAIST ICTES ProgramVLSI Design Methodology
Hiroaki Kunieda
Tokyo Institute of Technology
2
Outline
1. CPLD & FPGA2. Design Procedure
9.1 Programmable Device
4
FPGA
Reconfigurable LSI or Programmable Hardware
Programmable Logic Array and Programmable Interconnection
Programmed by Reconfigurable Data Xilinx and Altera Prototyping of ASIC (different physical
condition)
ECE 545 – Introduction to VHDL
The Programmable MarketplaceThe Programmable MarketplaceQ1 Calendar Year 2005
Source: Company reportsLatest information available; computed on a 4-quarter rolling basis
XilinxXilinxAltera
LatticeActel QuickLogic: 2% XilinxXilinx
All OthersAll Others
Two dominant suppliers, indicating a maturing market
PLD Segment FPGA Sub-Segment
Other: 2%
51%33%
5% 7%
AlteraAltera
58%
31% 11%
ECE 545 – Introduction to VHDL
FPGA families
Spartan 3 Virtex 4 LX / SX / FX Spartan 3E Virtex 5 LX
Spartan 3L
Low-cost High-performance
Xilinx
Altera Cyclone II Stratix II
Stratix II GX
Xilinx and Altera FPGA
Xilinx #gates Program
Clock Note
Virtex 50k-10M SRAM 550MHz System
Spartan 5k-300k SRAM 250MHz ASIC
XC9500 13k-85k SRAM 100MHz
Altera #gates Program Clock Note
Stratix 180k SRAM 500MHz High end RAM & Multiplier
Cyclone 16k SRAM 200MHz Low cost
FLEX 10k-250k SRAM 200MHz High Speed
MAX(CPLD)
600-10K EEPROM 150MHz Low Price
9.2 PLD
9
CPLD
Function Block in CPLD
Example of PLD Design
S 1 S 2 S 3 X
S 1 S 2 S3 Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 * 0 1 1 0
0 1 1 * 1 1 1 0
1 1 1 * 1 1 0 0
1 1 0 * 1 0 0 0
1 0 0 * 0 0 0 1
000
001
011
111
110
100
X=0
X=1State Transition Table
Y=1
PLA & FF Realization
S 1 S 2 S 3 X
DS 1 DS 2 DS3 Y
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 * 0 1 1 0
0 1 1 * 1 1 1 0
1 1 1 * 1 1 0 0
1 1 0 * 1 0 0 0
1 0 0 * 0 0 0 1
S1 DS1
PLAAND-OR
S2 DS2
S3 DS3
X Y
DFF
DFF
DFF
9.3 FPGA
ECE 545 – Introduction to VHDL
Blo
ck R
AM
s
Blo
ck R
AM
s
ConfigurableLogicBlocks
I/OBlocks
Xilinx FPGA
BlockRAMs
ECE 545 – Introduction to VHDL
CLB CLB
CLB CLB
Logic cell
Slice
Logic cell
Logic cell
Slice
Logic cell
Logic cell
Slice
Logic cell
Logic cell
Slice
Logic cell
Configurable logic block (CLB)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Xilinx CLB
LUT <Look Up Table>
LUT Structure
Interconnection
Logic BlockLogic Block
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Advantages and Disadvantages
Advantages Short TAT(Turn-Around Time) Small NRE (Non Recurrent Expense) Fee Logic and Timing Design are required. Full amount of IP (Intellectual Property)
Disadvantages Slow speed and Large Chip Area High cost for volume manufacturing
9.4 FPGA Design
FPGA Design
Functional Verification
Logic Synthesis
RTL SimulationRTL
Synthesis Netlist
Gate AssignmentLE Place and Rout
ConfigurationData
FPGA Tool
LSI Tool
FPGA Design Flow
1 bit Adder/Subtracter
4bit Adder/Subtracter
FPGA Design
Three-Step Design Compilation in Quartus II Software
1. Run the New Project Wizard
a. Specify project directory, name, and top-level entity.
b. Specify project design files.c. Specify Altera device family for the design.d. Specify device (or specify device information for
automatic device selection).e. Specify other EDA tools to be used for this project.f. Review project settings.
2. Run the TimeQuest Timing Analyzer
a. On the Process menu, click Start Analysis & Synthesis to build a netlist in preparation for TimeQuest timing analyzer use.b. On the Tools menu, click TimeQuest Timing Analyzer to launch TimeQuest analyzer. i. On the Netlist menu, click Create Timing Netlist and select Post- map to create the timing netlist with timing delay information. ii. Specify your design timing constraints using the analyzer’s graphical user interface (GUI) or by using the Synopsys Design Constraint (SDC) text editor.c. On the Assignment menu, click Timing Analysis Settings to specify TimeQuest analyzer as the timing analysis tool and to add your SDC file to the project.
Quartus II Assignment menu provides all settings and assignments for the project.
3. Compile the Design
a. Select one of the following methods to compile the design: i. On the Processing menu, click Start Compilation. ii. On the menu toolbar, click . iii. On the Processing menu, click Compiler Tool and click Start.b. When compilation is complete, refer to the Compilation Report window to view information on compiler settings, resource usage, and compilation equations.
Timing analysis is also performed during compilation on the current design, and the Compilation Report window includes the timing information.
9.5 Optimization
Trade-offs
speed area
power testability
Speed optimization (1)
better architecture (e.g., CLA vs. ripple carry adder)
pipelining parallel processing optimization options of synthesis
and implementation tools
ECE 545 – Introduction to VHDL
Speed optimization (2)
reducing fanout of control signals better state encoding registered outputs from the state
machine