deposition and etching of thin films nathaniel j. c. libatique, ph.d. [email protected]
TRANSCRIPT
Sze, Semiconductor Devices, John Wiley and Sons
Process StepsProcess Steps
• Start with polished wafers of chosen and crystal orientation• Films: epitaxial, thermal oxides, polysilicon, dielectrics, metals• Doping: via diffusion or ion implantation• Lithography: shadow masked or projection• Etching: Wet and Dry• Sequential Mask Transfer• Stepper Iteration
Starting MaterialsStarting Materials
Quartzite + carbon sources (coal, coke, wood chips)
• SiC(solid) + SiO2(solid) Si(solid) + SiO(gas) + CO (gas)provides metallurgical grade silicon (98%)
• Pulverize silicon and treat with HCl to produce trichlorosilane Si(solid) + 3 HCl(gas) 300oC SiHCl3(gas) + H2(gas)trichlorosilane liquid at RT. Fractional distillation.
Purified trichlorosilane in hydrogen reduction reactionSiHCl3(gas) + H2(gas) Si(solid) + 3HCl(gas)EGS (electronic grade Si) is produced. Ppb impurities. Poly.
(Elemental Ga and As are the starting materials for GaAs poly)
http://csmres.jmu.edu/geollab/Fichter/MetaRx/Rocks/quartzite1.html
Sze, Semiconductor Devices, John Wiley and Sons
Single CrystalSingle Crystal
• Furnace• Pulling Mechanism• Ambient Control
rotation mechanism, heating elements and power supply, seed holder, rotation mechanism, Ar gas, gas flow, exhaust, temperature, Si diameter, pull rate, rotation speed
Wafer FlatsWafer Flats• Grind to fixed diameter, edge grind for auto placement algos
• Secondary flats reveal conductivity and type
• Slice determines orientation, thickness, taper (t variation), bow (center to edge)
• Lap with Al2O3 and glycerine, flatness within 2 m
• Etch and polish
Sze, Semiconductor Devices, John Wiley and Sons
Deposition TechniquesDeposition Techniques
• Thermal Oxidation• Evaporation: Thermal & E-Beam• Sputtering• Vapor Phase Epitaxy• Molecular Beam Epitaxy
www.cnfusers.cornell.edu/
Thermal OxidationThermal OxidationMany films depositedon semiconductors
Native film advantages:- no deposition reqrd- relatively pure- excellent interface-device passivation
Silicon DioxideSilicon Dioxide
SiO2 on Si under fluorescent lighting
• Native Oxide = 15 to 20 Ang.• Si + O2 SiO2 ; dry• Si + 2H2O SiO2 +2 H2 ; wet• Wet Oxidation: H2 rapid diff’n
Oxide layer 2.7 times thicknessof consumed silicon
Thermal EvaporationThermal Evaporation• Electron Beam Evaporation gun • A System Controller , Power Supply • Crucibles for the evaporation material, Materials for Evaporation • Material to be coated PLUS
Substrates < 100 CHigh deposition rateSimple procedure
MINUSMetalsPoor layer adhesionUneven or structured surfaces
100 meV Energies
SputteringSputtering
1 to 20 eV Energies better adhesionOxides, ceramics, alloys, semiconductors, glasses
CVDCVD
AX(gas) + BY(gas) AB(solid) + XY(gas)
SiH4 + 2 N2O SiO2 + 2N2 + 2H2
SiH4 + NH3 SixNyHz + H2
LPCVDLPCVD
• Separate effusion chambers (pyrolitic boron nitride)• Ultra-high vacuum• Arsenic overpressure• E-Gun for Si Sze, Semiconductor Devices, John Wiley and Sons
Molecular Beam EpitaxyMolecular Beam Epitaxy
5 to 30 cm
Mean Free PathMean Free Path
d
cS = Collision cross section = r2
n particles in a volume V
c dt
S
V
One collision only if
(n/V) r2 c dt = [(n/V) r2 ]-1
Ultra-High Vacuum Ultra-High Vacuum RequiredRequired
= [(n/V) r2 20.5 ]-1
= kT/ (20.5 r2 P)P = nkT/V
At room temperature
cm = 5 x 10-3 / P (in Torr)
Typical value, 3 Angstrom for d, so about 0.5 x 103 cm for partial pressures of 10-5 Torr
Nucleation and GrowthNucleation and Growth
• Incident Flux• Surface diffusion until attachment• Desorption, higher probability for crystals adsorbed on a low binding energy site• Binding energies also function of surface, <111> slower growth rate than <100> in silicon• Surface preparation is key
Binding EnergiesBinding Energies
1 nearest neighbor, 2 second nearest neighbors1, 2, 3, 4 4, 6, 6, 8Ghandi, VLSI Fabrication Principles, 2nd Ed., John Wiley and Sons
Special ConsiderationsSpecial Considerations
• Off axis growth, say 2 to 4 degrees, series of steps and kinks are introduced• Elevated substrate temperatures increase surface diffusion (Ea,surface is 25% to 50% Ea,bulk)• Si (111) planes more easily stacked than (100), plane to plane distance is 57% of (111), better morphology• GaAs special.
Ghandi, VLSI Fabrication Principles, 2nd Ed., John Wiley and Sons
Successive Layers two dangling bonds, alernate Ga and As deposition
Double layers separated by a wide spacing. One dangling bond. yy’ signinficantly different from xx’. Significant surface energy change.
GaAsGaAs
Surface MorphologySurface Morphology
ComparisonComparison
[Gerlach and Dotzel]
EtchingEtching
• Si 20 .. 40 • SiO2 30 .. 40• Au 140
Etch rates in nm/min for ion beam etch (Ar+, 0.5 keV, ion flow at 1 mA/cm)
• Al 30• PR AZ 1350 20 .. 30
ComparisonComparison
Wet Etch: AnisotropicWet Etch: Anisotropic
ReferencesReferences
G. Gerlach and W. Dotzel, G. Gerlach and W. Dotzel, “Introduction to Microsystem “Introduction to Microsystem Technology, A Guide for Students”, Technology, A Guide for Students”, Wiley, ISBN 978-0-470-05861-9Wiley, ISBN 978-0-470-05861-9