development of drc calibre decks for dsm process

8/6/2019 Development of Drc Calibre Decks for Dsm Process

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byChandan T KChandru NKarthik K SVinay M V

DEVELOPMENT OF DRC CALIBRE

DECKS FOR DSM PROCESS


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CONTENTSy INTRODUCTIONy FULL CUSTOM FLOWy SEMI CUSTOM FLOWy DESIG N PROCESSy IMPORTANCE OF DRCy PERFORMANCE ANALYSIS AND OBSERVATIONy FUTURE TRENDSy CONCLUSION


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INTRODUCT ION


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INTRODUCT IONy Up until the 1950s electronic active device technology was

dominated by the vacuum tube and, although a measure of miniaturization and circuit integration did take place, thetechnology did not lend itself to miniaturization as we havecome to accept it today. Thus the vast majority of present dayelectronics is the result of the invention of the transistor in1947.


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Introductiony A topological design rule check is a mandatory check that is

done by the full custom and semi-custom (ASIC) physicalengineer.

y

To ensure that theG

DS that is sent for fabrication formasking and fabrication complies with the topological layoutrules of the respective fabrication, a DRC deck has to bedeveloped from scratch. Todays deep sub-micron (DSM)processes have numerous mask and processing steps.

y These rules comprise of checking for minimum dimension,spacing and connectivity based checks


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Ev olution of I Cs

y The very firstIC emerged at the beginning of 1960 and since that time there have already been fivegenerations of ICs:

y SSI (small scale integration)y MSI (medium scale integration)y LSI (large scale integration)y VLSI (very large scale integration)y ULSI (ultra large scale integration)


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M oore s lawy According to Moores Law, the number of transistors on a

chip roughly doubles every two years. As a result the scalegets smaller and smaller.


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M oore s Law


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F ull cu s tom de s ign flow

y Full-custom design specifies the layout of eachindividual transistor and the interconnections between them.

y Circuits involving smaller count of transistorsy Ideally to fabricate analog circuits


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F ull cu s tom de s ign flowy Full-custom design is limited toICs that are to be fabricated

in extremely high volumes, notablycertain microprocessors and a small number of ASICs.


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F ull cu s tom de s ign

flow


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F ull cu s tom de s ign flowAdvantages

y Each circuit elementcarefully handcrafted.

y

Low Unit Cost.y Typically used for high-

volume applications.y High Performance.

Di sadvantagesy High NRE Costs.y Laborious Design Process.y Circuit designer has to plan

every single detail of the block.

y Mask designer has to draw

every polygon of the layout before we can have fullyrouted design.


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F ull cu s tom de s ign flowAppl ic at io ns :

y Usually applied for large scale production.

y Largely applicable in analog back-end processes


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S emi cu s tom de s ign flow(AS IC flow)y An application-specific integrated circuit (ASIC-flow) is

an integrated circuit (IC) customized for a particular use,rather than intended for general-purpose use.

y

Modern ASI

Cs often include entire 32- bit processors, memory blocksincluding ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a system-on-a-chip.


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S emi cu s tom de s ign flow


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S emi cu s tom de s ign flowy . Designers of digital ASICs use a hardware description

language (HDL), such asVerilog orVHDL, to describe thefunctionality of ASICs.


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S emi cu s tom de s ign flowAdvantages

y Improves custom circuitdesigners productivity.

y Allows control over customplacement and routing.

y Encourages designers to focuson critical parts of the design.

y Utilizes standard Place andRoute tools for non-criticalparts of design

Di sadvantagesy For smaller designs semi

custom design is not costeffective.

y For lower productionvolumes usage of semicustom may run into themillions of dollars which is

unnecessary.


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S emi cu s tom de s ign flowAppl ic at io ns of ASIC Pr oc ess:y Used in Videoconferencing Systemy Mixed Signal PCBAnalog and Digitaly Hardware Acceleration in FPG Ay Power over Ethernet.


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Th e DRC proce ss

y A design rule check(DRC) is a mandatory check that is done by the full custom and semi-custom (ASIC) physical engineer


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development of drc calibre decks for dsm process

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