integrated circuits & systems

Lecture 24 Memory & Array Structures – 2

Original slides prepared by Prof. Luiz C. V. Santos (from J. Rabaey’s, A. Chandrakasan’s, and B. Nikolic’s book)

Prof. José Luís Güntzel [email protected]

Integrated Circuits & Systems INE 5442

Federal University of Santa Catarina Center for Technology

Computer Science & Electronics Engineering

Memory & Array Structures

Lecture 24 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 24.2

  Static (SRAM)   Data stored as long as supply is applied   Large (6 transistors/cell)   Fast   Differential

  Dynamic (DRAM)   Periodic refresh required   Small (1-3 transistors/cell)   Slower   Single Ended

Read-Write Memories

Efficiently implemented in same technology as processor cores in SoCs: embedded memories

It requires special technology to allow high densities: external memories

Source: Rabaey; Chandrakasan; Nikolic, 2003




WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell





WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell

1 0

(Stored bit)

Read




WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell

VDD 0

(Precharge)

Read VDD VDD




WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell

VDD 0

(Word line selection)

Read VDD VDD

VDD




WL

BL V DD

M 5 M 6

M 4

M 1 V DD V DD V DD

BL Q = 1 Q = 0

C bit C bit

Ripple here must be small so as to avoid flipping Q

Since ΔV is small, M5 is saturated: VDS = VDSATn

VD

D

GND

ΔV

M5 must be weaker than M1

CMOS SRAM Analysis (Read)





WL

BL V DD

M 5 M 6

M 4

M 1 V DD V DD V DD

BL Q = 1 Q = 0

C bit C bit






0 0

0.2

0.4

0.6

0.8

1

1.2

0.5 1 1.2 1.5 2 Cell Ratio (CR)

2.5 3

Volta

ge R

ise

ΔV

(V)

For higher density: min W1 and min L1 → min W5, larger L5 → CWL↑


Adapted from: Rabaey; Chandrakasan; Nikolic, 2003

0.25 µm tech.




For performance: min W5 and min L5 → larger W1, min L1 → Cell area↑



0 0

0.2

0.4

0.6

0.8

1

1.2

0.5 1 1.2 1.5 2 Cell Ratio (CR)

2.5 3

Volta

ge R

ise

ΔV

(V)

0.25 µm tech.




Read upset immunity enforced since VQ clamped at VDD by BL

Read upset immunity improved if precharge to VDD/2

Read time must be accelerated by sense amplifier

Read Robustness and Performance

WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

VDD 0

VDD VDD

VDD




WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell

1 0

(Stored bit)

Write





WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell

1 0

(Driving bit lines)

Write 0 1




WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

6-T CMOS SRAM Cell

(Driving bit lines)

Write 0 VDD

VDD 0

VDD




Due to sizing for Read, this value is kept below 0.4V:

BL must flip Q. VDD

GND

VQ

When VQ is small, M4 is saturated: VDS = VDSATp

M4 must be weaker than M6

CMOS SRAM Analysis (Write)


BL=1 BL=0

Q = 0 Q = 1

M 1

M 4

M 5 M 6

V DD

V DD WL

BL does not flip Q !




BL = 1 BL = 0

Q = 0 Q = 1

M 1

M 4

M 5 M 6

V DD

V DD WL






W4/L4

W6/L6 PR =

Due to read sizing: min W6 and min L6 → min L4, larger W4?

Even with min W4, Write is realiable! (since PMOS is weaker than NMOS)



Pull-up Ratio (PR)

Cel

l Vol

tage

VQ [V

] 0.25 µm tech.




Very robust since it relies on stronger BL driver

Write time dominated by delay of cross-coupled inverter pair

WL

BL

V DD

M 5 M 6

M 4

M 1

M 2

M 3

BL

Q Q

0 VDD

VDD 0

VDD

Write Robustness and Performance





VDD

GND

Q Q

WL

BL BL

M1 M3

M4 M2

M5 M6

6-T SRAM Layout





“This memory comes from my memories (18 years ago)” Designed at UCL, Louvain-la-Neuve, Belgium, 1990. (Source: Luiz Santos, MSc dissertation)

6-T SRAM: Mirrored Layout




••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word

Wired-NOR Match Line

••• CAM

Static CAM Memory Cell





S

S

BIT

BIT

INT

BIT S INT

0 0 1

0 1 0

1 0 0

1 1 1

INT = BIT ⊕ S

CAM Cell Requires 1-Bit Comparator





••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word


••• CAM






••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word


Match M1 M2

M7 M6 M4 M5 M8 M9

M3 int S Word

••• CAM

Bit Bit

S






••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word


Match M1 M2

M7 M6 M4 M5 M8 M9

M3 int S Word

••• CAM

Bit Bit

S

6T-SRAM cell





••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word


Match M1 M2

M7 M6 M4 M5 M8 M9

M3 int S Word

••• CAM

Bit Bit

S

2T-comparator





••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word


Match M1 M2

M7 M6 M4 M5 M8 M9

M3 int S Word

••• CAM

Bit Bit

S

1T-discharger





••• •••

CAM

Bit Word

Bit

••• CAM

Bit Bit

CAM

Word


Match M1 M2

M7 M6 M4 M5 M8 M9

M3 int S Word

••• CAM

Bit Bit

S

All match lines precharged; all but one discharged (at best) → Pdyn↑





CAM ARRAY

Input Drivers

Tag

SRAM ARRAY

Sense Amps / Input Drivers

Data

Add

ress

Dec

oder

Address

Hit

Logi

c

Hit R/W

CAM in Cache Memory





CAM ARRAY

Input Drivers

Tag

SRAM ARRAY

Sense Amps / Input Drivers

Data

Add

ress

Dec

oder

Address

Hit

Logi

c

Hit R/W Cache controller Datapath Status/Control

CAM in Cache Memory




[R. Banakar, S. Steinke, B.-S. Lee, 2001]

Ecache = 3,5 a 4,0 x ESPM

Ecache = 2,25 a 2,7 x ESPM

The Impact of the CAM Array




 Embedded Memories   6T SRAM cell: SPM   9T CAM cell + 6T SRAM cell: cache

 Energy Efficiency   SPM is promising (no CAM)   But requires embedded SW optimization

Conclusions




Reference

1.  RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3

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