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Lecture 1 Technology evolution. design representation,
design metrics
Prof. José Luís Güntzel [email protected]
Integrated Circuits & Systems INE 5442
Federal University of Santa Catarina Center for Technology
Computer Science & Electronics Engineering
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.2
Historical Perspective The use of Digital Electronics in different application domains (a chronology):
1. Digital data manipulation
2. Instrumentation & control
3. Telecommunications & consumer electronics
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.3
The First Automatic Calculator (Computer?)
Charles Babbage’s Difference Engine I (1832) • 25.000 mechanical parts • Price: £17,470 • Decimal-coded data
© Jan Rabaey et al. 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.4
ENIAC: The First Electronic Computer Year: 1946 18.000 vacuum tubes Intended for computing artillery firing tables Problems: • low reliability • excessive power consumption
© Jan Rabaey et al. 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.5
The First Transistor Bell Labs. 1948
© Jan Rabaey et al. 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.6
Bipolar Junction Transistor 1949 - Schockly introduces the bipolar transistor
base
colector
emiter
ib ic
ie
Approximate behavior:
if ib < imin ⇒ ie = 0
if ib > imin ⇒ ie ≈ ic
The base current controls the emitter current
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.7
Key Dates 1949 - Schockly introduces the bipolar junction transistor
1956 - first bipolar digital logic gate, made by discrete components (by Harris)
1958 - Jack Kilby (Texas Instruments) conceives the integrated circuit (all components are integrated on a single semiconductor substrate). He was awarded the Nobel prize
1960 - first set of IC commercial logic gates, the Fairchild Micrologic family
1962 - TTL (transistor-transistor logic) IC logic family is launched as commercial product, given rise to some large semiconductor companies, Fairchild, National and Texas Instruments.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.8
MOSFET (Metal-Oxide Silicon Field-Effect Transistor)
1925 - The MOSFET is proposed in a patent by J. Lilienfeld (Canada) 1935 – Independently, O. Heil proposes the MOSFET in a patent
(England) Problems concerning materials and the fabrication process postpone the
commercial use of MOS technology 1960 - MOS ICs with PMOS-only logic gates (used in calculators) 1971 - the Intel 4004, first microprocessor, uses NMOS technology 1970 - first MOS memory (4kbits) 1978 - Intel launches the 8080 microprocessor in NMOS technology 1980 - new fabrication processes allow the integration of both NMOS and
PMOS devices in the same IC. Consequence: reduction in power and increase of integration.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.9
The First Microprocessador
Intel 4004 (1971)
1,000 transistors 1 MHz operation frequency
© Jan Rabaey et al. 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.10
Pentium 4
© Jan Rabaey et al. 2003
Year: 2000
42M transistors 3 GHz
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.11
Itanium 2 (Year: 2003)
410M transistors 374 mm2 die size 6MB on-die L2
cache 1.5 GHz at 1.3V
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.12
Number of Transistors in a Single Die
Source: Intel Corporation. http://www.intel.com/museum/archives/history_docs/mooreslaw.htm
Intel Processors (until 2004)
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.13
Moore’s Law
Gordon E. Moore, Co-founder, Intel Corporation. Source: http://www.intel.com/museum/archives/history_docs/mooreslaw.htm
“The number of transistors incorporated in a chip will approximately double every 24 months.” Gordon Moore, Co-Founder Intel Co., 1965
Electronics, April 19, 1965.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.14
Number of Transistors in a Single Die
1,000,000
100,000
10,000
1,000
10
100
1 1975 1980 1985 1990 1995 2000 2005 2010
8086 80286
i386 i486
Pentium® Pentium® Pro
K 1 billion transistors
Fonte: Intel
Pentium® II Pentium® III
Pentium 4: 42M tr. Core 2 Duo: 291M tr. Core 2 Quad: 582M tr.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.15
Moore’s Law (until the year 2000)
5KW 18KW
1.5KW 500W
4004 8008 8080 8085 8086 286 386
486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Pow
er (W
atts)
P6 Pentium ® proc
486 386 286 8086 8085
8080 8008 4004 0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Freq
uenc
y (M
hz)
Doubles each 2 years
4004 8008 8080
8085 8086 286
386 486 Pentium® proc P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010
Tran
sisto
rs (M
T) Grows 2X in 1.96 years!
• # of transistors • Power • Clock frequency
Source: Rabaey; Chandrakasan; Nikolic, 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.16
Power and clock rate are correlated...
Source: Patterson; Hennessy. 2009
The Power Wall
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.17
Para desktops, há um limite prático de resfriamento que restringe a potência máxima a 100W
Source: Patterson; Hennessy. 2009
The Power Wall
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.18
Consequência: mudança de paradigma nos microprocessadores
Source: Patterson; Hennessy. 2009
The Power Wall
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.19
Core 2 Duo (Year: 2006)
291M transistors 374 mm2 die size 6MB on-die L2
cache 1.5 GHz at 1.3V
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.20
http://www.mpsoc-forum.org/2007/slides/Hattori.pdf
SH-Mobile G1: an MPSoC (Year: 2006/2007)
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.21
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./Chip Tr./Staff Month.
x x x x
x x
x 21%/Yr. compound
Productivity growth rate
x
58%/Yr. compounded Complexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c Tr
ansi
stor
per
Chi
p (M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
duct
ivity
(K
) Tra
ns./S
taff
- Mo.
Source: Sematech
Com
plex
ity
Courtesy, ITRS Roadmap
The Productivity Gap
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.22
CMOS Scaling Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per
chip; chip cost does not increase significantly Cost of a function decreases by 2x But …
How to design chips with more and more functions? Design engineering population does not double every two
years… Hence, a need for more efficient design methods
Exploit different levels of abstraction
Source: Rabaey; Chandrakasan; Nikolic, 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.23
Levels of Abstraction
+ n n
n
Transistor Level
Electric Level
Logic Level RT Level MIPS
$-I
ucart
$-D
DPS
Bar.
System Level
Design Representantion
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.24
Design “Visions”
Design Representantion
Descrição Estrutural • Utiliza-se um conjunto de blocos e conexões que representam uma
possível implementação do sistema eletrônico. Pode-se usar linguagem de descrição de hardware (HDL) ou esquemáticos (em papel ou usando algum editor de esquemático).
Descrição Comportamental • Faz uso de texto em linguagem natural, HDL ou equações para descrever
como o sistema eletrônico se comporta (i.e., funciona).
Descrição Física • usada para implementaro sistema eletrônico. No caso de fabricação do
chip com tecnologia CMOS, descrição das geometrias das máscaras que serão usadas no processo de litografia fina.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.25
Levels of Abstraction
Design Representantion
Nível de Transistores: • Transistores, • Resistores, • Capacitores, • Indutores e • Fios. Nível Lógico: • Portas lógicas, • Latches e • Flip-flops.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.26
Levels of Abstraction
Design Representantion
Nível RT (Register Transfer): • Unidades funcionais (somadores, subtratores,
somadores/subtratores, multiplicadores etc) • Rede de interconexão (fios, multiplexadores,
decodificadores, barramentos, buffers tri-state) • Registradores e blocos de memória RAM, ROM etc Nível de Sistema: • Processadores de uso genéricos (CPUs), • Processadores para domínios específicos (ASIPs), • Processadores específicos (ASICs), • Barramentos, • Memórias, • Software embarcado.
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.27
Syntesis and Automatic Synthesis
Design Representantion
Síntese: Traduz uma dada descrição de um sistema eletrônico para uma nova descrição (sendo esta nova descrição em um nível inferior de abstração) por meio da adição de detalhes de implementação.
Síntese Automática: Síntse realizada com o auxílio de ferramentas computacionais (atualmente referenciadas por ferramentas de EDA- Electronic Design Automation).
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.28
Synchronous Digital Systems
Design Strategies
Registers are used to provide data barriers
Clock period R1
n
n
R2
k
k
Combi. logic ck
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.29
How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function
Source: Rabaey; Chandrakasan; Nikolic, 2003
Quality Metrics of Digital Design
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.30
Fixed or NRE (non-recurrent engineering) costs: Design time and effort, mask generation One-time cost factor
Variable or Recurrent costs: Silicon processing, packaging, test Proportional to volume Proportional to chip area
Source: Rabaey; Chandrakasan; Nikolic, 2003
Quality Metrics of Digital Design
Cost of Integrated Circuits
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.31
Cost of Integrated Circuits
Quality Metrics of Digital Design
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.32
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm) Source: Rabaey; Chandrakasan; Nikolic, 2003
Quality Metrics of Digital Design
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.33
Cost per Transistor
Source: Rabaey; Chandrakasan; Nikolic, 2003
Fabrication capital cost per transistor (Moore’s law)
Quality Metrics of Digital Design
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.34
Quality Metrics of Digital Design
Yield
Source: Rabaey; Chandrakasan; Nikolic, 2003
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.35
Defects
Source: Rabaey; Chandrakasan; Nikolic, 2003
α is approximately 3
Quality Metrics of Digital Design
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.36
Examples (1994)
Source: Rabaey; Chandrakasan; Nikolic, 2003
Chip Metal layers
Line width
Wafer cost
Def./ cm2
Area mm2
Dies/wafer Yield Die cost
386DX 2 0.90 $900 1.0 43 360 71% $4
486 DX2 3 0.80 $1200 1.0 81 181 54% $12
Power PC 601 4 0.80 $1700 1.3 121 115 28% $53
HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73
DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149
Super Sparc 3 0.70 $1700 1.6 256 48 13% $272
Pentium 3 0.80 $1500 1.5 296 40 9% $417
Quality Metrics of Digital Design
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.37
The Semiconductor Industry
Apenas Componentes (dados de 2004)
• Mercado de aprox. U$ 150 bilhões/ano • Mercado de sistemas eletrônicos é de aprox. U$ 1
Trilhão • 2.6 Km2 de CIs (a maior parte em CMOS) produzidos
por ano • Custo da fabricação: aprox. U$ 75 000/m2
• 1018 transistores produzidos por ano
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.38
The Semiconductor Industry
ST/Philips/Motorola Foundry in Crolles/Grenoble (FR)
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.39
The Semiconductor Industry
CEITEC (Porto Alegre, Brazil)
Design House
Foundry
http://www.ceitec-sa.com/
Technology Evolution
Lecture 1 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 1.40
References
Rabaey J.; Chandrakasan A.; Nikolic B. “Digital Integrated Circuits: a design perspective.”, 2nd Edition, Prentice Hall, USA, 2003.
Patterson, D.; Hennessy, J. “Computer Organization and Design: the hardware/software interface.” 4th Edition. Morgan Kaufmann, 2009.