Modeling and calibration of ADP process for inductancecalculation with InductEx

Coenrad Fourie1, Xizhu Peng2, Akitomo Takahashi2, Nobuyuki Yoshikawa2

1) Department of Electrical and Electronic Engineering, Stellenbosch University, Stellenbosch, South Africa2) Faculty of Engineering, Yokohama National University, Yokohama, Japan

IntroductionThe AIST advanced process (ADP2) with 9 Nb layers and and 1 m minimum Josephson junction size is most complicated low-Tc process in operation.

All layers below main ground plane are planarized, and con-ductors may traverse several layers.

Inductance modeling for numerical calculations requires atten-tion to capabilities of extraction tool.

We present improvements made to InductEx to model the ADP process, including support for selective layer planarization, multiple ground planes and conductors below a ground plane, as well as layer defi nition fi le parameters for ADP2.

References[1] C. J. Fourie, O. Wetzstein, T. Ortlepp and J. Kunert, “Three-dimensional multi-terminal superconductive integrated circuit inductance extraction,” Supercond. Sci. Technol., vol. 24, 125015, 2011.[2] C. J. Fourie, M. H. Volkmann and R. M. C. Roberts, “InductEx: a programme for multi-terminal superconductive circuit inductance calculation,” unpublished.[3] M. M. Khapaev, “Inductance extraction of multilayer fi nite-thickness superconductor circuits,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 217-220, 2001.[4] M. M. Khapaev, M. Yu. Kupriyanov, E. Goldobin and M. Siegel, “Current distribution simulation for superconducting multi-layered structures,” Supercond. Sci. Technol., vol. 16, pp. 24-27, 2003.[5] P. I. Bunyk and S. V. Rylov, “Automated calculation of mutual inductance matrices of multilayer superconductor integrated circuits,” in Proc. Ext. Abstracts 4th Int. Supercond. Electron. Conf. (ISEC’93), Boulder, CO, 1993, p. 62.[6] S. Nagasawa, et al., “New Nb multi-layer fabrication process for large-scale SFQ circuits,” Physica C, vol. 469, pp. 1578-1584, 2009.[7] T. Kainuma, Y. Shimamura, F. Miyaoka, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, K. Takagi, N. Takagi, S. Nagasawa, “Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm2 Nb Process,” IEEE Trans. Appl. Superconductivity, vol. 21, pp. 827–830, 2011.[8] M. Kamon, M. J. Tsuk and J. K. White, “Fasthenry: A multipole-accelerated 3-d inductance extraction program,” IEEE Trans. Microwave Theory Tech., vol. 42, pp. 1750-1758, 1994.[9] C. J. Fourie, InductEx User’s Manual, Stellenbosch Univ., Jan. 2013. [Online]. Available: http://www.sun.ac.za/inductex[10] Stellenbosch University, C. J. Fourie, inp2dxf. [Online]. Available: http://www.sun.ac.za/inductex[11] K. Ehara, A. Takahashi, Y. Yamanashi and N. Yoshikawa, “Development of pulse transfer circuits for serially biased SFQ circuits using the Nb 9-layer 1-�m process,” IEEE Trans. Appl. Supercond., vol. 23, p. 1300504, 2013.[12] C. J. Fourie, “Calibration of inductance calculations to measurement data for superconductive integrated circuit processes,” IEEE Trans. Appl. Supercond., vol. 23, p. 1301305, 2013.

Practical exampleTo test InductEx modeling accuracy for ADP2, we calculated L1, L2 and coupling factor k for 4 magnetic coupling structures [11].

We used no calibration [12], segment size = 1.5 m, height fi laments = 1.

The results compared to measurements in Table 1 show good agreement.Table I: Calculated and measured inductance L1, L2 and coupling coeffi cient k of several SFQ pulse

transfer coupling structures [11].

Coupling structureL1 (COU) [pH] L2 (BAS) [pH] k

Calculated Measured Calculated Measured Calculated MeasuredHole version 12.0 10.8 10.3 10.5 0.56 0.55

Narrow hole version 11.5 10.9 8.7 7.9 0.48 0.50Covered version 10.9 10.1 8.6 7.9 0.53 0.55Extra covered

version9.7 8.9 8.3 7.7 0.49 0.53

BackgroundMost superconductive IC processes are unplanarized: up-per layers are deformed in height due to structures below.

InductEx [1], [2], a 3D inductance extraction tool, was de-veloped to handle such layer bumps and offsets. This sets it apart from 3D-MLSI [3], [4] and Lmeter [5], which assume planar structures.

The AIST ADP2 process uses complemented caldera pla-narization [6] in all but the upper two conductive layers, re-quiring a selective planarization strategy for extraction tools.

Fig. 3. Magnetically coupled SFQ transfer circuit [11] (reproduced with permission from IEEE).

InductEx Homepage:

www.sun.ac.za/inductex

Fig. 4. Cross-sectional sliced rendering of InductEx inductance calculation model for an SFQ pulse transfer circuit in the ADP2 process to correspond to Fig. 3 [11]. Th e ver-tical dimension is enlarged 2 times for clarity. Planarization and ground plane delimits

for layers DCP to GND3 can be seen. Layers BAS and COU are not planarized.

Fig. 5. Segment view of InductEx model from Fig. 4.

Fig. 2. Cross-sectional rendering of the 3D model created by InductEx for the structure pictured in Fig. 1. Dimensi-ons are exactly to scale. All layers from M1 to M7 are plana-rized. Layer M10, although not present in the current ADP2 process, was added to compare the InductEx model with the

SEM photograph in Fig. 1.

Fig. 1. Cross-sectional SEM photograph of IC fabricated with the ADP2 process. Layer M7 is the main ground plane, and lay-er M10 is the control layer (CTL) that is not present in the cur-

rent ADP2 process. (Courtesy of Dr. Hidaka at AIST).

ConclusionAddition of selective layer planariza-tion and multiple ground plane sup-port to InductEx, as well as customized layer definition file, allow us to model 9-layer AIST ADP2 process with good accuracy.

We can now develop complex induc-tive coupling structures such as those in [11] with a high degree of confidence.

AIST AdvancedProcess ADP2

Based on Nb IC process developed in ISTEC [6].

Multi-layer fabrication process for large-scale Jo-sephson ICs.

Nine Nb layers, of which bottom 7 are planarized.

Active layers including Josephson junctions placed on top, and interconnection layers with supercon-ductive passive transmission lines (PTLs) are formed below the active layers. Two PTL layers are completely shielded by ground planes, making fl exible interconnection possible. DC power layer (DCP) placed at bottom of device structure, con-siderably reducing the infl uence of magnetic fi eld from bias currents.

Large-scale circuits are under development in AIST-ADP2 [7].

Modeling ADP2 with InductExPlanarization acts on isolation layers, and allows metal layers to lie evenly except over via connections.

InductEx models 3D IC structures with interleaved segments [1], [2], and uses magnetoquasistic fi eld solver FastHenry [8] to calculate current dis-tribution. Segments are formed between nodes at the segment end points.

Height of nodes (z offset) calculated by examining x and y coordinates on every layer below that of node, and adding heights of positive layers with objects and negative layers with no objects: “object dependent z offset”.

For planarization we set z offset as cumulative height of all layers below that of node. For the z offset of higher, unplanarized layers, we add object dependent offset to the height of the last planarized layer.

Planarization added to layer defi nition fi le with “PlanarModel” layer pa-rameter [9]. For ADP2, we set “PlanarModel=1” for all 6 isolation (via) lay-ers between M1 and M7 (main GP), as well as for isolation layer between M7 and the resistive layer. This allows InductEx to model via depressions as seen in ADP2 (see Fig. 1 and Fig. 2, which shows good agreement).

ADP2 also uses multiple negative-mask ground planes, which by default exist everywhere. To limit these for 3D models, an automated ground plane delimitation routine was added to InductEx.

As an example, the magnetically coupled SFQ transfer circuit [11] in Fig. 3 is modeled with InductEx as shown in Fig. 4 and Fig. 5.

ADP layer defi ni-tion fi le (excerpt)

...* VIA1$LayerNumber = 18Name = VIA1Thickness = 0.2Order = 1Mask = -1Filmtype = IPlanarModel = 1$End...* GND1$LayerNumber = 19Name = GND1Thickness = 0.2Lambda = 0.08Order = 2Mask = -1Filmtype = SHFilaments = 1Colour = 150$End...* BC$LayerNumber = 7Name = BCThickness = 0.4Order = 20Mask = -1Filmtype = IPlanarModel = 0LayerADD = 10$End...

Metal layer above is planarized

I = Isolation layer

S = Superconductive layer

Ground plane layers have negative mask - will be automati-cally delimited

The metal layer above BC is not planarized

Filmtype mtype I1P

ypPl

ADD

r M

t