mtk gsm clam shell reference design circuit...

Media Tek Inc

MTK GSM clam shell reference design

circuit analysis

V0.1

MTK GSM Clam Shell Reference Design Circuit Analysis

PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE 1 MTK CONFIDENTIA, NO DISCLOSURE

Media Tek Inc

MTK GSM clam shell reference

design circuit analysis

V0.3

Revision History

Revision Date Author Comments 0.1 2003/10/15 Kevin Shih/Ethan

Lee Clam Shell GSM Circuit Analysis

0.2 2003/11/14 Kevin Shih/Ethan Lee

Add ADC description

0.3 2003/11/20 Johnny Yang Refinement

PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE 2 MTK CONFIDENTIAL, NO DISCLOSURE

Media Tek Inc



V0.3

Table of contents

MTK GSM Clam Shell................................................................................ 1

Reference Design Circuit Analysis ............................. 1

Revision History .................................................................................................................................................... 2 Specification .......................................................................................................................................................... 4 Transceiver introduction ...................................................................................................................................... 7 2.1 General Descriptions...................................................................................................................................... 8 3 RF Circuit Description........................................................................................................................................ 9

3.1 The front end .................................................................................................................................................. 9 3.2 Receiver ................................................................................................................................................ 10 3.3 Transmitter ............................................................................................................................................ 10 3.4 RF Frequency Synthesizer .................................................................................................................... 11

3.4.1 Synthesizer System Description...................................................................................................... 11 3.4.2 Synthesizer Frequency Programming for Rx Mode......................................................................... 12 3.4.3 Synthesizer Frequency Programming for Tx Mode ......................................................................... 12

3.5 26MHz and AFC control circuit .............................................................................................................. 14 3.6 TXVCO and PA Circuit .......................................................................................................................... 14 3.7 Regulator ............................................................................................................................................... 15

Pin Assignment and Description ....................................................................................................................... 22 4 Circuit Description..................................................................................................................................... 24

4.1 Base Band overview.............................................................................................................................. 24 4.2 External Memory Interface..................................................................................................................... 24 4.3 User Interface ........................................................................................................................................ 25 4.4 Audio Interface ...................................................................................................................................... 30 4.5 Radio Interface ...................................................................................................................................... 31 4.6 Debug Function ..................................................................................................................................... 32 4.7 Power Management............................................................................................................................... 32 4.8 MT6305 Power Management System overview .................................................................................... 32 4.9 YAMAHA YMU762C Melody ................................................................................................................. 37 4.10 Hall Sensor IC ....................................................................................................................................... 38 4.11 Auxiliary ADC Unit ................................................................................................................................. 38


Media Tek Inc



V0.3

Specification

1.1 General Table 1. General Specification

1.2 EGSM Band RF Specifications

Transmitting Frequency Range: EGSM: 880 - 915 MHz DCS: 1710 - 1785 MHz

Receiving Frequency Range: EGSM: 925 - 960 MHz DCS: 1805 - 1880 MHz

TX - RX Duplex Spacing: EGSM: 45 MHz / DCS: 95MHz Channel Spacing: EGSM: 200 KHz / DCS: 200 KHz Number of Channels: EGSM: 174 (Numbered 975 to 1024, 1 to

124) DCS: 374 (Numbered 512 to 885)

Table 2. EGSM Band RF Specifications Frequency Stability RF Maximum Power Output RF Output Power Levels

Power Control Level 5 Power Control Level 6 Power Control Level 7 Power Control Level 8 Power Control Level 9 Power Control Level 10 Power Control Level 11 Power Control Level 12 Power Control Level 13 Power Control Level 14 Power Control Level 15 Power Control Level 16 Power Control Level 17 Power Control Level 18 Power Control Level 19

TX Frequency Output Low Channel (Ch 975) Mid Channel (Ch 65) High Channel (Ch 124) TX Frequency Calculation (Ftx)

TX UHF VCO Frequency Low Channel (Ch 975) Mid Channel (Ch 65) High Channel (Ch 124) TX UHF VCO Freq. Calculation (Ftuhf)

< +/- 90Hz 33dBm 15, decrementing in 2dB steps 33dBm +/-2dB 31dBm +/-3dB 29dBm +/-3dB 27dBm +/-3dB 25dBm +/-3dB 23dBm +/-3dB 21dBm +/-3dB 19dBm +/-3dB 17dBm +/-3dB 15dBm +/-3dB 13dBm +/-3dB 11dBm +/-5dB 9dBm +/-5dB 7dBm +/-5dB 5dBm +/-5dB 880.2 MHz 903 MHz 914.8 MHz 890 + (ARFCN x 0.2) = Ftx MHz , ARFCN =1 to 124 1936.44MHz 1986.6MHz 2012.56MHz Detail see TX VCO freq setting


Media Tek Inc



V0.3

Phase Error

Peak Phase Error RMS Phase Error

< 20 degrees < 5 degrees

1.3 DCS Band RF Specifications Table 3. DCS Band RF Specifications Frequency Stability RF Maximum Power Output RF Output Power Levels

Power Control Level 0 Power Control Level 1 Power Control Level 2 Power Control Level 3 Power Control Level 4 Power Control Level 5 Power Control Level 6 Power Control Level 7 Power Control Level 8 Power Control Level 9 Power Control Level 10 Power Control Level 11 Power Control Level 12 Power Control Level 13 Power Control Level 14 Power Control Level 15

TX Frequency Output Low Channel (Ch 512) Mid Channel (Ch 699) High Channel (Ch 885) TX Frequency Calculation (Ftx)

TX UHF VCO Frequency Low Channel (Ch 512) Mid Channel (Ch 698) High Channel (Ch 885)

Phase Error

Peak Phase Error RMS Phase Error

< +/- 180Hz 30dBm 16, decrementing in 2dB steps 30dBm +/-2dB 28dBm +/-3dB 26dBm +/-3dB 24dBm +/-3dB 22dBm +/-3dB 20dBm +/-3dB 18dBm +/-3dB 16dBm +/-3dB 14dBm +/-4dB 12dBm +/-4dB 10dBm +/-4dB 8dBm +/-4dB 6dBm +/-4dB 4dBm +/-4dB 2dBm +/-5dB 0dBm +/-5dB 1710.2 MHz 1747.4 MHz 1784.8 MHz 1710.2 + (ARFCN-512 x 0.2) = Ftx MHz 1881.22MHz 1965.825MHz 1963.28MHz < 20 degrees < 5 degrees

4. Receiver (EGSM) Specifications Table 4. Receiver (EGSM) Specifications


Media Tek Inc



V0.3

RX Frequency Input

Low Channel (Ch 975) Mid Channel (Ch 65) High Channel (Ch 124) RX Frequency Calculation (Frx)

RX VCO Frequency Low Channel (Ch 975) Mid Channel (Ch 65) High Channel (Ch 124)

IF Frequency BER (Bit Error Ratio)

925.2 MHz 948 MHz 959.8 MHz 935 + (ARFCN x 0.2) = Frx MHz 1850.2 MHz 1895.8 MHz 1919.4 MHz 100KHz Type II BER <2.4% at -102dBm Type II BER <0.1% at -15dBm

5. Receiver (DCS) Specifications Table 5. Receiver (DCS) Specifications RX Frequency Input

Low Channel (Ch 512) Mid Channel (Ch 698) High Channel (Ch 885) RX Frequency Calculation (Frx)

RX UHF VCO Frequency Low Channel (Ch 512) Mid Channel (Ch 698) High Channel (Ch 885)

IF Frequency BER (Bit Error Ratio)

1805.2 MHz 1842.4 MHz 1879.8 MHz Ftx + 95 Mhz = Frx MHz 1805.1MHz 1842.3MHz 1879.7MHz 100KHz Type II BER <2.4% at -102dBm Type II BER <0.1% at -15dBm


Media Tek Inc



V0.3

Transceiver introduction

Features Receiver

- Very low IF architecture - Triple differential input LNA’s - Quadrature RF mixers - Fully integrated channel filter - Maximum 110 dB gain with more than 78 dB gain control range - Image-reject down conversion to baseband

Transmitter - High precision IQ modulator - Translation loop architecture

Frequency Synthesizer - Single integrated, fully programmable fractional-N synthesizer - Fully integrated wide range RF VCO - Fast settling time suitable for multi-slot GPRS application

Voltage Control Crystal Oscillator (VCXO) - 26 MHz crystal oscillator capable of supporting 13 MHz / 26 MHz output clock

Regulators - Built-in low-noise, low-dropout (LDO) regulators

Low power consumption QFN (Quad Flat Non-lead) Package 56pin SMD 3-wire serial interface MT6119 is fabricated using a 0.35 µm BiCMOS process


Media Tek Inc



V0.3

2.1 General Descriptions

MT6119 is a highly integrated RF transceiver IC for Global Systems for Mobile communication (GSM), Digital Cellular communication Systems (DCS), and Personal Communication Services (PCS) triple band cellular systems. The MT6119 includes three LNA’s, two RF quadrature mixers, a channel filter, a programmable gain amplifier, an IQ demodulator for the receiver, a high precision IQ modulator with offset PLL for the transmitter, a VCXO oscillator, on-chip regulators, and a fully programmable Sigma-Delta fractional-N synthesizer with an on-chip LC VCO. The MT6119 includes control circuits to implement different operating modes. The device is housed in a 56-pin QFN SMD package with a downset paddle for additional grounding.


Media Tek Inc



V0.3

3 RF Circuit Description

3.1 The front end The RF receive signal (EGSM :925Mhz-960Mhz,DCS : 1805Mhz-1880Mhz) is input from the antenna to the front end switch U502.The circuit which consists C511,L502 andL520 is matching circuit for antenna.The front end switch with input signal LB_TX and HB_TX controls to switch ether RX or TX path on. When the LB_TX is high and HB_TX is low,EGSM_TX path is switched on. When the LB_TX is low and HB_TX is high,DCS_TX path is switched on. When both LB_TX and HB_TX are low,the receive siganl switch to EGSM_RX or DCS_RX.The EGSM RX path contains EGSM SAW filter Z501 and matching circuit C522,C525,L507 to filter out unwanted signal from EGSM_RX to MT6119 differential LNA GSM_RF and GSM_RFB. The DCS RX path also contains DCS SAW filter Z502 and matching circuit C526,C528,L508 to filter out unwanted signal from DCS_RX to MT6119 differential LNA DCS_RF and DCS_RFB.

Figure 1 Front end Block Diagram


Media Tek Inc



V0.3

3.2 Receiver

The receiver section of MT6119 U506 includes Tri-band low noise amplifiers (LNAs), RF quadrature mixers, on-chip channel filters, Programmable Gain Amplifiers (PGAs), quadrature second mixers, and a final low-pass filter. The very low-IF MT6119 uses image-rejection mixers and filters to eliminate interference. With accurate RF quadrature signal generation and mixer matching techniques, the image rejection of the MT6119 can reach 35 dB for all bands. The fully integrated channel filters rejects interference, blocking signals, and images without any external components. Compared to a direct conversion receiver (DCR), MT6119’s very low-IF architecture improves the blocking rejection, AM suppression , as well as the adjacent channel interference performance. Moreover, the very low-IF architecture eliminates the need for complicated DC offset calibration that is necessary in a DCR architecture. In addition, the common-mode balance requirement of the SAW filter input is relaxed. The MT6119 provides the analog IQ baseband output without any extra frequency conversion components.

The MT6119 includes two differential LNAs for GSM900 (925 MHz-960 MHz)and DCS1800 (1805 MHz-1880 MHz). The gain of the LNAs can be controlled either high or low for an additional 35 dB dynamic range control. Following the LNAs are the image-rejection quadrature RF mixers that down-convert the RF signal to the IF frequency. No external components are needed at the output of the RF mixers.

The IF signal is then filtered and amplified through an image-rejection filter and a PGA. The multi-stage PGA is implemented between filtering stages to control the gain of the receiver. With - 2 dB gain steps, a 78 dB dynamic range of the PGA ensures a proper signal level for demodulation. The quadrature 2nd mixers are provided on-chip to down convert IF signal to baseband in an analog differential IQ format :I,IB,Q,QB..

3.3 Transmitter The MT6119 transmitter section consists of a feedback buffer amplifier, a down converting mixer, a quadrature modulator. The dividers and filters are used to achieve the desired IF frequency from the down-conversion mixer and quadrature modulator. For a given transmission channel, the transmitter will select one of the two different Tx reference dividing numbers. These built-in components, along with an external voltage controlled oscillator (TxVCO) and a loop filter implement a translation loop modulator.

In transmitter there has two choices of TX reference divider number for the same transmission channel. The choice criterion is to avoid small fractional number in synthesizer for the relative LO frequency, it can avoid the effect of synthesizer spur.


Media Tek Inc



V0.3

Figure 2 Transmitter Block Diagram

3.4 RF Frequency Synthesizer

3.4.1 Synthesizer System Description The MT6119 includes a single RF synthesizer with a RF VCO and loop filter include C548,R514,C549,R515 and C550 to generate Rx and Tx local oscillator frequencies. The PLL locks the RF VCO to a precise reference frequency at 26 MHz. In order to reduce the inherent spurs caused by fractional-N synthesizers, a 3rd-order Sigma-Delta modulator with a dithering function is used to modulate the prescaler divider number N. The prescaler is based on a multi-modulus architecture with programmable divider numbers ranging from 68 to 83.

The RF synthesizer is programmed using a 3-wire serial interface :SDATA,SCLK,LE. A control word programs the required frequency (integer and fractional division numbers), phase detector current, mode of operation, and fast lock current.


Media Tek Inc



V0.3

Figure 3 RFVCO and Loop Filter Diagram

3.4.2 Synthesizer Frequency Programming for Rx Mode The frequency range of the RF synthesizer for Rx mode is

Rx mode GSM900 1850 MHz ~ 1920 MHz

DCS1800 1805 MHz ~ 1880 MHz

PCS1900 1930 MHz ~ 1990 MHz.

And the divider number N can be decided by the following procedure.

1. Calculate LO frequency fVCO from Rx channel frequency fCH fVCO = 2 * fCH – 200k for GSM900 fVCO = fCH – 100k for DCS1800 and PCS1900

3.4.3 Synthesizer Frequency Programming for Tx Mode The frequency range of the RF synthesizer for Tx mode is

Tx mode GSM900 1936 MHz ~ 2059 MHz

DCS1800 1881 MHz ~ 2008 MHz

PCS1900 2035 MHz ~ 2149 MHz


Media Tek Inc



V0.3

And the divider number N can be decided by the following procedure.

1. Set the divider ratio D1 of Tx reference divider = 11

2. Calculate LO frequency fVCO from Tx channel frequency fCH fVCO = 2 * D1 * fCH / (D1-1) for GSM900 fVCO = D1 * fCH / (D1-1) for DCS1800 and PCS1900

1V CC R F

2G N D R F

34

5

G SM R FB

6

78

D CSR F

910

D CSR FB

PC SR FB

12

CREG 2

56 55 CREG1

54 TXBUF

53 GNDTXCP

52 TXCPO

51 VCCTXCP

50 VCCTXPFD

49 VCCIQ 48 I47 IB46 Q45 QB

from /toB ase bandV C C IQ

V C C TX CP

PC SR F

V C CTX PFD

V B A T2

G N D B U F1314

PFD

÷2/1

C P

D elta-Sigm aM odulator

15 16

RFVCON

17RFVCOP

18VCCRFVCO

19

RFTUNE

20GNDRFCP

21RFCPO 22

VCCRFCP

23GNDSYN

24

VCCSYN

25 26ENRFVCO

V C CR FV C O

ToB ase band

V C O TESTO U T

31REFO U T

30V CC V C X O

29X TA L

from B aseB and A FC

44 4327ENREG

28VCXOCAP

42

A U X O U T41

SD A TA40

CLK

39

EN38

G N D M O D

37V CC M O D

3635V CX O FR Q

34V CX O C X R

FromSystemcontroller

V C C V C X O

V C C V C XO

V C C M O D

33

32GN D V C X O

V B A T

G SM

D C S

PC S

+

Σ

+

+

S

_

PG A&

PolyPhaseFilter

PFD& C P

++

TX V C OR egulator

R F M ulti-M odulusD ivider

TXVCO

FromA ntenna

FromA ntenna

FromA ntenna

VCO

Regulator

Polyphase

Shifter

÷2

÷2/1 ÷9/11

D elta-Sigm aM odulatorRegulator

÷260

G SM R F

G N D LN A 1

V C C R F

G N D LN A 2

11

V CC B U F

V C C B U F

GNDVCO

V C C B U F

V B A T

VBAT3

FromSystemcontroller

V C CB U F

G N D D

V C C D

V C C D

GNDIQ

V B A TV C CTX V C O

TR XR egulator

÷2/1

3_wire

control

PLLC alibration

RFBUF

Regulator

T R X / V C OR egulatorBand-G ap

Figure 4 MT6119 Function Block Diagram


Media Tek Inc



V0.3

maximum output current is 20 mA in this third regulator.There is an external capacitor connected to the noise bypass pin to lower the output noise level in each regulator. The VCXO_EN enable regulator 1nad 2 with a logic high.

3.5 26MHz and AFC control circuit VCXOCXR with a logic high connects the reference frequency 26MHz provided by an external 26 MHz Temperature Compensated Crystal Oscillator ( TCXO ) U504. MT6119 can be selected with a reference frequency of either 13 MHz or 26 MHz. The VCXO_EN enable the REF_OUT 26Mhz with a logic high and 13Mhz with a logic low. The AFC controls the TCXO for AFC control loop with RC filter R509,C538.

Figure 5 26 MHz and AFC Bock Diagram

3.6 TXVCO and PA Circuit The transmitter part of MT6119 and voltage controlled oscillator (TxVCO) U510 with a loop filter contains C507, R502, C506, R503 and C505, implement a translation loop modulator. TXCPO control transmitter charge pump output. R504 , R505 ,R506 and C515 are feedback paths to MT6119 TXBUF.The TXVCO


Media Tek Inc



V0.3

U510 output is fed to the power amplifier (PA) RF3140 with attenuator R330( GSM path ),R331( DCS path) for good VSWR. The BANDSW_GSM and BANDSW_DCS control the EGSM band or DCS band with a logic high or low. When BANDSW_GSM is high and BAND_DCS is low,the TXVCO is in GSM band . When BANDSW_GSM is low and BAND_DCS is high, the TXVCO is in DCS band. The BPI7/VCO_EN enable the TXVCO power on with a logic high.

The RF3140 U507 is a high power, high efficiency power module with integrated power control loop. The C509, L501 and C510 are EGSM band output matching circuit. The C502, L500 and C503 are DCS band output matching circuit. The BANDSW_DCS control the EGSM band or DCS band with a logic high or low. A logic low enable the GSM bands, whereas a logic high enables the DCS band. The Vreg is regulated voltage 2.8V input for power control function of PA module. The PA_EN enable the PA module with a logic high. The ramping signal from Vapc through RC filter C558, R510 and R511, connect the VRAMP of power amplifier. Ramping signal from DAC determines the power level and the ramping profile to met GSM specification for burst timing and transient spectrum.

Figure 6 TXVCO and PA Block Diagram

3.7 Regulator The MT6119 uses internal regulators to provide low noise, stable, temperature and process independent supply voltages to critical blocks in the transceiver. There are three regulators in MT6119, which are fed to “TRX and external TxVCO , VCO buffer, VCXO, synthesizer and VCO core circuit , and Sigma-Delta modulator , respectively. The first one which has two 2.8 V outputs is fed to TRX and external TxVCO. The maximum output current is 100 mA and 40 mA, respectively. Regulator 2 which has 2.8 V and 2 V outputs is fed to VCO buffer, VCXO, syntheszier, and VCO core circuit. The maximum output current is 50 mA and 20 mA, respectively. The last one which has only one output is fed to the Sigma-Delta modulator..There is an external capacitor connected to the noise bypass pin to lower the output noise level in each regulator. The VCXO_EN enable regulator 1nad 2 with a logic high.


Media Tek Inc



V0.3

Ch1: 26MHZ Ch2: AFC

Figure 7 Signal of 26Mhz


Media Tek Inc



V0.3

Ch1: PA_EN Ch2: APC CH3: BANDSW_GSM

Figure 8 RF3140 GSM Band Power Level 5


Media Tek Inc



V0.3


Ch1: PA_EN Ch2: APC CH3: BANDSW_GSM

Figure 9 RF3140 GSM Band Power Level 5

Media Tek Inc



V0.3


Ch1: PA_EN Ch2: APC CH3: BANDSW_DCS

Figure 10 RF3140 DCS Band Power Level 0

Media Tek Inc



V0.3


Ch1: PA_EN Ch2: APC CH3: BANDSW_DCS

Figure 11 RF3140 DCS Band Power Level 15

Media Tek Inc



V0.3


Media Tek Inc



V0.3


Pin Assignment and Description

Pin No. Pin Name Description 1 VCCRF TRX RF block supply voltage and Regulator 1 (TRX) voltage output 2 GNDRF TRX RF block ground 3 GSMRF Receiver GSM RF differential positive input 4 GSMRFB Receiver GSM RF differential negative input 5 GNDLNA1 Receiver RF GSM LNA block ground 6 DCSRF Receiver DCS RF differential positive input 7 DCSRFB Receiver DCS RF differential negative input 8 GNDLNA2 Receiver RF DCS / PCS LNA block ground 9 PCSRFB Receiver PCS RF differential negative input

10 PCSRF Receiver PCS RF differential positive input 11 CREG2 Regulator 2 external noise bypass 12 VBAT2 Battery supply for Regulator 2 13 VCCBUF RF VCO buffer supply voltage and Regulator 2 (BUF) voltage output 14 GNDBUF RF VCO buffer ground 15 RFVCON RF VCO test differential negative output 16 RFVCOP RF VCO test differential positive output 17 GNDVCO RF VCO ground 18 RFTUNE RF VCO tune input 19 VCCRFVCO RF VCO supply voltage and Regulator 2 (RF VCO) voltage output 20 GNDRFCP RF charge pump and PFD ground 21 RFCPO RF charge pump output 22 VCCRFCP RF charge pump and PFD supply voltage 23 VCCSYN RF synthesizer supply voltage 24 GNDSYN RF synthesizer ground 25 VBAT 26 ENRFVCO Regulator 2 enable input for RFVCO 27 ENREG Regulator 1 and 2 enable input for TRX / RFVCO buffer / RF synthesizer / VCXO 28 VCXOCAP VCXO coarse tuning capacitor

Media Tek Inc



V0.3


29 XTAL 26 MHz crystal reference input 30 VCCVCXO VCXO supply voltage 31 REFOUT 13 MHz / 26 MHz reference buffer output 32 GNDVCXO VCXO ground 33 VCXOCXR VCXO internal / external output buffer control 34 VCXOFRQ Reference output buffer 13 MHz / 26 MHz selection 35 GNDMOD RF synthesizer Sigma-Delta modulator ground 36 VCCMOD RF synthesizer Sigma-Delta modulator supply voltage and Regulator 3 output 37 EN 3-wire serial bus enable input 38 CLK 3-wire serial bus clock input 39 SDATA 3-wire serial bus data input 40 AUXOUT Auxiliary test output 41 GNDD 3-wire digital circuit ground 42 VCCD Supply voltage for 3-wire digital circuit and supply voltage for Regulator 3 43 QB Q path negative baseband input / output 44 Q Q path positive baseband input / output 45 IB I path negative baseband input / output 46 I I path positive baseband input / output 47 GNDIQ IF circuit ground 48 VCCIQ IF circuit supply voltage 49 VCCTXPFD Transmitter PFD and Receiver IF circuit supply voltage 50 VCCTXCP Transmitter charge pump supply voltage 51 TXCPO Transmitter charge pump output 52 GNDTXCP Transmitter charge pump ground 53 TXBUF Transmitter VCO feedback input 54 CREG1 Regulator 1 external noise bypass 55 VBAT1 Battery supply for Regulator 1 56 VREG1 Regulator 1 (TxVCO) voltage output

Table 1 MT6119 Pin Description

Media Tek Inc



V0.3


4 Circuit Description

4.1 Base Band overview MT6205B is a highly integrated baseband processor optimized specially for multi-media enabled GSM terminal. Combining the 32-bit ARM7TDMITM RISC processor core, proprietary low-power digital signal processor, user interface, radio control, audio codec, baseband codec, and other GSM specific analog and digital hardware, the MT6205B completes the best single-chip solution for GSM phone with multi-media function. MT6305 is a power management IC optimized specially for MT6205B baseband processor. It provides the seven high efficiency LDOs, power on sequence, SIM level shift, charging function and some peripherals to reduce part counts.

4.2 External Memory Interface With the External Memory Interface, the MT6205B can supports varieties of SRAM and Flash in the market and multi-media devices with parallel interface, such as color LCD panel, MIDI synthesizer and Digital Still Camera etc. In this project, we control the AMD combo memory (AM41DL6408G – 3V 64Mb Flash + 8Mb SRAM), Color LCM, and YAMAHA MA3 Melody IC by external memory interface.

RFM odule

M T6205B

Debugger

AudioOutputs

AudioInputs

KeypadInterface

External M emory Interface

Flash SRAMColorLCD

TCVCXOAFC

APC

TX I/Q

RX I/Q

BPI

BSI

AlerterOutput

SIM InterfaceAuxADC

SupplyVoltages GPIO

JTAG

UART

SerialLCDInterface

SYSCLK

1 2 3

4 5 6

7 8 9

* 0 #

M IDIor

Cam era

SIMLCDM odule

Pow erM anagem entCircuitry

Media Tek Inc



V0.3


4.3 User Interface For user interactions, the MT6205B brings together all necessary peripheral blocks for a value-added GSM phone. It comprises the Keypad Scanner, SIM Controller, dual channels UART, Alerter, Real Timer Clock, PWM, Serial LCD Controller and General Purpose Programmable I/Os. Keypad Scanner: The keypad can be divided into two parts: one is the keypad interface including 5 columns and 5 rows; the other is the key detection block which provides key pressed, key released and de-bounce mechanism. This keypad can detect one or two key-pressed simultaneously. Due to the keypad interface, more than two keys pressed simultaneously will get the wrong information. Folder phone key mapping:

Column 0 Column 1 Column 2 Column 3 Column 4

Row 0 SEND UP SIDEKEY DOWN SIDEKEY POWER

Row 1 UP 1 2 3

Row 2 DOWN 4 5 6

Row 3 LEFT 7 8 9 LEFT SOFT KEY

Row 4 RIGHT * 0 # RIGHT SOFT KEY

Media Tek Inc



V0.3


SIM Controller: The MT6205Bcontains a dedicated smart card interface to allow the MCU access to the SIM card. It can operate via 5 terminals, using SIM VCC, SIMSEL, SIMRST, SIMCLK and SIMDATA. The SIMVCC is used to control the external voltage supply to the SIM card and SIMSEL determines the regulated smart card supply voltage. SIMRST is used as the SIM card reset signal. Besides, SIMDATA and SIMCLK are used for data exchange purpose. MT6305 provide the SIM Level shift Between the SIM controller and SIM card.

VSIM

TP303

J301

SIM SOCKET

1 2

3 4

5 6

CLK I/O

RST VPP

VCC GND

C34710u (0805 Y5V 10V)

C317nc

C316nc

C315nc

TP302TP301TP300 TP304

U300

PMIC MT6305

323331

1312

4544

42363534

1

65

2

27

2324

719264730291721283740

4820

34

91011

141516

2518822

43

413938

46

49

PWRKEYPWRBBSRCLKEN

SIMSELSIMVCC

VmSELVaSEL

BATUSELEDENALERTERENVIBRATOREN

CHRIN

CHRDETCHRCNTL

GATEDRV

Va

RSTCAP/RESET

VBATSNSVBAT

AVBATVBATVREF

NC/BPDGNDDGNDAGNDPGNDPGND

VcoreVio

NC/DANODEISENSE/NC

SIMIOSIMRSTSIMCLK

SIOSRSTSCLK

VtcxoVm

VSIMVrtc

BATDET

LEDALERTER

VIBRATOR

DGND

GN

D

SIMDATASIMRSTSIMCLKSIMVCCSIMSEL

Dual channels UART: The MT6205B has two UARTs. Besides a full-functional UART, there is another simplified UART for displaying debugging messages. The UARTs provide full duplex serial communication channels between the MT6205 and external devices. Alerter: The output of Alerter has two sources: one is the enhanced PWM output signal, which is implemented embedded in Alerter module; the other is PDM signal from DSP domain directly. Real Timer Clock: The Real Time Clock (RTC) module provides time and data information. It works on the 32.768KHz oscillator with independent power supply. When the MS is power off, a dedicated regulator (1.5V) is used to supply the RTC block. If the main battery is not present, the backup supply such as a small mercury cell battery or a large

Media Tek Inc



V0.3


capacitor is used. In addition to provide timing data, alarm interrupt is generated and it can be used to power up the base-band core through the BBWAKEUP pin. Also, regulator interrupts corresponding to the seconds; minutes, hours and days can be generated whenever the time counter value reaches a maximum. The year span is supported up to 2127. The maximum day of month values are stored in the RTC block, which depend on the leap year condition. PWM: Two generic pulse-width modulators are implemented to generate pulse sequences with programmable frequency and duty cycle for LCD backlight or charging purpose. The duration of the PWM output signal is Low as long as the internal counter value is greater than or equals to the threshold value. Reference phone use these two PWM pins to control the color backlight and keypad LEDs. It can control the brightness of the color LCM backlight to save current consumption.

PWM

PWM1 KPLED_PWM Keypad PWM control PWM2 GPO1_BLEN_PWM Main LCD backlight PWM control LCD Backlight: SC600B is the charge pump LED driver. The wide input range is matched for Li-ion battery applications. One two tiny ceramic capacitors are required, and the inductorless implementation provides a reduced-EMI solution. Its output current is up to120mA with fixed 4.5V. Reference phone only uses two parallel white LEDs as main display backlight. Set R1=10 ohm to limit the SC600B output current as 50mA(max). MCU can control the SC600B EN pin to enable/disable its output and use PWM to control U6 NMOS to change brightness of the main display backlight. In the sub-LCM backlight, reference design just uses the GPIO to control U6 NMOS to on/off sub-LCM backlight (two parallel blue LEDs) and set R13=22 ohm to limit LED current as 50mA(max).

VBAT

VDD

+4.5V

GPIO6_BLDRVEN

U2

SC600B

1

2

3

4

5 6

7

8

9

10

11

VOUT

CF1+

VIN

CD4

CX8 EN

CF2-

GND

CF1-

CF2+

GN

D1

TP6

TP7

TP8

C81u (0603)

C7 1u (0603)

C91u (0603)

R1 10

R20 0

R22 0

R21 0

R19100K

C101u (0603) BLGND

BLGND

BLGND BLGND

BLGND

Media Tek Inc



V0.3


mtk gsm clam shell reference design circuit...

Documents