Semiconductor Device Modeling and

Characterization – EE5342 Lecture 10– Spring 2011

Professor Ronald L. Carterronc@uta.edu

http://www.uta.edu/ronc/

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First Assignment

• e-mail to listserv@listserv.uta.edu– In the body of the message include

subscribe EE5342

• This will subscribe you to the EE5342 list. Will receive all EE5342 messages

• If you have any questions, send to ronc@uta.edu, with EE5342 in subject line.

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Second Assignment

• Submit a signed copy of the document that is posted at

www.uta.edu/ee/COE%20Ethics%20Statement%20Fall%2007.pdf

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Additional University Closure Means More Schedule

Changes• Plan to meet until noon some days in the next few weeks. This way we will make up for the lost time. The first extended class will be Monday, 2/14.

• The MT changed to Friday 2/18• The P1 test changed to Friday 3/11.• The P2 test is still Wednesday 4/13• The Final is still Wednesday 5/11.

MT and P1 Assignment on Friday, 2/18/11

• Quizzes and tests are open book – must have a legally obtained copy-no

Xerox copies.– OR one handwritten page of notes.– Calculator allowed.

• A cover sheet will be published by Wednesday, 2/16/11.

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Ideal JunctionTheory

Assumptions

• Ex = 0 in the chg neutral reg. (CNR)

• MB statistics are applicable• Neglect gen/rec in depl reg (DR)• Low level injections apply so that

np < ppo for -xpc < x < -xp, and pn < nno for xn < x < xnc

• Steady State conditions

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Forward Bias Energy Bands

1eppkT/EEexpnp ta VV0nnFpFiiequilnon

1/exp 0 ta VV

ppFiFniequilnon ennkTEEnn

Ev

Ec

EFi

xn xnc-xpc -xp 0

q(Vbi-Va)

EFPEFNqVa

x

Imref, EFn

Imref, EFp

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Law of the junction(follow the min. carr.)

t

bia

n

p

p

na

t

bi

no

po

po

no

po

not

no

pot2

i

datbi

V

V-Vexp

n

n

pp

,0V when and

,V

V-exp

n

n

pp

get to Invert

.nn

lnVp

plnV

n

NNlnVV

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Law of the junction (cont.)

t

a

pt

a

n

t

a

t

a

t

bi

t

bia

VV

2ixpp

VV

2ixnn

VV

no

2iV

V

pono

pon

VV

nopoVV-V

pn

ennp also ,ennp

Junction the of Law the

enn

epn

np have We

enn nda epp for So

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Law of the junction (cont.)

dnonapop

ppnn

ppopppop

nnonnnon

a

Nnn and Npp

injection level- low Assume

.pn and pn Assume

.ppp ,nnn and

,nnn ,ppp So

. 0V for nnot' eq.-non to Switched

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pt

apop

nt

anon

V

V-

pononoV

V-V

pon

t

biaponno

xx at ,1VV

expnn sim.

xx at ,1VV

exppp so

,epp ,pepp

giving V

V-Vexpppp

t

bi

t

bia

InjectionConditions

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Ideal JunctionTheory (cont.)

Apply the Continuity Eqn in CNR

ncnn

ppcp

xxx ,Jq1

dtdn

tn

0

and

xxx- ,Jq1

dtdp

tp

0

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Ideal JunctionTheory (cont.)

ppc

nn

p2p

2

ncnpp

n2n

2

ppx

nnxx

xxx- for ,0D

n

dx

nd

and ,xxx for ,0D

p

dx

pd

giving dxdp

qDJ and

dxdn

qDJ CNR, the in 0E Since

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Ideal JunctionTheory (cont.)

)contacts( ,0xnxp and

,1en

xn

pxp

B.C. with

.xxx- ,DeCexn

xxx ,BeAexp

So .D L and D L Define

pcpncn

VV

po

pp

no

nn

ppcL

xL

x

p

ncnL

xL

x

n

pp2pnn

2n

ta

nn

pp

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Excess minoritycarrier distr fctn

1eLWsinh

Lxxsinhnxn

,xxW ,xxx- for and

1eLWsinh

Lxxsinhpxp

,xxW ,xxx For

ta

ta

VV

np

npcpop

ppcpppc

VV

pn

pncnon

nncnncn

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Carrier Injection

-xp

xn-xpc 0

ln(carrier conc)ln Naln Nd

ln ni

ln ni2/Nd

ln ni2/Na

xnc

x

~Va/Vt~Va/Vt

1enxn t

aV

V

popp

1epxp t

aV

V

nonn

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Minority carriercurrents

1eLWsinh

Lxxcosh

LNDqn

xxx- for ,qDxJ

1eLWsinh

Lxxcosh

LN

Dqn

xxx for ,qDxJ

ta

p

ta

n

VV

np

npc

na

n2i

ppcdx

ndnn

VV

pn

pnc

pd

p2i

ncndxpd

pp

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Evaluating thediode current

p/nn/pp/nd/a

p/n2isp/sn

spsns

VV

spnnp

LWcothLN

DqnJ

sdefinition with JJJ where

1eJxJxJJ

then DR, in gen/rec no gminAssu

ta

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Special cases forthe diode current

nd

p2isp

pa

n2isn

nppn

pd

p2isp

na

n2isn

nppn

WN

DqnJ and ,

WND

qnJ

LW or ,LW :diode Short

LN

DqnJ and ,

LND

qnJ

LW or ,LW :diode Long

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Ideal diodeequation• Assumptions:

– low-level injection– Maxwell Boltzman statistics– Depletion approximation– Neglect gen/rec effects in DR– Steady-state solution only

• Current dens, Jx = Js expd(Va/Vt)

– where expd(x) = [exp(x) -1]

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Ideal diodeequation (cont.)• Js = Js,p + Js,n = hole curr + ele curr

Js,p = qni2Dp coth(Wn/Lp)/(NdLp) =

qni2Dp/(NdWn), Wn << Lp, “short” =

qni2Dp/(NdLp), Wn >> Lp, “long”

Js,n = qni2Dn coth(Wp/Ln)/(NaLn) =

qni2Dn/(NaWp), Wp << Ln, “short” =

qni2Dn/(NaLn), Wp >> Ln, “long”

Js,n << Js,p when Na >> Nd

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Diffnt’l, one-sided diode conductance

Va

IDStatic (steady-state) diode I-V characteristic

VQ

IQ QVa

DD dV

dIg

t

asD V

VdexpII

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Diffnt’l, one-sided diode cond. (cont.)

DQ

t

dQd

QDDQt

DQQd

tat

tQs

Va

DQd

tastasD

IV

g1

Vr ,resistance diode The

. VII where ,V

IVg then

, VV If . V

VVexpI

dV

dIVg

VVdexpIVVdexpAJJAI

Q

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Charge distr in a (1-sided) short diode

• Assume Nd << Na

• The sinh (see L12) excess minority carrier distribution becomes linear for Wn << Lp

pn(xn)=pn0expd(Va/Vt)

• Total chg = Q’p = Q’p = qpn(xn)Wn/2x

n

x

xnc

pn(xn

)

Wn = xnc-

xn

Q’p

pn

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Charge distr in a 1-sided short diode

• Assume Quasi-static charge distributions

• Q’p = Q’p =

qpn(xn)Wn/2

• dpn(xn) = (W/2)*

{pn(xn,Va+V) -

pn(xn,Va)}x

n

xxnc

pn(xn,Va)

Q’p

pn pn(xn,Va+V)

Q’p

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Cap. of a (1-sided) short diode (cont.)

p

x

x p

ntransitQQ

transitt

DQ

pt

DQQ

taaa

a

Ddx

Jp

qVV

V

I

DV

IV

VVddVdV

dVA

nc

n2W

Cr So,

. 2W

C ,V V When

exp2

WqApd2

)W(xpqAd

dQC Define area. diode A ,Q'Q

2n

dd

2n

dta

nn0nnn

pdpp

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General time-constant

np

a

nnnn

a

pppp

pnVa

pn

Va

DQd

CCC ecapacitanc diode total

the and ,dVdQ

Cg and ,dV

dQCg

that so time sticcharacteri a always is There

ggdV

JJdA

dVdI

Vg

econductanc the short, or long diodes, all For

QQ

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General time-constant (cont.)

times.-life carr. min. respective the

, and side, diode long

the For times. transit charge physical

the ,D2

W and ,

D2W

side, diode short the For

n0np0p

n

2p

transn,np

2n

transp,p

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General time-constant (cont.)

Fdd

transitminF

gC

and 111

by given average

the is time transition effective The

sided-one usually are diodes Practical

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References *Fundamentals of Semiconductor Theory and Device

Physics, by Shyh Wang, Prentice Hall, 1989. **Semiconductor Physics & Devices, by Donald A.

Neamen, 2nd ed., Irwin, Chicago. M&K = Device Electronics for Integrated Circuits, 3rd

ed., by Richard S. Muller, Theodore I. Kamins, and Mansun Chan, John Wiley and Sons, New York, 2003.

• 1Device Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, 1986.

• 2Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, 1981.

• 3 Physics of Semiconductor Devices, Shur, Prentice-Hall, 1990.