1

High Step-up DC/DC Topology and MPPTAlgorithm for use with a Thermoelectric Generator

Ian Laird, Student Member, IEEE, and Dylan D.C. Lu, Senior Member, IEEE,

Abstract—A thermoelectric generator (TEG) is a low voltage,high current DC power source with a linear V-I characteristicand therefore it is desirable to create a power converter with atopology and control method suited to these attributes. Due tothe TEG’s low voltage, a topology that produces a high step-upgain for a moderate duty cycle is required to reduce voltage andcurrent stresses within the converter. The linear V-I characteristicproduces a P-I characteristic with a flatter peak relative to othersources. This can result in large operating point variations whileperforming maximum power point tracking (MPPT) thus analgorithm with low steady state error is desired. This paperpresents a novel high step-up DC/DC converter topology operat-ing with a fractional short-circuit MPPT algorithm for use with a4.2V, 3.4A (for matched load at ∆T = 270C) TEG module anda converter output of 180V. Compared to existing high step-upDC/DC converters, the proposed converter achieves higher gainwith similar component count. Experimental results are reportedto confirm the converter analysis and better performance of theshort-circuit MPPT algorithm over the Perturb and Observe(P&O) algorithm.

Index Terms—Thermoelectric energy conversion, DC-DCpower conversion, Tracking.

I. INTRODUCTION

DEVELOPING sustainable, non-polluting electrical en-ergy is a crucial part of ensuring that the increasing

global energy demand is met without affecting the environmentin a detrimental way. In order to achieve this, many differentenergy sources and conversion devices are being used inapplications such as centralised generation, small distributednetworks and system energy recovery. One conversion devicethat is showing potential in waste heat recovery applicationsis the thermoelectric generator (TEG).

A TEG is a solid state device that converts a temperaturegradient directly into electricity. It consists of a large numberof thermocouples that are connected electrically in seriesand thermally in parallel. The thermocouples are junctionsof heavily doped semiconductors. During operation, heat isapplied to one junction while it is removed from the other.This causes electrons in the n-type leg and holes in the p-typeleg to drift away from the hot junction towards the cold one.

I. Laird and D. Lu are with the School of Electrical and InformationEngineering, University of Sydney, NSW, 2006 Australia

This project was sponsored by an Australian Postgraduate Award (APA)and the Norman I. Price scholarship

Corresponding author contact: ian.laird@sydney.edu.auCopyright c©2013 IEEE. Published in the IEEE Transactions on Power

Electronics, Vol. 28, No. 7, pp. 3147-3157, July 2013. Personal use of thismaterial is permitted. However, permission to reprint/republish this materialfor advertising or promotional purposes or for creating new collective worksfor resale or redistribution to servers or lists, or to reuse any copyrightedcomponent of this work in other works, must be obtained from the IEEE.

The resulting charge separation produces a voltage across thethermocouple. This is known as the Seebeck voltage and itsmagnitude is proportional to the temperature difference of thehot and cold junctions [1]. If a load is connected across thethermocouple, a DC current flows.

Over the years TEGs have been developed that rangefrom experimental large scale 5 kW units [2] right downto micro-watt systems [3], [4]. At present, commercially andreadily available TEGs, from companies such as Kryotherm,Thermonamic and Hi-Z technology, have power levels rangingfrom 0.5 to 20 W [5], [6]. The V-I characteristic of thesemodules are linear with short-circuit current values that tendto be of similar or greater magnitude than the open-circuitvoltage (e.g. for the HZ-20 module shown in [7], VOC ≈ 5Vand ISC ≈ 16A). Thus these modules are generally consideredto be low voltage, high current devices.

Applications for these commercial modules have been lim-ited to niche products, however there has been research intoutilising TEGs in small scale solar energy systems [8]–[10].Ultimately the goal of these projects is to make thermoelectricsa viable part of a DC micro-grid based system much likephotovoltaics are now. DC micro-grids tend to operate at 120to 400 V [11], [12] therefore a converter with a high step-upgain is required in order for a TEG module to interfaced tosuch a system.

Step-up converters are theoretically able to produce in-finitely high conversion ratios, however in reality the maxi-mum gain is limited by various circuit imperfections such asparasitic components and switch commutation times. Parasiticcomponents degrade not only the gain but also the efficiencyof the converter. They cause the maximum gain to occur atduty ratios of typically 80 to 90% and a significant drop offin efficiency as the duty ratio moves towards and beyond thispoint. Switch commutation times place limits on the maximumswitching frequency and duty cycle ratio (and therefore thevoltage gain) of the converter [13]. Whilst switching frequencycan only be improved by using faster switching components,by implementing a different topology the required gain canbe achieved with a much smaller duty cycle ratio. As well asthis, there are added benefits to using lower duty cycles. Forexample, operating with an extreme duty cycle will mean theinductor current will fall rapidly during the diode’s conductionperiod and hence produce a large electromagnetic interference(EMI) emission. Also the short conduction time will meanlarger peak currents for the output diodes in order to producethe same average current. This places a larger stress on thediode similar to that experienced by the switching transistorin a high step-down converter [14]. There is also the chance

2

that the diode might malfunction as there might not be enoughtime to fully turn both on and off during its short conductionperiod [15].

Previous attempts at designing DC/DC converter topologiesspecifically for TEGs have focused on driver and startercircuits that ensure that the converter can operate at very lowinput voltage. [16] proposed a starter circuit that utilised atriple winding transformer and a nominally-on JFET allowingoperation for input voltages as low as 0.3 V. However theconverter overall only produced an output of 5 V. Other startercircuits that used a mechanical (reed) switch or a tunnel diodein place of the JFET were analysed in [17]. In [18] a converterbased on a charge pump with a variable number of stageswas used with a TEG operating on the micro-power scale andproduced an output of ≈1.5 V. A converter that can be usedfor either a photovoltaic (PV) cell or a TEG is presented in[19] which can operate on an input voltage of 40 mV. As aresult of this work there are now readily available low inputvoltage converters such as the LM2623. While such convertersserve their purpose, they are not suited to interfacing a TEGto a high voltage DC bus as is the intention of this paper.

There have been various techniques used to create high step-up converters that maintain high efficiency. Converters utilisingrepeated component networks, such as multiplier capacitors orvoltage doublers, are described in [20]–[23]. The advantage ofthis method is that it usually avoids magnetic components andtheir associated problems such as the high voltage stressesinduced by the leakage inductance of a transformer. Thedrawback however is that as larger gains are needed morecomponents are required. Typically a gain of N requires Ncapacitors. Another method, shown in [15], [24], involvesusing switching blocks either in addition to or replacinginductors and capacitors in a range of classical converters(such as the buck or boost). The advantage of these blocksare that they store less energy in their electric/magnetic fieldsand thus are smaller, lighter and cheaper than an equivalenttransformer. However they do not produce gains as high astransformer based converters. Transformer or coupled inductorconverters are well established with well known topologiessuch as the forward, flyback and other topologies describedin [25]–[29]. The voltage gain of standard coupled inductorconverters has been further increased by connecting capacitorsto the coupled inductor windings in configurations known asvoltage multipliers or voltage lifters as shown in [30]–[36].Despite these converters experiencing problems due to theleakage of the coupled-inductor, the addition of a voltagemultiplier greatly increases the gain whilst only adding a smallnumber of extra components. This makes it a suitable choicefor the low to medium power levels of the TEG applicationsand as a result, a novel topology based on the coupled inductor,voltage multiplier converter configuration will be presented inthis paper.

Aside from the converter topology, TEGs require a suitablecontrol algorithm to achieve maximum power point tracking(MPPT) of the device. Similar to photovoltaics (PV), thereis an operating point that causes a TEG to deliver maximumpower. A comprehensive survey of MPPT methods has beenoutlined in [37] but this was focused on PV. Previous attempts

N1 C1Lm

+

v1(t)

−

− nv1(t) +

Vi

+

VC1

−

C2

− VC2 + N2

(a) On state

N1 N2C1

RLCo

+

Vo

−

Lm

+ v1(t) − + nv1(t) −

Vi

− VC1 + C2

− VC2 +

(b) Off state

Fig. 1. Converter 8 switching states

N1 N2C1

RLCo

+

Vo

−

Lm

+ v1(t) − + nv1(t) −

Vi

− VC1 +

S

D3

D1

C2D2

−

VC2

+

Fig. 2. Proposed high step-up gain converter

at implementing an MPPT with a TEG device have involvedusing either the perturb and observe [38], [39], incrementalconductance [40] or a modified version of open-circuit voltage[41], [42]. This paper implements the fractional short circuitcurrent method MPPT algorithm in the proposed converter dueto its low steady state error.

The paper is organised as follows. The proposed converteris introduced and its operation explained in Section II. Theconverter is analysed in terms of voltage gain and efficiency inSection III. MPPT algorithm suitability is discussed in SectionIV. The converter is built and tested in Section V. Finallyconclusions are drawn in Section VI.

II. PROPOSED CONVERTER AND PRINCIPLES OFOPERATION

As mentioned in section I, the proposed topology is basedon the coupled-inductor, voltage multiplier principle. The mostbasic implementation of this principle, of which an interleavedversion can be seen in [32], involves a capacitor being chargedby a winding of the coupled-inductor when the switch is on,and then discharging in series with both windings into theload such that the voltages of all three components combinetogether to boost the output voltage. This principle can beextended such to utilise multiple capacitors such that they

3

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(a) Stage 1 (T0 - T1)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(b) Stage 2 (T1 - T2)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(c) Stage 3 (T2 - T3)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(d) Stage 4 (T3 - T4)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(e) Stage 5 (T4 - T5)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(f) Stage 6 (T5 - T6)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(g) Stage 7 (T6 - T7)

N1 N2− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

Lk

CDS

VS

CD1

(h) Stage 8 (T7 - T8)

Fig. 3. Proposed converter stages of operation for mode 2

charge independently during the switch on stage and dischargein series during the off stage. However the components canalso be arranged so that during the on stage one capacitor,along with the windings, discharges into the other capacitorand thus boost it voltage to an even higher voltage. During theoff stage, the high voltage capacitor can discharge, in serieswith the windings, into the load whilst the other capacitor isrecharged.

In order to realise this concept, equivalent circuits represent-ing both the on and off states of the converter were developedfor various arrangements of the components in order to find acombination that resulted in a desirable gain function. The onand off stage equivalent circuits that resulted from the designprocess, and that make up the main on and off stages of thispaper’s proposed converter, are shown in Fig. 1. During theon state C2 is placed in series with both the primary andsecondary windings so that discharges into and hence booststhe voltage of C1. During the off stage, C1 discharges in serieswith both windings into the load whilst C2 is recharged by the

higher voltage secondary winding. To complete the design,switches and diodes were added so that these switching statescould be realised. The resulting converter is shown in Fig. 2.

The circuit itself operates in one of 4 different modesdepending on the circuit parameters. The main differenceamong the 4 different modes is the sequence and durationof conduction of the three diodes D1, D2 and D3. Mode 1is complete continuous conduction mode (CCM) where theswitch and diode D1 conduct for a portion of the switchingcycle followed by diodes D2 and D3 conducting for theremainder. Mode 2 is the same as Mode 1 except that thecurrent in D1 reduces to zero before the active switch is turnedoff. Mode 3 begins as Mode 1 does however D2 and D3

both simultaneously reduce to zero before the switch turns onthus putting the converter in discontinuous conduction mode(DCM). In Mode 4, all three diodes D1, D2 and D3 reduceto zero within their operation intervals respectively. ThereforeMode 1 has 2 main switching stages, Modes 2 and 3 have 3stages, and Mode 4 has 4 stages. This section will focus on

4

the main and transitional operating stages of Mode 2.In order to show the switching stages of the proposed

converter it is modelled as follows. The coupled inductor ismodelled as an ideal transformer with parallel magnetising andsecondary series leakage inductances. The switch and diodesare considered to be ideal, however the switch and diode D1

both have parasitic capacitances placed in parallel with them.Capacitors Ci, Co, C1 and C2 are all assumed to be largeenough to maintain constant voltages over the entire switchingperiod. Fig. 3 shows the switching stage diagrams while Fig. 4shows the key waveforms over a switching period. Below isa description of the switching stages. Prior to Stage 1 diodesD2 and D3 are conducting.

Stage 1 [T0,T1] (Fig. 3a): Switch Q turns on at T0 andits parasitic capacitance CDS begins to discharge via theinternal resistance of the switch. As a result diode D3 will stopconducting and its blocking voltage will start to rise. Parasiticcapacitance CD1 will also discharge as a result of the voltageon CDS dropping. Leakage inductance Lk discharges throughD2.

Stage 2 [T1,T2] (Fig. 3b): At time T1 CDS is fully dis-charged. As a result CD1 stops discharging and holds aconstant voltage for the duration of the stage. Lk continuesto discharge through D2.

Stage 3 [T2,T3] (Fig. 3c): At time T2 Lk has fully dis-charged and D2 turns off. Current now begins to flow throughLk in the reverse direction causing it to charge but with reversepolarity. This current also causes CD1 to discharge.

Stage 4 [T3,T4] (Fig. 3d): At time T3 CD1 has fullydischarged and D1 is turned on. Energy is transferred fromthe Vi, Lk and C2 into Lm and C1, thus causing the currentin Lm to increase and that in Lk to decrease. The overallcurrent slope through L1 can either positive or negative as itis the sum of the magnetising and reflected leakage currents.

Stage 5 [T4,T5] (Fig. 3e): At time T4 the current in Lk hasreturned to zero and D1 naturally turns off. Lm continues tocharge from Vi and thus its current increases.

Stage 6 [T5,T6] (Fig. 3f): Switch Q turns off at T5. CDS

begins to charge. This in turn causes CD1 to also charge and asa result the blocking voltages of D2 and D3 begin to reduce.The current draw of CD1 also causes Lk to charge.

Stage 7 [T6,T7] (Fig. 3g): At time T6 the voltage acrossD2 is reduced to zero and it begins to conduct. The blockingacross D3 continues to decrease.

Stage 8 [T7,T8] (Fig. 3h): At time T7 the voltage across D3

is reduced to zero and it begins to conduct. Lm, Lk and C1

discharge their energy to C2 and the load.

III. CONVERTER ANALYSIS

A. Converter gainIn order to determine the converter gain only Stages 4, 5

and 8, where there is significant energy transfer between thesource, energy storage elements and the load, as shown inFig. 3d, 3e and 3h, are required. Since Lk, CDS and CD1

contribute significantly to the switch transitions but not theenergy transfer they are ignored. The analysis model is shownin Fig. 5. Note that with the absence of Lk, the voltage acrossLm for Stage 4 can also be written in two different ways:

t

vGS(t)

t

t

t

t

t

t

iDS(t)

v1(t)

v2(t)

iD3(t)

vD3(t)

iD2(t)

vD2(t)

vD1(t)

iD1(t)

vDS(t)

im(t)i1(t)

T0 T8T7T6T5T4T3T2T1

i2(t)

Fig. 4. Switching waveforms of proposed converter for mode 2

N1 N2

− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS

Lm

+ v1(t) − + nv1(t) −

Vs

− vD1(t) +

−

vD2(t)

+

− vD3(t) +

+

vDS(t)

−

Fig. 5. Circuit model for gain analysis

5

v1(t) = Vi or v1(t) =VC1 − VC2 − Vi

n

∴ VC1 = (n+ 1)Vi + VC2 (1)

A similar relationship is also found in Stage 8 as shown:

v1(t) = Vi − Vo + VC1 + VC2 or v1(t) = −VC2

n

∴ n (Vi − Vo + VC1) + (n+ 1)VC2 = 0 (2)

Noting that the voltage across Lm during Stage 5 is Vi, thevolt-second balance for these three stages is:

ViDT + (Vi − Vo + VC1 + VC2) (1−D)T = 0 (3)

Solving (1), (2) and (3) gives the following relations:

Vo

Vi=

(n− 1)D + n+ 21−D

(4)

VC1

Vi=n+ 1−D

1−D(5)

VC2

Vi=

nD

1−D(6)

From this we can determine the blocking voltages experi-enced by the switching devices:

VDS = Vo − VC1 − VC2 =1

1−DVi (7)

VD1 = Vo − Vi − VC2 =n+ 11−D

Vi (8)

VD2 = VC1 − Vi =n

1−DVi (9)

VD3 = Vo − Vi − VC2 =n+ 11−D

Vi (10)

Table I and Fig. 6 show the gain of the proposed convertercompared to a range of other converters that use the same orsimilar component sets. All converters use a single coupledinductor and a single active switch. The input capacitor isignored in the total capacitor count as it is common to all theconverters. Also only CCM operation is considered to allowfor easy comparison between the converters. As can be seenthe proposed converter compares favourably with the otherconverters. Compared to [34] its gain is smaller for duty cyclevalues of less than approximately 0.5, however it is greater forthose above and it achieved with fewer components.

TABLE ITOPOLOGY COMPARISON

Parameter [30] [31] [34] Proposed

Capacitors 3 3 4 3Diodes 3 3 4 3

Gain n+21−D

nD+21−D

n(2−D)+21−D

(n−1)D+n+21−D

0

5

10

15

20

25

30

35

40

45

50

0 0.2 0.4 0.6 0.8 1

Vo

Vi

D

[30]

[31]

[34]

Proposed

Fig. 6. Gain comparison of various topologies (n = 5)

B. Losses and efficiency analysis

In this section the estimated conduction and switchinglosses of the converter are modelled and analysed in terms oftheir effect on the converter efficiency. To model the averagetransformer and semiconductor conduction losses the circuitmodel shown in Fig. 7 has been used. To simplify the analysisonly Mode 1 operation of the converter and thus only themain on and off stages (Fig. 3d and 3h) are considered. Allvoltages and currents are assumed to be DC for the durationof a switching stage however they may have different valuesfor different stages. The magnetising inductance and capacitorsare assumed to have constant current and voltages respectivelyover the entire switching period. Performing an amp-secondon Co gives:

−IoD +(I1off

− Io)

(1−D) = 0

I1off=

Io1−D

(11)

N1 N2

− VC1 +

−

VC2

+

RL

Q

D3

D1

D2

+

Vi

−

Ii Io

+

Vo

−

RS+ V1 − + nV1 −

I2

I1

ILm

ICi

IDS

IC1

ID1

ID3

ID2

IC2

ICo

R1

VS

RDSR2

RD2

RD1

RD3

VD1

VD3

VD2

nI2

Fig. 7. Circuit model for loss and efficiency analysis

6

Vo =DRL (((n− 1)D + n+ 2)Vi − (1−D) (VD1 + VD2 + VD3))

(n(1+D)+1)2

1−D RDS +(

(n(1+D)+D)2

1−D +D)R1 + (1 + 3D)R2 + (1−D) (RD1 +DRL) +D (RD2 +RD3)

(21)

Performing an amp-second balance on C1 and using (11)gives:

−I2onD − I1off(1−D) = 0

I2on = −IoD

(12)

Using (11) and (12) on the amp-balance on C2 produces:

I2onD +

(I2off

− I1off

)(1−D) = 0

I2off=

2Io1−D

(13)

And the amp-second balance on Ci using (11) and (12) is:

(Ii − I1on + I2on)D +(Ii − I1off

)(1−D) = 0

I1on =Ii − 2IoD

(14)

Since the average current through Lm is constant over theperiod therefore:

I1on+ nI2on

= I1off+ nI2off

Ii − 2IoD

+ n

(−IoD

)=

Io1−D

+ n2Io

1−D

Ii =(n− 1)D + n+ 2

1−DIo (15)

As before, while Q and D1 are on V1 can be defined in thefollowing ways:

V1on = Vi − (R1 +RDS) I1on +RDSI2on (16)

V1on=VC1 − VC2 + VD1 −R1I1on

− (R2 +RD1) I2on

n+ 1(17)

Similarly when D2 and D3 are off V1 can be defined in thefollowing ways:

V1off=RD2I1off

− (R2 +RD2) I2off− VC2 − VD2

n(18)

V1off=Vi − Vo + VC1 − VD3

n+ 1−

(R1 +RD3) I1off+R2I2off

n+ 1(19)

Using (16) and (17) the volt-second on Lm is:

VC2 + VD2 −RD2I1off+ (R2 +RD2) I2off

n(1−D)

= (Vi − (R1 +RDS) I1on+RDSI2on

)D (20)

0

20

40

60

80

100

120

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

aaaaa

D

n=5

n=10

n=15

n=20

Vo

Vi

Vi=5V, VD1=VD2=VD3=0.6V, RDS=R1=0.025Ω, R2=0.5Ω, RD1=RD2=RD3=0.1Ω, RL=2.25kΩ

Fig. 8. Effect of turns ratio on the voltage gain when accounting fortransformer and semiconductor conduction losses

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

η

D

n=5

n=10

n=15

n=20

Vi=5V, VD1=VD2=VD3=0.6V, RDS=R1=0.025Ω, R2=0.5Ω, RD1=RD2=RD3=0.1Ω,

RL=2.25kΩ, tc,on=40ns, tc,off =125ns, fs=100kHz

Fig. 9. Effect of turns ratio on converter efficiency

Using Io = Vo

RLand substituting and solving (11) to (20)

produces (21). Using (21) the output power of the convertertaking all the conduction losses into consideration can begiven by Pocond = VoIo. However for calculating the converterefficiency both the conduction and switching losses need tobe considered and thus it can be written as:

η =Pocond − PQ loss

Pi(22)

where PQ loss =16

(VDSoff

IDSon+ VD1off

ID1on

+ VD2offID2on

+VD3offID3on

)fs (tc,on + tc,off )

Where VDxoffand IDxon

are respectively the blockingvoltages and conduction currents that the switch and diodes

7

TABLE IIPROPOSED CONVERTER COMPONENTS AND PARAMETERS

Component/Parameter Value

f 100 kHzQ IPB009N03L

D1, D2, D3 MBR40250n 7.5Lm 25 µHCore 32-580-47Ci 1000 µF

Co, C1, C2 22 µF

are subjected to during the switching period, tc,on and tc,off

are the turn-on and turn-off transition times, and fs is theswitching frequency. Equations (21) and (22) are plotted fordifferent values of the turns ratio n in Fig. 8 and 9 respectively.As can be seen, as the turns ratio increases the voltage gainfunction becomes increasingly linear, resulting in higher gainsat lower duty cycle values and therefore producing a more evenspread of voltage and current stress across the components andallowing for more precise gain control. The overall efficiencyhowever decreases over the entire operation range with thisincrease in turns ratio thus a trade-off must be made betweengain, desired operating point and efficiency.

IV. MPPT ALGORITHM SUITABILITY FOR A TEG

The purpose of maximum power point tracking (MPPT) isto move the electrical operating point of a circuit so that theinput power source operates at a voltage and current that willcause it to transfer maximum power to the load regardless ofwhether the load or the input power source itself is changingdue to external factors. For the case of TEGs, power outputvariations are the result of changes in the load current and/orthe temperature difference applied across the TEG itself.

Research into using MPPT with PV is well establishedwith a wide range of algorithms available to choose from.The three most prevalent methods are the perturb and observe(P&O), incremental conductance (INC) and the fractionalopen/short-circuit voltage/current (Frac. VOC /ISC) more com-monly known as constant voltage/current (CV/CI). Both P&Oand INC are hill-climbing based methods. This means thatthey operate by measuring the power at a particular operatingpoint, step to a new point and measure the power there. If thepower has increased then the algorithm will keep steppingthe operating point in the same direction. However it willstep in the reverse direction if the power has decreased. Thedifference between the P&O and INC algorithms is that theP&O, upon reaching the maximum power point (MPP), willoscillate around it as, in its purest form, the algorithm hasno condition to stop the stepping. The INC algorithm hasa condition that determines if the MPP has been reached.However, in practice this condition is extended to a rangearound the MPP as it is highly unlikely that a step will landdirectly on the MPP. Thus the INC algorithm often stops at apoint near the MPP rather than exactly on it.

The Frac. VOC /ISC method uses the observation thatthe relationship between the MPP voltage/current and the

0

0.125

0.25

0.375

0.5

0.625

0.75

0.875

1

0 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1

V,

P

I

PV V-I

TEG V-I

PV P-I

TEG P-I

IMPP

VMPP ΔVTEG

ΔIPV

ΔVPV

ΔITEG

ΔP Pmax

Fig. 10. Characteristic comparison of a PV and TEG operating pointoscillation

open/short-circuit voltage/current for a PV module is approx-imately given by VMPP = k1VOC and IMPP = k2ISC

respectively. Therefore the MPP can be tracked by simplymeasuring VOC or ISC and calculating the desired operatingpoint. The drawback of this method is that k1 can vary between0.71 and 0.78 and k2 between 0.78 and 0.92 from moduleto module and thus must be determined prior to use in thealgorithm [37]. Also since the relationship is not actuallylinear, choosing a particular k value can result in varyinglevels of steady-state error under changing conditions. Anotherdisadvantage is that in order to operate, the algorithm mustperiodically stop tracking and measure VOC or ISC and, indoing so, briefly reduces the output power to zero. The numberof these power outages can be reduced by increasing the lengthof time between these measurements however this will reducethe responsiveness of the converter to changes in the operatingconditions. As a result the Frac. VOC /ISC method is used lessfrequently with PV modules than the P&O or INC.

However it is different for TEGs. Plotting the V-I char-acteristic of a TEG reveals a linear characteristic that canbe modelled by a voltage source in series with a resistor[7]. For this model the voltage source represents the open-circuit voltage of the TEG, which is directly proportional tothe temperature difference applied to it, while the resistor issimply the electrical resistance of the TEG. The linear V-Icharacteristic results in a parabolic P-I characteristic with itsmaximum located at exactly half of the short circuit current.This is equivalent to half of the open circuit voltage and thusk1 = k2 = 0.5. Unlike PV modules this ratio does not changeregardless of operating conditions. It should be noted that theTEG resistance varies slightly with temperature however thisonly changes the gradient of the V-I characteristic and not itslinear nature.

Therefore the advantage of this method over a hill-climbingalgorithm is the reduced oscillations in the control signal atsteady state. This is of particular importance when consideringthe performance of an MPPT algorithm for use with a TEG.The V-I and P-I characteristics of a PV and TEG that deliverthe same maximum power are shown in Fig. 10. As can be

8

0

10

20

30

40

50

60

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Vo

Vi

D

Experimental

Ideal

Fig. 11. Voltage gain versus duty cycle for proposed converter operatingwith Vi = 4.2V and RL = 2.655kΩ

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

0 2 4 6 8 10 12 14

η

Po (W)

Fig. 12. Efficiency versus output power for proposed converter operatingwith Vi = 4.2V and Vo = 180V

seen, for the same variation in output power, the oscillationsaround the MPP are much larger for a TEG than a PV. If theTEG is connected to the input of a single stage converter withno intermediate energy storage buffer, any variations in theTEG voltage due to MPP oscillations will also be reflectedat the converter’s output. Therefore reducing the MPP oscilla-tions will steady the converter’s output and thus will place asmaller burden on the regulation controls used in subsequentconverter stages. Previous work [43] has experimentally com-pared the perturb and observe, incremental conductance andthe fractional open/short circuit voltage/current methods andconcluded that the fractional short circuit method produced theleast steady state error. Also hill-climbing algorithms requirethe measurement of both the voltage and current whilst Frac.VOC /ISC only needs one, thus reducing sensing circuitry cost.

As mentioned before the drawback of this method is thereduced responsiveness of the converter however this is notsignificant when using an MPPT with a TEG. Changes tothe MPP are the result of the load or the TEG temperaturedifference changing. Changes in the load have no effect on

the value of VOC or ISC and thus can be tracked withoutre-determination of the operation set point. Also, since theconverter only requires the measurement of one parameter, thetracking of load changes can be faster than hill-climbing thatrequires the measurement of two. Changes in temperature willrequire the re-measurement of VOC or ISC . However, due tothe typical thermal capacitance of a TEG, the rate of change ofthese values is relatively slow compared to the tracking speedand thus longer intervals between measurements does notsignificantly degrade the dynamic response of the algorithm.

V. EXPERIMENTAL RESULTS

An experimental version of the proposed converter wasdesigned and built for use with a TEP1-12656-0.6 TEG device.The component values are shown in table II.

The converter was connected to a 4.2V source to simulatethe datasheet specified MPP voltage for a TEP1-12656-0.6running under the maximum temperature differential (∆T =270C). Similarly a fixed output load of 2.655kΩ was con-nected so that a converter output of 180V resulted in an inputcurrent of 3.4A matching the specified MPP current. Fig. 11shows the voltage gain as a function of duty cycle underthese conditions. Replacing the fixed load with a variableone and regulating the output to 180V gave the efficiency ofthe converter as a function of the output power as shown inFig. 12. Overall the European efficiency is calculated to be88.3%. Fig. 13a, 13b, 13c show the switch voltage and L1

and L2 currents respectively for 4.2V input and 180V output.It is worth noting that the switch blocking voltage is only≈15V thus allowing the use of a low voltage MOSFET witha low RDSon . Fig. 13d displays the voltages on C1, C2 andCo which are constant will the exception of a spike on C1

when the leakage inductance rapidly charges during turn on.To test the MPPT steady state performance both a P&O

and Frac. ISC algorithm were implemented on a PIC18F4431.The converter was connected to a TEP1-12656-0.6 operating at∆T = 75C and ∆T = 175C. Various loads over the rangeof 0.5 - 3.5 kΩ were used to vary the converter output voltagethat was required to achieve maximum power transfer. Eachalgorithm was run and the steady state performances are shownin Fig. 14. Fig. 14a and 14b show the converter’s average inputpower delivered by the TEG for each operating temperature.As can be seen, running under the P&O algorithm the powerdelivered has a large variation due to the oscillating natureof the algorithm. The Frac. short-circuit algorithm howeverdelivers a more constant level of power despite some constanterror. The error occurs because the algorithm does not trackthe actual MPP but rather a calculated set-point current whilstthe lower power variation is due to the tracking of only theinput current as opposed to both the input voltage and current.In addition the steadier input power produced by the Frac. ISC

results in a steadier operation voltage for the TEG, as shownin Fig. 14c and 14d, which in turn produces a steadier voltageat the output of the converter as shown in Fig. 14e and 14f.

VI. CONCLUSION

In conclusion this paper has presented a novel high step-up converter that utilises the coupled-inductor and voltage

9

2.5μs/div

VDS = 5V/div

VGS

(a) Switch node voltage

IL1 = 2A/div

2.5μs/div

VGS

(b) L1 current

VGS

2.5μs/div

IL2 = 500mA/div

(c) L2 current

Vo = 50V/div

VGS

2.5μs/div

VC1 = 50V/div

VC2 = 50V/div

(d) C1, C2 and Co voltage

Fig. 13. Waveforms of proposed converter for Vi = 4.2V and Vo = 180V

multiplier principles for use with a TEG or other low voltage,high current power source such as a portable fuel cell unit.It has shown that the proposed converter has a high gaincompared to other circuits of similar component counts andtransformer turns ratio. The converter gain was derived and theeffect of conduction losses on the gain, as well as the overallefficiency, were analysed with particular reference to the con-verter’s turns ratio. The merits of using a fractional open/short-circuit algorithm for controlling a TEG were discussed. Asthe fractional open/short-circuit algorithm experiences reducedoscillations it is therefore more suitable for use with TEGmodules which experience larger steady state oscillations thanPV modules of the same output power rating. The proposedconverter was designed and built for operation with a TEP1-12656-0.6 module and is able to output 180V for an input of4.2V. Both P&O and Frac. ISC algorithms were implementedon the converter and the results obtained showed that theFrac. ISC algorithm produced a more stable output over theoperation range.

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10

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0.84

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era

ge

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W)

Load (Ω)

P&O

Frac Isc

(a) Average Pi, ∆T = 75C

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4

4.1

0 500 1000 1500 2000 2500 3000 3500 4000

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era

ge

Pi (

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Frac Isc

(b) Average Pi, ∆T = 175C

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tan

da

rd d

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tio

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Frac Isc

(c) Standard deviation Vi, ∆T = 75C

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(d) Standard deviation Vi, ∆T = 175C

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0 500 1000 1500 2000 2500 3000 3500 4000

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(e) Vo standard deviation, ∆T = 75C

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tio

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(f) Vo standard deviation, ∆T = 175C

Fig. 14. Characteristics of proposed converter running a TEP1-12656-0.6 for various loads, temperature differences and MPPT algorithms

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Ian Laird graduated from the University of Sydney,Australia in 2008 with a BEng (Hons. I) in Mecha-tronic Engineering. He is currently pursuing his PhDin the fields of thermoelectrics and power electronicsat the University of Sydney. His research interestsinclude thermoelectric modelling, DC-DC convertertopologies and MPPT algorithms.

Dylan Dah-Chuan Lu (S’00 - M’04 - SM’09)received his B.Eng. (Hons.) and Ph.D. degrees inElectronic and Information Engineering from TheHong Kong Polytechnic University, Hong Kong,in 1999 and 2004 respectively. In 2003, he joinedPowereLab Ltd. as a Senior Engineer. His ma-jor responsibilities include project development andmanagement, circuit design, and contribution of re-search in the area of power electronics. In 2006,he joined the School of Electrical and InformationEngineering, The University of Sydney, Australia,

where he is currently a Senior Lecturer. He presently serves as a Memberof the Editorial Board of International Journal of Electronics, a Member ofthe Editorial Board of Smart Grid and Renewable Energy, a Member of theEditorial Board of Energy and Power Engineering and an Associate Editor ofthe Australian Journal of Electrical and Electronic Engineering. His currentresearch interests include power electronics circuits and control for efficientpower conversion, lighting, renewable electrical energy systems, microgridand power quality improvement, and engineering education. He has publishedover 80 technical articles in the areas of power electronics and engineeringeducation. He has two patents on efficient power conversion. Dr. Lu receivedthe Dean’s Research Award in 2011 and is also a member of the Institute ofEngineers Australia.