tesi di laurea - diegm.uniud.itluca/e2/tesi/bertolissi.pdf · contents sommario i abstract iii...

UNIVERSITA DEGLI STUDI DI UDINE

Facolta di IngegneriaCorso di Laurea in Ingegneria Elettronica

Dipartimento di Ingegneria Elettrica, Gestionale e Meccanica

Tesi di Laurea

Modeling and Simulation of Self-Heating Effects

in Deep Sub-Micron Silicon on Insulator (SOI)

Technologies for Analog Circuits

Modellazione e Simulazione degli Effetti di

Riscaldamento Termico in Tecnologie

“Silicon on Insulator” (SOI) Sub-Micrometriche

per Circuiti Analogici

Relatore: Laureando:

Prof. Ing. Luca Selmi Lorenzo Bertolissi

Correlatori:

Dr. Gerhard Knoblinger

Dott. Ing. Pierpaolo Palestri

Dott. Ing. David Esseni

Anno Accademico 2003-04

Sommario

La necessita di ridurre le dimensioni dei transistor ha portato la comunita scien-tifica a proporre nuovi processi costruttivi come la tecnologia “Silicon On Insula-tor” (SOI) e i dispositivi a gate multipli. Rispetto alle tecnologie standard BulkCMOS, queste nuove soluzioni garantiscono diversi miglioramenti, come minorieffetti di canale corto e ridotte capacita parassite. Applicazioni sia analogicheche digitali hanno tratto vantaggio da questi nuovi processi produttivi, ma anchenuovi inconvenienti sono emersi. In particolare, il riscaldamento dei dispositivie dovuto alla bassa conducibilita termica dello strato di ossido di silicio. Comeconseguenza di questo, considerevoli aumenti di temperatura possono avveniredurante il normale funzionamento dei transistor, che a loro volta determinanouna riduzione della mobilita degli elettroni e quindi minori correnti nei dispositi-vi. I circuiti analogici sono influenzati da queste ridotte correnti, di conseguenzaun’appropriata modellazione e comprensione degli effetti del riscaldamento neitransistor sono necessari.

Questa tesi propone un modello termico capace di rappresentare gli incremen-ti di temperatura statici in transistor FinFET, sia a singolo finger che a fingermultipli. La rete termica e stata applicata alla geometria di transistor di rife-rimento e i risultati delle simulazioni validati attraverso misurazioni impulsate.Un’estensiva analisi di sensitivita del modello viene presentata, allo scopo di valu-tare la dipendenza tra aumenti di temperatura e i principali parametri geometricidel FinFET. I risultati delle simulazioni sono stati impiegati per la realizzazionedi un ambiente di sviluppo per circuiti elettronici analogici, con la creazione disottocircuiti completamente scalabili per transistor FinFET capaci di simulare glieffetti del riscaldamento dei dispositivi a differenti livelli di accuratezza. A titolodi esempio, un amplificatore operazionale Miller Op Amp e stato implementatoe l’influenza degli incrementi di temperatura in questo popolare circuito analo-gico quantificata. Il riscaldamento dei dispositivi si e dimostrato un importanteproblema nei circuiti analogici, in particolar modo con la progressiva riduzionedelle dimensioni geometriche dei dispositivi.

i

ii Sommario

Abstract

The need to further scale down the transistor dimensions has led the scientificcommunity to propose new manufacturing processes such as Silicon On Insulator(SOI) and multi-gate technologies. Compared to standard Bulk CMOS, thesenew solutions yield several improvements, such as reduced Short Channel Effects(SCE) and reduced parasitics. Both analog and digital applications take advan-tage from these fabrication processes, which however have their own drawbacks.In particular, self-heating effects are caused by the very low thermal conductiv-ity of the buried oxide layer. As a result, considerable temperature incrementsmay occur during the normal operating conditions of the transistor, which inturn determine a reduced electron mobility and hence lower currents in the de-vices. Analog designs can be influenced by these reduced currents, hence a propermodeling and understanding of self-heating effects is required.

This thesis proposes a thermal model capable to represent the steady-statetemperature increments in both mono-finger and multi-finger FinFETs. Thethermal network has been applied to the geometry of reference transistors andthe simulation results validated by means of pulsed measurements. An exten-sive sensitivity analysis of the model has been carried out, which evaluates thedependence of the temperature increments on the main geometric parameters ofthe FinFET. The simulation results have been employed for the setting up ofan analog circuit simulation environment, with the development of completelyscalable FinFET subcircuits capable to simulate self-heating effects at differentlevels of accuracy. As an example, a Miller Op Amp has been modeled and theinfluence of the temperature increments on this popular analog block evaluated.Self-heating effects proved to be a concern to analog design, especially as thefeature size continues to scale down.

iii

iv Abstract

Contents

Sommario i

Abstract iii

Contents v

List of Figures ix

List of Tables xv

1 New transistor architectures 11.1 The microelectronics age . . . . . . . . . . . . . . . . . . . . . . . 11.2 The MOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 MOS device scaling . . . . . . . . . . . . . . . . . . . . . . . . . . 31.4 SOI technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.5 Multi-gate technologies . . . . . . . . . . . . . . . . . . . . . . . . 81.6 Self-heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.7 Scope of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Heat Transfer Modeling 132.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2 Mechanisms of heat transfer . . . . . . . . . . . . . . . . . . . . . 13

2.2.1 Heat conduction . . . . . . . . . . . . . . . . . . . . . . . 132.2.1.1 Fourier’s law . . . . . . . . . . . . . . . . . . . . 142.2.1.2 Thermal conductivity . . . . . . . . . . . . . . . 152.2.1.3 Nonlinear thermal conductivity . . . . . . . . . . 152.2.1.4 Equations describing heat conduction . . . . . . . 172.2.1.5 Initial and boundary conditions . . . . . . . . . . 19

2.2.2 Heat convection . . . . . . . . . . . . . . . . . . . . . . . . 192.2.3 Heat radiation . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3 Solution of the heat conduction equations . . . . . . . . . . . . . 212.4 Solution in simple cases . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.1 Rectangular material stripe . . . . . . . . . . . . . . . . . 232.4.2 Trapezoidal material stripe . . . . . . . . . . . . . . . . . . 242.4.3 Rectangular material stripe with one nonadiabatic surface 252.4.4 Rectangular material stripe with nonadiabatic lateral surfaces 27

2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

v

vi CONTENTS

3 Thermal model for the FinFET 33

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2 Description of the FinFET geometry . . . . . . . . . . . . . . . . 33

3.3 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.4 Basic blocks of the thermal compact network . . . . . . . . . . . . 39

3.4.1 Metal line . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.4.2 Poly gate termination . . . . . . . . . . . . . . . . . . . . 40

3.4.3 Source-drain contact . . . . . . . . . . . . . . . . . . . . . 43

3.4.4 1 finger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.4.5 2 fingers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.4.6 n fingers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.5 Thermal compact network for the FinFET . . . . . . . . . . . . . 51

3.5.1 1-finger transistor . . . . . . . . . . . . . . . . . . . . . . . 51

3.5.2 2-finger transistor . . . . . . . . . . . . . . . . . . . . . . . 53

3.5.3 n-finger transistor . . . . . . . . . . . . . . . . . . . . . . . 53

3.6 Comparison with existing works . . . . . . . . . . . . . . . . . . . 54

3.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4 Application to template FinFETs 57

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2 Geometry of the reference device . . . . . . . . . . . . . . . . . . 58

4.2.1 1-finger reference transistor . . . . . . . . . . . . . . . . . 58

4.2.2 Multi-finger reference transistor . . . . . . . . . . . . . . . 62

4.3 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.4 Validation of the results . . . . . . . . . . . . . . . . . . . . . . . 70

4.5 Effect of changing geometric parameters . . . . . . . . . . . . . . 72

4.5.1 Gate length . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.5.2 Hotspot and heat source position . . . . . . . . . . . . . . 73

4.5.3 Fin length . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.5.4 Fin width . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.5.5 Fin height . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.5.6 Z-width and finger spacing . . . . . . . . . . . . . . . . . . 76

4.5.7 Buried oxide thickness . . . . . . . . . . . . . . . . . . . . 76

4.5.8 Gate oxide thickness . . . . . . . . . . . . . . . . . . . . . 78

4.5.9 Contact width . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.5.10 Contact height . . . . . . . . . . . . . . . . . . . . . . . . 79

4.5.11 Metal length . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.5.12 Metal thickness . . . . . . . . . . . . . . . . . . . . . . . . 81

4.5.13 Metal width . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.5.14 Properties of the materials . . . . . . . . . . . . . . . . . . 82

4.5.15 Number of fingers . . . . . . . . . . . . . . . . . . . . . . . 83

4.5.16 Other parameters . . . . . . . . . . . . . . . . . . . . . . . 85

4.5.17 General scaling of the geometry . . . . . . . . . . . . . . . 85

4.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

CONTENTS vii

5 Temperature-Aware Analog Circuit Simulation 875.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.2 Brief overview of the Titan simulator . . . . . . . . . . . . . . . . 87

5.2.1 BSIM4 model . . . . . . . . . . . . . . . . . . . . . . . . . 885.2.1.1 Temperature dependence of the mobility . . . . . 885.2.1.2 Temperature dependence of the threshold voltage 895.2.1.3 Other temperature dependent quantities . . . . . 89

5.2.2 BSIMFD2 model . . . . . . . . . . . . . . . . . . . . . . . 905.3 Analog simulation environment for FinFETs in Titan . . . . . . . 91

5.3.1 Circuit modeling strategy . . . . . . . . . . . . . . . . . . 925.3.1.1 Electrical model . . . . . . . . . . . . . . . . . . 925.3.1.2 Subcircuits topology . . . . . . . . . . . . . . . . 93

5.3.1.2.1 FinFET subcircuit without self-heatingeffects. . . . . . . . . . . . . . . . . . . . 93

5.3.1.2.2 FinFET subcircuit with self-heating effects:classical version. . . . . . . . . . . . . . 94

5.3.1.2.3 FinFET subcircuit with self-heating effects:enhanced version. . . . . . . . . . . . . . 95

5.3.2 Implementation of the FinFET subcircuits in Titan . . . . 955.3.2.1 Electrical model extraction . . . . . . . . . . . . 955.3.2.2 Thermal resistances extraction . . . . . . . . . . 96

5.3.2.2.1 FinFET subcircuit without self-heatingeffects. . . . . . . . . . . . . . . . . . . . 96

5.3.2.2.2 FinFET subcircuit with self-heating effects:classical version. . . . . . . . . . . . . . 97

5.3.2.2.3 FinFET subcircuit with self-heating effects:enhanced version. . . . . . . . . . . . . . 101

5.3.3 Simple simulations of the FinFET subcircuits . . . . . . . 1065.4 Analog circuit example: Miller Op Amp . . . . . . . . . . . . . . 1075.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6 Conclusions 115

Bibliography 117

viii CONTENTS

List of Figures

1.1 50 years of transistor technology evolution . . . . . . . . . . . . . 1(a) First experimental semiconductor transistor, 1947, Bell Labs 1(b) State-of-the-art MOSFET, 2002, Intel . . . . . . . . . . . . 1

1.2 Market share of semiconductor devices . . . . . . . . . . . . . . . 21.3 N-channel bulk MOSFET cross view . . . . . . . . . . . . . . . . 21.4 Foreseen ultimate limitations to device scaling [2] . . . . . . . . . 61.5 Typical SOI MOSFET cross view . . . . . . . . . . . . . . . . . . 71.6 Comparison between planar bulk, partially depleted SOI and fully

depleted SOI devices . . . . . . . . . . . . . . . . . . . . . . . . . 71.7 Double-gate MOSFET . . . . . . . . . . . . . . . . . . . . . . . . 8

1.8 FinFET as a vertical double-gate transistor . . . . . . . . . . . . . 91.9 Single-gate, double-gate and triple-gate devices . . . . . . . . . . 91.10 Quadruple-gate and pi-gate devices . . . . . . . . . . . . . . . . . 91.11 Possible application of the temperature-aware design concept . . . 11

2.1 Heat conduction in a solid material . . . . . . . . . . . . . . . . . 14

2.2 Baron Jean Baptiste Joseph Fourier (1768-1830) [19] . . . . . . . 142.3 Temperature dependence of the thermal conductivity of several

solid materials [19] . . . . . . . . . . . . . . . . . . . . . . . . . . 162.4 Temperature dependence of the thermal conductivity of silicon . . 172.5 Generic geometry for the heat conduction problem . . . . . . . . . 182.6 Heat convection mechanism . . . . . . . . . . . . . . . . . . . . . 202.7 Heat radiation mechanism . . . . . . . . . . . . . . . . . . . . . . 202.8 Heat flow through a rectangular material stripe . . . . . . . . . . 232.9 Heat flow through a trapezoidal material stripe . . . . . . . . . . 242.10 Top view of the trapezoidal stripe . . . . . . . . . . . . . . . . . . 242.11 Rectangular material stripe located at the top of a material layer 26

(a) Geometry of the rectangular material stripe located at thetop of a material layer . . . . . . . . . . . . . . . . . . . . . 26

(b) Thermal compact network of the rectangular material stripelocated at the top of a material layer. Heat can flow alongthe stripe and through the bottom surface . . . . . . . . . . 26

2.12 Heat flow through a rectangular material stripe with nonadiabaticsurfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.13 Front view of the rectangular material stripe with nonadiabaticsurfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ix

x LIST OF FIGURES

2.14 Temperature curves along the rectangular material stripe withnonadiabatic lateral surfaces, for several boundary temperaturesat the end of the structure . . . . . . . . . . . . . . . . . . . . . . 30

3.1 General thermal network of a transistor. Two external nodes areavailable: the heat source is employed for the injection of the powerdissipated in the device whilst the hotspot represents the temper-ature of the device . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2 Geometry under analysis: 1-finger FinFET . . . . . . . . . . . . . 35

(a) 3d view of the 1-finger FinFET . . . . . . . . . . . . . . . . 35

(b) Zoomed 3d view of the 1-finger FinFET . . . . . . . . . . . 35

3.3 Geometry under analysis: views of the 1-finger FinFET . . . . . . 36

(a) yz-plane view of the 1-finger FinFET . . . . . . . . . . . . . 36

(b) xy-plane view of the 1-finger FinFET . . . . . . . . . . . . . 36

(c) Top view of the 1-finger FinFET . . . . . . . . . . . . . . . 36

3.4 Simplified top view of the 1-finger FinFET . . . . . . . . . . . . . 37

3.5 Simplified cross view of the 1-finger FinFET . . . . . . . . . . . . 37

3.6 Geometry under analysis: views of the 16-finger FinFET . . . . . 38

(a) Zoomed 3d view of the 16-finger FinFET . . . . . . . . . . . 38

(b) Top view of the 16-finger FinFET . . . . . . . . . . . . . . . 38

3.7 Geometry and thermal model of the metal line . . . . . . . . . . . 41

(a) Metal line geometry . . . . . . . . . . . . . . . . . . . . . . 41

(b) Thermal compact network of the metal line, consisting of aπ2 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

(c) π2 structure of the metal line . . . . . . . . . . . . . . . . . 41

3.8 Geometry and thermal model of the poly gate termination . . . . 42

(a) Poly gate termination geometry . . . . . . . . . . . . . . . . 42

(b) Thermal compact network of the poly gate termination . . . 42

(c) Complete thermal network of the poly gate termination: thepoly line is represented with a π2 structure . . . . . . . . . . 42

3.9 Heat flowing from the poly line end to the contact . . . . . . . . . 43

3.10 Geometry and thermal compact model of the source-drain contact.The structure does not include the pad but only the plug betweenthe active area and the metal line . . . . . . . . . . . . . . . . . . 44

(a) Source-drain contact geometry . . . . . . . . . . . . . . . . . 44

(b) Thermal compact network of the source-drain contact . . . . 44

(c) Thermal resistance of the source-drain contact . . . . . . . . 44

3.11 Geometry of the 1-finger structure . . . . . . . . . . . . . . . . . . 45

(a) 1-finger structure, top view and geometry. The source-drainpads (without the contacts) are parts of the structure . . . . 45

(b) 1-finger structure, cross view of the fin below the poly gate . 45

3.12 Complete thermal compact network of the 1-finger structure (finand source-drain pad). The Pi2 blocks are the π2 structures pre-sented in section 2.4.3. The upper and lower nodes can be used toconnect several fingers in parallel in multi-finger devices. . . . . . 47

LIST OF FIGURES xi

3.13 Thermal compact network of the 1-finger structure (fin and source-drain pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

(a) 1-finger structure, view of the fin below the poly gate. Heatcan flow through the gate oxide and reach the poly gate line 48

(b) 1-finger structure, view of the source active area. Heat canflow through the fin and reach the source active area . . . . 48

(c) 1-finger structure, cross view of the fin below the poly gate.Heat generated in the heat source point can flow towards thedrain, source, gate and bottom silicon . . . . . . . . . . . . 48

3.14 How to obtain the network of the 2-finger structure from the com-bination of two fingers . . . . . . . . . . . . . . . . . . . . . . . . 50

3.15 Complete thermal compact network of 2 fingers. The Pi2 blocksare the π2 structures presented in section 2.4.3 . . . . . . . . . . . 51

3.16 Complete thermal compact network of n fingers. The Pi2 blocksare the π2 structures presented in section 2.4.3 . . . . . . . . . . . 52

3.17 Complete thermal network of the 1-finger transistor . . . . . . . . 53

3.18 Complete thermal network of the 2-finger transistor . . . . . . . . 54

3.19 Complete thermal network of the n-finger transistor. Example: n=16 55

4.1 Complete thermal network of the reference 1-finger FinFET . . . 61

4.2 Thermal resistances (K/W) in the 1-finger FinFET . . . . . . . . 63

4.3 Sorted thermal resistances of the 1-finger FinFET. The high ther-mal resistances between the fin and the bottom silicon inhibit theheat flow towards the bulk. . . . . . . . . . . . . . . . . . . . . . . 64

4.4 Heat flows (W) in the 1-finger FinFET . . . . . . . . . . . . . . . 65

4.5 Sorted heat flows in the 1-finger FinFET. The heat flow from thefin to the bottom silicon is obstructed by the insulator layer. . . . 66

4.6 Node temperature increments (K) in the 1-finger FinFET . . . . . 67

4.7 Temperature profile along the three main heat flow paths in the1-finger FinFET . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.8 Temperature profile along the fin of the 1-finger FinFET . . . . . 68

4.9 Terminal temperatures as a function of the number of fingers. Thedrain, gate and source temperatures are evaluated at the top ofthe contacts. The hotspot temperature is the average value of thehotspot temperatures of the fingers . . . . . . . . . . . . . . . . . 69

4.10 Finger temperatures in a 20-finger device. The contacts are impor-tant heat flow paths and contribute to the lowering of the fingertemperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.11 Pulsed measurements results of a 10-finger device with a gatelength of 250nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.12 Temperature versus power curves extracted from pulsed measure-ments of a 10-finger device with a gate length of 250nm . . . . . . 71

4.13 Gate length dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2 . . . . . . . . . . . . . 72

xii LIST OF FIGURES

4.14 GateCenter-HeatSource distance dependence of the normalized ther-mal resistance. The hotspot is assumed at the center of the gate.The other parameters are reported in table 4.2 . . . . . . . . . . . 73

4.15 GateCenter-HotSpot distance dependence of the normalized ther-mal resistance. The heat source is assumed at three-fourths of thegate length, towards the drain. The other parameters are reportedin table 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.16 Fin length dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2 . . . . . . . . . . . . . 75

4.17 Fin width dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2 . . . . . . . . . . . . . 75

4.18 Fin height dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2 . . . . . . . . . . . . . 76

4.19 Z-width dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2 . . . . . . . . . . . . . 77

4.20 Buried oxide thickness dependence of the normalized thermal re-sistance. The other parameters are reported in table 4.2 . . . . . 77

4.21 Equivalent gate oxide thickness dependence of the normalized ther-mal resistance. The other parameters are reported in table 4.2 . . 78

4.22 Contact width dependence of the normalized thermal resistance.The other parameters are reported in table 4.2 . . . . . . . . . . . 79

4.23 Contact and metal height dependence of the normalized thermalresistance. The other parameters are reported in table 4.2 . . . . 80

4.24 Metal length dependence of the normalized thermal resistance.The other parameters are reported in table 4.2 . . . . . . . . . . . 80

4.25 Metal thickness dependence of the normalized thermal resistance.The other parameters are reported in table 4.2 . . . . . . . . . . . 81

4.26 Metal width dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2 . . . . . . . . . . . . . 82

4.27 Materials dependence of the normalized thermal resistance. Thethermal conductivity of each material has been modified separately.The other parameters are reported in table 4.2 . . . . . . . . . . . 83

4.28 Number of fingers dependence of the normalized thermal resis-tance. The other parameters are reported in table 4.2. In theupper curve, the finger spacing is modified according to the designrules. In the lower curve, only the number of fingers is altered . . 84

5.1 Temperature dependence of the mobility in BSIM4 . . . . . . . . 89

5.2 Temperature dependence of the threshold voltage in BSIM4 . . . 90

5.3 Electro-thermal malfunctioning in Titan AC simulations when aBSIM4 model is employed . . . . . . . . . . . . . . . . . . . . . . 92

5.4 FinFET subcircuit without self-heating effects . . . . . . . . . . . 93

5.5 FinFET subcircuit with self-heating effects: classical version . . . 94

5.6 FinFET subcircuit with self-heating effects: enhanced version . . 95

5.7 Output characteristics of N-channel and P-channel transistors ob-tained with the modified BSIM4 model (nfinger = 1, L = 100nm) . 97

LIST OF FIGURES xiii

5.8 Curve fit of the thermal resistance versus the channel length L, fora fixed value of channel width W = 176nm . . . . . . . . . . . . . 98

5.9 Curve fit of the thermal resistance versus the channel width W,for a fixed value of channel length L = 100nm . . . . . . . . . . . 99

5.10 Transistor subcircuit, classical topology: thermal resistance as afunction of channel width (number of fingers) and channel length,as obtained from the model of equation (5.3.4) . . . . . . . . . . . 100

5.11 Transistor subcircuit, enhanced topology: drain thermal resistanceas a function of channel width (number of fingers) and channellength, as obtained from the model of equation (5.3.8) . . . . . . . 103

5.12 Transistor subcircuit, enhanced topology: gate thermal resistanceas a function of channel width (number of fingers) and channellength, as obtained from the model of equation (5.3.9) . . . . . . . 103

5.13 Transistor subcircuit, enhanced topology: source thermal resis-tance as a function of channel width (number of fingers) and chan-nel length, as obtained from the model of equation (5.3.10) . . . . 104

5.14 Transistor subcircuit, enhanced topology: bottom thermal resis-tance as a function of channel width (number of fingers) and chan-nel length, as obtained from the model of equation (5.3.11) . . . . 104

5.15 Output characteristic and temperature increments comparison be-tween the three subcircuits (Vgs = 1.2V, nfinger = 1 and L =100nm). The curves obtained with the classical and enhancedtopologies are almost superimposed . . . . . . . . . . . . . . . . . 106

5.16 Comparison between the three subcircuits in a transient simula-tion. An 8% current decrease with a time constant of 100ns dueto self-heating is observed, as expected . . . . . . . . . . . . . . . 107

5.17 Miller Op Amp schematic . . . . . . . . . . . . . . . . . . . . . . 1085.18 Miller Op Amp layout from the first FinFET testchip . . . . . . . 1095.19 Results of the Miller Op Amp simulation with the three subcircuits:

DC output characteristic, small signal gain and temperature of theM11 transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.20 Results of the Miller Op Amp simulation with increasing thermalresistances. RTH0ALTER is the normalized thermal resistanceRth0 expressed in

(m·KW

). Cross-heating has been neglected . . . . 113

xiv LIST OF FIGURES

List of Tables

1.1 MOS geometry scaling (constant field) . . . . . . . . . . . . . . . 31.2 Main scaling effects in MOS devices . . . . . . . . . . . . . . . . . 41.3 Main drawbacks due to device scaling in MOSFETs . . . . . . . . 41.4 MOS transistor downsizing limits [2] . . . . . . . . . . . . . . . . 4

2.1 Thermal conductivity of some materials used in microelectronics . 152.2 Approximate ranges of the convection coefficient of some substances 202.3 Electro-thermal analogy . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 Most important design rules for the second FinFET testchip . . . 584.2 Dimensions of the reference transistor . . . . . . . . . . . . . . . . 594.3 Reference transistor material properties . . . . . . . . . . . . . . . 604.4 External sources and boundary conditions for the reference tran-

sistor problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604.5 Simulation results of the reference 1-finger FinFET . . . . . . . . 64

xv

xvi LIST OF TABLES

Chapter 1

New transistor architectures

1.1 The microelectronics age

During the last few decades, microelectronics has evolved in a very extraordinaryand unpredictable way, bringing great transformations and improvements in hu-man life. Signs of these changes can be seen everywhere in our society: globalcommunications, information technology, medicine sciences but even arts and hu-man relationships have been heavily affected by the relatively recent discoveriesin semiconductor technology. Even though this technological run has been of-ten obstructed by the public opinion for its undoubted pervasiveness, nowadaysnothing leads to think that this growth will end in the future to come.

The main character of what has been called “microelectronics revolution” iswithout doubt the transistor. From the first heavyweight experimental semicon-ductor device (a rudimentary collection of wires, insulators and germanium firstdemonstrated in 1947 at Bell Labs by William Shockley (figure 1.1(a))) to therecent deep sub-micron silicon-on-insulator technologies (figure 1.1(b)), only 50years have passed by. Almost no other scientific discipline has ever known such

(a) First experimentalsemiconductor transistor,

1947, Bell Labs

(b) State-of-the-art MOSFET, 2002, Intel

Figure 1.1: 50 years of transistor technology evolution

1

2 New transistor architectures

a rapid growth in recent times.

The first attempt to give a formal definition to this seemingly simple semi-conductor device dates back to 1948, when the name transistor was used for thefirst time as an abbreviated combination of the words “transconductance” and“varistor”. From that time on, several enhancements and improved structureshave been developed and proposed by both semiconductor industries and scien-tific community. The undisputed winner of this technological race (figure 1.2) canbe considered the MOSFET, which is nowadays employed in the manufacturingof most of integrated circuits.

Figure 1.2: Market share of semiconductor devices

1.2 The MOS transistor

A diagram showing the typical structure of a MOSFET (Metal Oxide Semicon-ductor Field Effect Transistor) is presented in figure 1.3. It is often referred asbulk planar MOS, differentiating this structure from SOI and multi-gate tech-nologies. The classical MOS transistor is formed as a “sandwich” of three layers:a semiconductor layer (bulk), a layer of silicon dioxide (the oxide) and a layer

Figure 1.3: N-channel bulk MOSFET cross view

1.3 MOS device scaling 3

of metal. At present, most devices have polycrystalline silicon in place of metalgates. The transistor consists of three contacts, labeled “gate”, “drain” and“source”. Electrical charge, or current, can flow from the source to the draindepending on the voltage applied on the gate. N channel and P channel devicescan be manufactured, depending on the type of materials used to “dope” thedrain, source and substrate regions. The MOSFET can operate as a very effi-cient switch for the current flowing between the source and drain regions. Duringthe last decades it has become the most used element in the design of large scaleintegrated circuits.

One of the most popular MOSFET technologies available today is the comple-mentary MOS, or CMOS, technology. It employs both N and P channel devicesin the same substrate material. Such devices are extremely useful, since the samesignal which turns on a transistor of one type is used to turn off a transistor of theother type. The production process is more complex than that for simple MOStechnology, but several design improvements can be achieved, such as reducedDC power consumption.

1.3 MOS device scaling

During the past years, MOSFET performance has been improved mainly throughthe scaling of the transistor dimension. The study of the effects of a scaling ofthe main geometric dimensions by a factor 1/α can be carried out by analyzingthe formulas available for the parameters of the device. If we consider the scal-ing strategy presented in table 1.1, the power consumed per unit area remainsconstant. Simple relations derived for MOS transistors bring to the scaling rulespresented in table 1.2. Device scaling leads also to some drawbacks, as displayedin table 1.3.

Moore’s law predicts an exponential growth in the number of transistors perintegrated circuit. In the last 40 years it proved to correctly represent techno-logical trends, even though the exponential factor for some applications had tobe adjusted in order to match the changeable market situations. Despite theseveral efforts spent in the direction of MOS device scaling, this process cannotbe applied forever. Table 1.4 displays the MOS downsizing limits that the indus-try and scientific community have faced in the past years. Whenever a limitingfactor seemed to represent an insurmountable obstacle, new solutions have beenfound to overcome the problem. A particular effort in this direction has been em-ployed with the establishment of the ITRS (International Technology Roadmap

Parameter Scaling factorLength (L) 1/αWidth (W) 1/αOxide thickness (D) 1/αVoltage (V) 1/αDoping concentration (N) α

Table 1.1: MOS geometry scaling (constant field)


Parameter Scaling factor Formula

Transit time (τ) 1/α τ = L2/(µVDS); τ ′ = L2/α2

µV/α; τ ′ = τ/α

Gate capacitance (C) 1/α C = cLW/D

Current (I) 1/α I = µεW2LD

(VGS − Vth)2

Device area (Λ) 1/α2 Λ = LWGates / Unit area α2 1/ΛPower consumption (P) 1/α2 P = IV or P = CV 2/τPower / Unit area 1Channel resistance (R) 1 R = V/IGate delay (RC) 1/αSwitching energy (E) 1/α3 E = CV 2 or E = Pτ

Table 1.2: Main scaling effects in MOS devices

Parameter Scaling factor FormulaInterconnection resistance α σL/ΛInterconnect voltage drop α IR/VCurrent density α I/ΛContact resistance α2 1/ΛInterconnect signal propagation time 1 σLC/Λ

Table 1.3: Main drawbacks due to device scaling in MOSFETs

for Semiconductors), which tries to ensure Moore’s law by realizing the futureplanning of the semiconductor technology development.

As the feature size reaches the sub-micron range, the most important limitingfactors in bulk MOSFETs are the short-channel effects. A MOSFET is considereda short-channel device when the gate length is comparable with the width of thedepletion layer. In this situation, several detrimental physical phenomena occur:

• Drain Induced Barrier Lowering (DIBL), which causes the threshold poten-tial to be a function of the operating voltages

• punch-through, which consists of a sharp current increase due to DIBL andcan damage the device if a high source-drain voltage is applied

Period Expected limit (size) Causelate 1970’s 1µm short channel effectsearly 1980’s 0.5µm S/D resistanceearly 1980’s 0.25µm direct tunneling of gate oxidelate 1980’s 0.1µm variousearly 2000’s 50nm various

today 10nm practical limit?

Table 1.4: MOS transistor downsizing limits [2]

1.3 MOS device scaling 5

• surface scattering, which causes a reduced mobility due to collisions betweenthe electrons on the channel surface

• drift velocity saturation for high electrical fields, which reduces the transcon-ductance of short-channel devices in the saturation condition

• impact ionization, where high longitudinal fields accelerate electrons thatmay be able to ionize silicon atoms by impacting against them

• hot electrons, which occurs when the electrons flowing in the channel haveenough kinetic energy to surmount the surface potential of the gate oxideand are injected into the oxide

The overall effect of these phenomena is a reduced performance of the short-channel transistors.

In light of these considerations, to maintain scaling and performance in sub-micron transistors new solutions have been proposed [1]. They include both newstructural configurations such as Silicon On Insulator (SOI) MOSFET and multi-gate MOSFETS which will be discussed in sections 1.4 and 1.5 and new materialsand processes such as high-k dielectric (silicon dioxide gate insulation is replacedby material with higher dielectric constant), metal gate (polysilicon gate is re-placed by metal), low channel doping, strained silicon (silicon substrate is replacedby strained silicon), metal source-drain, and raised active areas. These new op-tions have been partially already implemented but are still under development.Compared to standard Bulk CMOS, their undisputed advantages will probablylead in the future to their widespread employment as mainstream technology.

Even though these structures are still under study, several papers (such as [1]and [2]) have faced even more challenging scaling factors. In particular, as thefeature size reaches the deep sub-micron range, more and more physical limitingfactors come out, so that Moore’s law seems difficult to be preserved in the futureto come. The main problems that must be faced for the sub-10nm MOSFETdevelopment can be summarized as follows:

• depletion layer formation on the polysilicon gate

• direct-tunneling current through the gate insulator

• fringing capacitance between gate and active areas

• high source-drain extension resistance

• channel inversion layer capacitance

• direct-tunneling current between active areas

• nonuniformity of bulk and active areas

In addition, the exploration of the sub-10nm area would require the applicationof the quantum theory: completely new approaches to transistor manufacturingand modeling would be necessary. Even though these problems would be solved,


it is clear that this scaling process cannot continue exclusively in this direction. Inparticular, technology processes are reaching the real ultimate physical limits forelectronic devices as we have always used them. Iwai in [2] has tried to extrapolatethe time frame for the reaching of these ultimate goals (figure 1.4), but practicallimits will emerge before the ultimate limit is reached. The big problem is thatno one knows where the practical limit is.

Figure 1.4: Foreseen ultimate limitations to device scaling [2]

1.4 SOI technologies

Silicon-On-Insulator (SOI) technology has emerged as an alternative to BulkCMOS technology to meet the scaling requirements for sub-100nm devices. Eventhough it has been employed for several years in particular applications such asmilitary and space exploration, only recently its adoption in mainstream appli-cations has been pursued. Several papers concerning their employment in analogcircuits have been presented ([3] and [4]).

The unique idea that characterizes SOI devices is the introduction of an in-sulating layer (Buried oxide, BOX) just below a superficial layer of silicon, asshown in figure 1.5. The main advantages of this new production process can besummarized as follows:

• excellent vertical and lateral isolation of active devices

• reduced parasitic junction capacitance, which in turn leads to faster deviceoperation

• lower dynamic power consumption

• reduced short channel effects when the device is scaled

1.4 SOI technologies 7

Figure 1.5: Typical SOI MOSFET cross view

On the contrary, new problems have arisen, the most important being the floating-body effects and the so called self-heating effects. The first one is caused by thefact that the body of the SOI device is isolated, thus resulting in an added par-asitic transistor connected in parallel. This causes a drain current discontinuityin the output characteristic (“kink” effect) that must be taken into account indevice simulations, since it degrades the differential drain conductance of thetransistor ([3], [5] and [6]). Even history effects occur in floating-body devices[7]. A partial solution to the floating-body effects have been found with the in-troduction of body-contacted devices, even though imperfectly body tied devicesreveal an even sharper kink effect [8]. Self-heating effects are due to the verylow thermal conductivity of the insulator layer, which creates a strong barrierfor the heat flow through the bulk. As it will be investigated in more detail inthe next chapters, this reduces heat removal leading to substantial temperatureincrements within the device, thus affecting some important quantities of thetransistor such as the threshold voltage and the mobility. The overall effect isa reduced on-current which can affect the correct behaviour of both analog anddigital circuits fabricated in these technologies. SOI transistors exist in mainlytwo nuances (figure 1.6): partially depleted (PD) and fully depleted (FD). In

Figure 1.6: Comparison between planar bulk, partially depleted SOI and fullydepleted SOI devices


partially depleted devices the top silicon layer is thicker than the depth of thedepletion region in the channel. In fully depleted devices the silicon film is totallydepleted and no holes are present. There are significant differences in these twoversions of SOI transistors [9]. So far, partially depleted devices resulted in animproved robustness to fabrication process variance. However, an optimizationof the device manufacturing process can shorten this gap, so that the final winnerhas still to emerge.

1.5 Multi-gate technologies

The need to further scale down CMOS technologies has forced the microelec-tronics industry to explore other device structures [10] that permit to overcomethe more and more challenging limitations of the classical structures. One ofthe most promising improvements consists in the introduction of devices withmultiple gates (multi-gate technologies) built over SOI substrates.

As displayed in figure 1.5, the classical SOI MOSFET has a single gate elec-trode located at the top of the device. In principle, a double-gate device can beobtained as depicted in figure 1.7. The introduction of a second gate in correspon-

Figure 1.7: Double-gate MOSFET

dence of the buried oxide layer permits to have a second channel, thus allowingincreased drive current. The first papers analyzing these new solutions predictedthe good short-channel characteristics of these devices [11].

The first double-gate devices received the acronym XMOS due to its resem-blance with the Greek letter Ξ. Later implementations of these structures consid-ered the opportunity to build vertical structures, where the conductive channelstands in the vertical direction. Such structures comprise the FinFET (figure1.8), the MFXMOS, the triangular-wire SOI MOSFET and the ∆-channel SOIMOSFET.

The good characteristics outlined by these new structures lead the scientificcommunity to propose structures with more than two gates. These include triple-

1.5 Multi-gate technologies 9

Figure 1.8: FinFET as a vertical double-gate transistor

gate structures [12] (figure 1.9), triple-plus-gate structures such as the omega-gateand pi-gate MOSFETs (figure 1.10) and quadruple-gate structures (figure 1.10).Even an “ideal MOS transistor” has been theorized, with a cylindrical metal gatecompletely surrounding a fully depleted region of semiconductor.

In this thesis, the attention is focused on the FinFET transistor [13], whosegeneral structure is presented in figure 1.8. This device derives its name from thesilicon fin that rises at the top of the SOI insulating layer and has a conductivechannel on both sides. The good scaling properties of this double-gate verticaldevice and its easy manufacturability using a traditional process flow have been

Figure 1.9: Single-gate, double-gate and triple-gate devices

Figure 1.10: Quadruple-gate and pi-gate devices


demonstrated, so that the FinFET has emerged as one of the most promisingmulti-gate structures. From a circuit designer’s point of view, the increaseddevice packing density offers the possibility of higher on-current, thus bringingconsiderable advantages to both analog [14] and digital circuit design. As it willbe pointed out later, even some drawbacks occur, the most important of thesebeing the well-known floating-body and self-heating effects.

Nonclassical MOSFET structures require new electrical compact models todescribe device characteristics. Even though standard electrical models for multi-gate devices have not been released yet, at present time much effort is being spentby the scientific community in this direction.

1.6 Self-heating

As CMOS technology scales down to deep sub-micron dimensions, power densityincreases accordingly, thus resulting in remarkable temperature increases in theactive devices. This problem has become even more critical with the introductionof SOI technologies, where the low thermal conductivity of the insulation layerbelow the top silicon film inhibits an efficient heat flow through the substrate asin standard bulk CMOS technologies.

Semiconductor components are really sensitive to temperature variations, thusrequiring a correct understanding and modeling of this issue. The impact ofraised operating temperatures in both analog and digital circuits has been alreadystudied ([15], [16] and [17]). The main effects can be summarized as follows:

• degraded carrier mobility which leads to a reduced on-current of transistorsand thus slower speed

• higher interconnect metal resistivity which yields longer delays

• increased failure rate and reduced reliability of electronic devices, with sec-ondary effects such as interconnect electromigration

In brief, performance, power consumption and reliability are affected. In digitalcircuits, the main consequences are longer delays due to increased interconnectresistance and reliability issues due to electromigration. Analog circuits are muchmore sensitive to temperature variations, which may degrade matching proper-ties. Thus, nowadays thermal simulations and modeling are playing an essentialrole in the design of integrated circuits. The concept of temperature-aware designhas been recently proposed: with the employment of the modern semiconductortechnologies, the temperature must be considered a guideline throughout theentire design flow. The strategy proposed in [18] employs a thermal model rep-resenting the thermal behaviour which continuously interacts with the modelsdescribing the other relevant aspects of the device (figure 1.11). The appropriateconvergence of the whole system permits to obtain a more accurate descriptionof the device under analysis, taking into account even the thermal effects.

1.7 Scope of the thesis 11

ModelReliability

PowerModelModel

Performance

ModelThermal

Figure 1.11: Possible application of the temperature-aware design concept

1.7 Scope of the thesis

This thesis focuses on the thermal characterization of the FinFET transistor.The new SOI structures are particularly affected by self-heating effects, whichmust be quantified in order to achieve temperature-aware design. In order toobtain an estimation of the temperature increment during the normal operatingconditions, the approach followed in this thesis is the development of a completethermal model based on device layout. The resulting lumped network describesthe steady-state thermal behaviour of both mono-finger and multi-finger devices.The dependence of the temperature increases on the geometric dimensions canbe easily evaluated, thus providing important indications for future device de-sign. Since the final objective is the implementation of self-heating effects in ananalog circuit simulation environment, a procedure for the parameterization ofthe thermal resistance versus channel length and channel width is presented anda circuit example is simulated.

Chapter 2

Heat Transfer Modeling

2.1 Introduction

Information obtained from heat transmission studies can be applied to a widerange of engineering applications, with typical problems requiring the calculationof temperature distributions and heat fluxes. In the previous chapter the necessityof a correct heat transfer modeling and understanding in modern SOI technologieshas been introduced. In this chapter, heat transfer modes and formulations arepresented, with special emphasis on semiconductor electronic applications. An-alytical solutions can be found only for very simple geometries: both analyticaland approximate techniques can be employed. This is the starting point to builda thermal compact network for the FinFET transistor that can be employed inany general purpose circuit simulator for electro-thermal simulation. This modelis the main outcome of this thesis and will be presented in the following chapters.

2.2 Mechanisms of heat transfer

In a typical semiconductor structure, heat spreads from the region where poweris dissipated mainly through conduction to the surrounding medium. The otherheat transfer modes, convection and radiation, are present in discrete components,but their contribution can be assumed to be negligible. A brief summary of thethree main mechanisms of heat transfer follows.

2.2.1 Heat conduction

Conductive heat transfer occurs in any material where temperature gradientsare present (figure 2.1) and strongly depends on the material properties. In asolid medium, the equation describing the temperature distribution in a genericgeometry is obtained from Fourier’s Law and the first law of thermodynamics.The complete formulation of the conduction problem is presented in the nextpages.

13

14 Heat Transfer Modeling

TEMPERATUREHIGH LOW

TEMPERATUREheat flow

Figure 2.1: Heat conduction in a solid material

2.2.1.1 Fourier’s law

The empirical law that is the basis of heat conduction theory has been formulatedby Joseph Fourier (figure 2.2) in its remarkable book Theorie Analytique de laChaleur in 1822. Fourier’s law is represented by the following statement: the heatflux, q (W/m2), resulting from thermal conduction is proportional to the magni-tude of the temperature gradient and opposite to it in sign. In one-dimensionalformulas, it can be expressed as:

q = −kdT

dx(2.2.1)

where k (W/m·K) is the constant of proportionality called thermal conductivity

Figure 2.2: Baron Jean Baptiste Joseph Fourier (1768-1830) [19]

2.2 Mechanisms of heat transfer 15

and q is the heat flux, which means that it is expressed per unit area.

The heat flux is a vector quantity. Heat flows from high to low temperatureregions. The three-dimensional form of the equation is

~q = −k∇T (2.2.2)

2.2.1.2 Thermal conductivity

Thermal conductivity is the material property that mostly affects heat conduc-tion. Fourier’s law denotes that there is a direct proportionality between thisproperty and the heat flux due to heat conduction in the material. Table 2.1summarizes thermal conductivity values for typical materials used in microelec-tronics.

Material Thermal Conductivity k(

Wm·K

), at 20C

Diamond 1350Copper (pure) 398

Gold 318Aluminum (pure) 235

Tungsten 178Silicon 140Zinc 121

Chromium 90Platinum 71

Titanium (pure) 22Silicon dioxide 1.38Glass (window) 1.22

Table 2.1: Thermal conductivity of some materials used in microelectronics

2.2.1.3 Nonlinear thermal conductivity

In semiconductor structures, the assumption of constant thermal conductivityk is justified only for small temperature differences. For larger differences, thethermal nonlinearity of k cannot be neglected. A good approximation for thenonlinear thermal conductivity k(T ) for semiconductor materials above about100K is

k(T ) = k(T0)

(T

T0

)−γ

(2.2.3)

where k(T0) is the conductivity at temperature T0 (approximately 140 W/m·Kfor silicon at T0=300K) and the constant γ is a material constant (approximately1.324 for silicon). Figure 2.3 displays the measured dependence of the thermalconductivities for several solid materials. Figure 2.4 shows the dependence of thethermal conductivity on the temperature for silicon.


Figure 2.3: Temperature dependence of the thermal conductivity of several solidmaterials [19]


0.6 0.8 1 1.2 1.4 1.6 1.8 2T/T0

0

0.5

1

1.5

2

2.5

3

k(T)

/k(T

0)

Figure 2.4: Temperature dependence of the thermal conductivity of silicon

2.2.1.4 Equations describing heat conduction

The problem under analysis consists of a generic three-dimensional volume Venclosed in an external surface A (figure 2.5). The rate of heat transfer Q enteringvolume V can be expressed as

Q = −∫

A

~q · ~ndA (2.2.4)

In the energetic balance, also the internal heat generation must be accounted for,in the following way:

dQg

dt=

∫V

HdV (2.2.5)

where H represents the heat generation rate inside the volume (W/m3). Finally,in solid materials, the internal energy variation can be expressed as

dU

dt=

∫V

ρdu

dtdV =

∫V

ρc∂T

∂tdV (2.2.6)

where U is the internal energy (J), ρ is the density of the material (kg/m3)supposed to be uniform, and c is the specific heat (J/kg·K). In the absence ofwork exchanges and variations of kinetic and potential energy, the first law ofthermodynamics assures that the internal variation of energy in one time unityequals the sum of the heat entering the volume and the heat internally generated.The relations (2.2.4), (2.2.5) and (2.2.6) permit to express the energetic balance


z

x

y

n

V

dA

A

Figure 2.5: Generic geometry for the heat conduction problem

for the volume under analysis in the following way∫V

ρc∂T

∂tdV +

∫A

~q · ~ndA−∫

V

HdV = 0 (2.2.7)

The divergence theorem can be applied to the second term, thus giving∫V

(ρc

∂T

∂t+∇ · ~q −H

)dV = 0 (2.2.8)

where the integration volume is arbitrary. Then, (2.2.8) necessarily implies that

ρc∂T

∂t+∇ · ~q −H = 0 (2.2.9)

The Fourier’s law expressed for an isotropic material (2.2.2) can be employed,thus leading us to the general equation for heat conduction in isotropic materials

ρc∂T

∂t= ∇ · (k∇T ) + H (2.2.10)

In case of uniform and temperature independent thermal conductivity, k can bemoved out of the divergence operator and both terms can be divided by ρc, thusgiving

∂T

∂t= a∇2T +

H

ρc(2.2.11)

where ∇2 represents the Laplacian operator and a is the thermal diffusivity ofthe material (m2/s). The thermal diffusivity represents how rapidly the temper-ature variations spread in the medium. From equation (2.2.11), in the absence ofinternal heat generation, the Fourier equation can be obtained

∂T

∂t= a∇2T (2.2.12)


Instead, in steady-state problems the Poisson equation can be obtained

∇2T +H

k= 0 (2.2.13)

From the Poisson equation, in the absence of internal heat generation, the Laplaceequation is derived

∇2T = 0 (2.2.14)

Equations (2.2.10), (2.2.11), (2.2.12), (2.2.13) and (2.2.14) are vector expressionswhich can also be written in cartesian, cylindrical and spherical coordinates.

2.2.1.5 Initial and boundary conditions

For the determination of the temperature distributions described by the heatconduction equations, boundary and initial conditions must be introduced.

On the external surface A of the domain under analysis V , three types ofboundary conditions can be applied: temperature, thermal flux and convection.On the portion of the external surface where temperature is imposed, we have

T = Ts (2.2.15)

that is known as Dirichlet or essential boundary condition. On the portion ofsurface where the heat flux is imposed, we have

qs = −k∂T

∂n(2.2.16)

Finally, on the portion of the external surface where convective heat transmissionoccurs with a fluid at temperature Tf , we have

qc = α (T − Tf) (2.2.17)

In case of transient problems, in addition to boundary conditions imposed on thespatial domain, even conditions on the time domain have to be imposed. Sincethe time domain is usually open and extends from the initial instant to infinite,these conditions are usually called “initial conditions”.

2.2.2 Heat convection

Convection is the heat transmission mode that occurs in a moving fluid (figure2.6. It is characterized by the simultaneous presence of conduction, related tomolecular interactions, and advection, associated to fluid fluxes.

Forced and natural convection are the typical convective heat transfer config-urations. We refer to forced convection when the fluid flux is caused by inter-ventions external to the thermal field, like pumps or fans. We refer to naturalconvection when the fluid flux is caused by density variations of the fluid gener-ated by the thermal fields themselves, like in the case of the ascending air fluxabove a warm surface. Both forced and natural convection can be laminar or tur-bulent, according to whether the fluid fluxes are organized in regular thin layersor are characterized by whirlpools and random perturbations.


Figure 2.6: Heat convection mechanism

In the typical case of a solid wall lapped by a fluid, the heat flux is generallyexpressed as

q = α (Ts − Tf) (2.2.18)

where Ts is the temperature of the wall external surface and Tf represents thetemperature of the undisturbed fluid. In (2.2.18), α is the convection coefficient(W/m2·K). Typical values of α are presented in table 2.2.

Situation Convection coefficient α(

Wm2·K

)Air in natural convection 3÷30Air in forced convection 10÷200

Water in natural convection 100÷1.000Water in forced convection 500÷5.000

Water vapor in condensation 1.000÷5.000Boiling Water 2.500÷50.000

Table 2.2: Approximate ranges of the convection coefficient of some substances

2.2.3 Heat radiation

Heat transfer by radiation is caused by electromagnetic waves propagation thatspread from any material at nonabsolute zero temperature (figure 2.7). Differently

Figure 2.7: Heat radiation mechanism

2.3 Solution of the heat conduction equations 21

than in the case of conduction and convection, direct heat transmission throughradiation does not require a material medium.

Stefan-Boltzmann’s law describes the maximum thermal flux that can be emit-ted by a surface at absolute temperature Ts:

q = σT 4s (2.2.19)

where σ = 5.67 · 10−8 (W/(m2·K4)) is the Stefan-Boltzmann constant. Thisfundamental law can then be employed to extract all the equations that describeradiative heat transmission between surfaces.

2.3 Solution of the heat conduction equations

The differential equations describing heat conduction in solid mediums can beanalytically solved in a very limited number of situations, where geometries andboundary conditions are very simple. Therefore, in practical applications theemployment of sophisticated Computer Aided Design (CAD) tools has becomethe most common solution to approach these problems. In the past years, severalmethodologies, analytical and numerical, have been proposed and standardized.They can be summarized as follows [20]:

• Analytical solutions:

– Fourier SeriesIn this method, the temperature distribution and heat sources areexpressed as proper Double Fourier cosine series that match the steady-state heat conduction equations and boundary conditions.

– Transformation Method.This method employs a simplified Laplace transform with a two-dimensional cosine transform, thus allowing to obtain a conventionaldifferential equation depending on a single variable. The simple solu-tion can then back transformed to obtain the solution in the originaldomain.

– Compact Models.In the steady-state problem, a Compact Model is a resistance net-work whose values are extracted from the solution of the heat flowconduction equations. Even thermal capacitances must be extractedif the study of the dynamic problem is requested. The final result ofthis extraction procedure is a complete lumped thermal R-C networkwhich describes both static and dynamic thermal behaviour of thecomponent. In these works, the well-known analogy between electricaland thermal quantities (table 2.3) is applied: voltage at a node of theequivalent circuit is the temperature rise in the material, current is theheat flux, and resistances and capacitances are the thermal resistancesand capacitances, respectively. The heat sources are modeled with cur-rent sources connected to the proper nodes. With this structure, the


Electrical quantity Thermal quantity

Voltage (V) Temperature rise (K)Current (A) Heat flow (W)

Resistance (Ω) Thermal resistance (K/W)Capacitance (F) Heat capacity (J/K)

Time constant (s) Thermal time constant (s)

Table 2.3: Electro-thermal analogy

evaluation of heat flows and temperatures at specific points is easilyobtained by employing circuit simulators. If the voltage at an arbitrarydistance is needed, interpolation/extrapolation techniques are easy toapply.

• Numerical solutions:

– Heat Transfer EquationThe solution obtained from numerical approaches such as Finite El-ement Method (FEM) and Finite Difference Method (FDM) satisfiesthe differential equation describing the problem under analysis on av-erage on the whole domain.

– Computational Fluid DynamicsIn these methods, fluid dynamics similarity and equations are appliedby analogy to the thermal problem. The intensive computational re-quirements and lack of robustness are issues still to be solved.

• Electro-thermal solutions:

– Direct Method (Fully Coupled Method)Taking advantage of the analogy between electrical and thermal quan-tities, the electrical and thermal responses of the component are solvedconcurrently by a circuit simulator. Power dissipation in the compo-nent active area is calculated and the resulting heat flux acts as theinput to the thermal model for the structure. The thermal behaviourof the component is realized with an analytical model or an electricalequivalent circuit. The response of the thermal model, the averagetemperature, controls the components behaviour by changing the dis-sipated power. The electro-thermal components are implemented inany general purpose circuit simulator.

– Relaxation MethodThe electrical and thermal problems are split and solved with differenttools. Generally, a circuit simulator is employed for the electrical partwhilst a finite element software solves the thermal problem. The sepa-rate tools must reciprocally interact. Convergence and computationalcost can be important issues.

– TCAD simulatorsThe microscopic equations describing carrier transport and heat trans-

2.4 Solution in simple cases 23

fer are solved simultaneously on a discretized mesh representing thegeometry under analysis [21].

2.4 Solution in simple cases

There are three general types of heat spreading models depending on the heattransfer path, the most important being the three-dimensional model, especiallywhen heat is generated in a small volume. The one and two-dimensional modelscan have applications in specific situations. Despite these considerations, thereally complex 3d structure of the FinFET under study does not allow an easyanalytical solution of the heat conduction equations. In this section the mainformulas of the thermal resistances used in our thermal model are presented,thus revealing the use of only one-dimensional heat flow in each material stripein which the complete geometry has been split.

2.4.1 Rectangular material stripe

The structure displayed in figure 2.8 represents the typical situation where theheat is assumed to flow one-dimensionally. No heat dissipation through the lateralsurfaces occurs. With these assumptions, the temperature on a plane orthogonal

t

L

W

Figure 2.8: Heat flow through a rectangular material stripe

to the heat flow is constant, hence the temperature is specified only by the po-sition x evaluated along the length of the structure. Even though in figure 2.8 arectangular cross section is considered, the shape of the transversal area can bearbitrarily chosen.

In one-dimensional steady-state problems the Fourier’s law 2.2.2 can be ex-pressed in a very convenient scalar form:

q = k∆T

L(2.4.1)

where L is the length of the structure calculated along the direction of the heatflow and ∆T is the temperature difference of the two external interfaces.The thermal resistance of the stripe can be easily calculated as follows:

Rth,rectangular =∆T

Q=

∆T

q A=

L

k A=

L

k t W(2.4.2)

where k is the thermal conductivity of the material. This formula will be widelyemployed in the thermal model of the FinFET.


2.4.2 Trapezoidal material stripe

The geometry of this structure is depicted in figure 2.9. It represents a situation

L

W(0) W(L)

t

Figure 2.9: Heat flow through a trapezoidal material stripe

where the heat flows one-dimensionally but the transversal section is not constant.The top view of the structure is represented in figure 2.10. The thermal resistancecan be calculated starting from the formula 2.4.2, derived for the rectangularmaterial stripe. If we consider an infinitesimal stripe, its thermal resistance dRth

can be calculated as follows:

dRth =dx

kA(x)=

dx

ktW (x)=

dx

kt[(

W (L)−W (0)L

)x + W (0)

] (2.4.3)

The thermal resistance of the whole structure can be calculated by integrating

W(x)

dR=dx/kA(x)

dx

x=L

y

xx=0x=0

Figure 2.10: Top view of the trapezoidal stripe


dRth along the length of the structure:

Rth,trapezoidal =

∫ L

x=0

dx

kt[(

W (L)−W (0)L

)x + W (0)

] (2.4.4)

If we consider

s =

(W (L)−W (0)

L

)x + W (0) (2.4.5)

we have

Rth,trapezoidal =

∫ W (L)

s=W (0)

1

kt

L

W (L)−W (0)

1

sds =

=L

ktW (0)

ln(

W (L)W (0)

)W (L)W (0)

− 1

(2.4.6)

In case of W (0) = W (L), this formula gives 00. If we consider that

limx→0

ln(x + 1) ≈ x (2.4.7)

we getlimy→1

ln y ≈ y − 1 (2.4.8)

then

Rth,trapezoidal,W(0)=W(L) =L

ktW (0)(2.4.9)

This result agrees with the formula obtained for the rectangular material stripe2.4.2.

2.4.3 Rectangular material stripe with one nonadiabaticsurface

This geometry is thermally modeled with the so called π2 structure, which willbe intensively used inside the thermal model of the FinFET. Its name relates toits particular topology (see figure 2.11(b)), which looks very similar to a seriesof two π resistance networks. This structure represents the one-dimensional heatflow through a rectangular stripe of material surrounded on side and top walls byadiabatic surfaces. The bottom surface is not adiabatic and it is separated froman ambient-temperature surface by a material of thermal conductivity kbottom.Basically, there are two heat flow paths: through the stripe and towards thebottom surface. All the thermal resistances are calculated with the formulasfor the rectangular material stripe, provided that the right geometric dimensionsand materials are considered. The geometry of the problem is displayed in figure2.11(a). Figure 2.11(b) depicts the thermal network associated to the structure.The thermal resistances are calculated as follows:

R1 = R3 =tbottom

4kbottomLW(2.4.10)


H

L

W

node_A node_Bnode_C

k_inner

t_bottom k_bottom

T_amb

(a) Geometry of the rectangular material stripe located at the top of a material layer

R1 R2 R3

R4 R5node_A

node_C

node_B

(b) Thermal compact network of the rectangular material stripe located at the top of amaterial layer. Heat can flow along the stripe and through the bottom surface

Figure 2.11: Rectangular material stripe located at the top of a material layer


R2 =tbottom

2kbottomLW(2.4.11)

R4 = R5 =L

2kinnerHW(2.4.12)

As a further improvement, even heat flow through side and top walls can bemodeled. The node C is externally available for this purpose. In any case, it canbe left floating to simulate the absence of lateral and upward heat flow. Thisstructure is mainly used for the thermal modeling of material stripes locatedabove oxide layers. Even metal lines are represented by means of π2 structures.

2.4.4 Rectangular material stripe with nonadiabatic lat-eral surfaces

This structure represents the situation where the heat can flow along a rectangularmaterial stripe and through its lateral surfaces. The geometry is displayed infigure 2.12. Figure 2.13 depicts the front view of the geometry and the heat

x=Lx=0x

Pin (W/(m*m))

Figure 2.12: Heat flow through a rectangular material stripe with nonadiabaticsurfaces

flowing through the lateral surfaces. If we assume the boundary surfaces atambient temperature T0 and the heat flowing in parallel lines as displayed infigure 2.13, an analytical approach can be carried out. The heat flow balance ina structure with a length of ∆x can be expressed as

AinnF (x) = AinnF (x + ∆x) + AbottFbott + AtopFtop + Aside1Fside1 + Aside2Fside2

(2.4.13)where F are the heat fluxes (W/(m2)) and A are the surface areas (m2). Theareas can be rewritten as

Ainn = tinnWinn

Abott = Atop = Winn∆x

Aside1 = Aside2 = tinn∆x

(2.4.14)


T0

T0

T0 T0t_inn

W_inn

t_bottom

t_top

t_side1 t_side2

Figure 2.13: Front view of the rectangular material stripe with nonadiabaticsurfaces

If we consider the heat flowing through the bottom surface of the stripe towardsthe bottom boundary surface, we can write

Rbott =tbott

kbottAbott

(2.4.15)

Wbott =T (x)− T0

Rbott

=kbottAbott

tbott

[T (x)− T0] (2.4.16)

Fbott =Pbott

Abott

=kbott

tbott

[T (x)− T0] (2.4.17)

where kbott (W/(m·K)) is the thermal conductivity of the bottom material, Rbott

(K/W) is the thermal resistance of the bottom layer, Wbott (W) is the heat flowingfrom the stripe towards the bottom and T (x) (K) is the temperature at distance x.Equations similar to (2.4.15), (2.4.16) and (2.4.17) can be derived for the lateraland top surfaces of the stripe. Hence, the equation (2.4.13) can be rewritten as

tinnWinnF (x) = tinnWinnF (x + ∆x)+

+ Winn∆xkbott

tbott

[T (x)− T0] + Winn∆xktop

ttop

[T (x)− T0] +

+ tinn∆xkside1

tside1

[T (x)− T0] + tinn∆xkside2

tside2

[T (x)− T0]

(2.4.18)

tinnWinnF (x)− F (x + ∆x)

∆x=

=

(Winnkbott

tbott

+Winnktop

ttop

+tinnkside1

tside1

+tinnkside2

tside2

)[T (x)− T0]

(2.4.19)

If we consider ∆x → 0, then

−dF (x)

dx=

(kbott

tinntbott

+ktop

tinnttop

+kside1

Winntside1

+kside2

Winntside2

)[T (x)− T0] (2.4.20)


The heat flows one-dimensionally in the internal material along the x-direction,hence the Fourier’s law can be expressed as

F (x) = −kinndT (x)

dx(2.4.21)

and thendF (x)

dx= −kinn

d2T (x)

dx2(2.4.22)

The equation (2.4.22) can be employed in (2.4.20), thus leading to the differentialequation describing the temperature distribution along the internal stripe

d2T (x)

dx2= γ2 [T (x)− T0] (2.4.23)

with

γ =

√kbott

kinntinntbott

+ktop

kinntinnttop+

kside1

kinnWinntside1

+kside2

kinnWinntside2

(2.4.24)

where γ (1/m) is a constant which depends only on the geometry and the mate-rials of the problem. The general solution of the differential equation (2.4.23) is

T (x) = C1 eγx + C2 e−γx + T0 (2.4.25)

where C1 and C2 are constants which depend on the boundary conditions of theproblem. The heat flux expression can be calculated starting from the Fourier’slaw (2.4.21) applied to the expression (2.4.25)

F (x) = −kinnγ C1 eγx + kinnγ C2 e−γx (2.4.26)

The boundary conditions of the problem areT (L) = TL

F (0) = Pin(2.4.27)

They can be applied to the expressions (2.4.25) and (2.4.26) for the calculationof the constants C1 and C2 C1 =

− Pinkinnγ

e−γL+TL−T0

2 cosh(γL)

C2 =Pin

kinnγeγL+TL−T0

2 cosh(γL)

(2.4.28)

The equations (2.4.28) can be applied to (2.4.25) and (2.4.26). The final expres-sion of the temperature along the structure is

T (x) =Pin

kinnγ cosh(γL)sinh [γ(L− x)] +

TL − T0

cosh(γL)cosh(γx) + T0 (2.4.29)

The final expression of the heat flux along the structure is

F (x) =Pin

cosh(γL)cosh [γ(L− x)] +

kinnγ(TL − T0)

cosh(γL)sinh(γx) (2.4.30)


The structure studied in this section can represent the silicon fin of a FinFET,when it is wrapped by the poly gate. If we consider a typical geometry (as it willbe presented in tables 4.2 and 4.3), we can assume kbott = ktop = kside1 = kside2 =1.38 (W/(m·K)), kinn = 141 (W/(m·K)), tbott = 200 · 10−9 (m), ttop = 44.5 · 10−9

(m), tside1 = tside2 = 2 · 10−9 (m), tinn = 88 · 10−9 (m), Winn = 55 · 10−9 (m),Pin = 140·10−6

55·10−9·88·10−9 = 28.9 · 109 (W/m2), L = 50 · 10−9 (m), T0 = 25 (C) andthe constant γ calculated with the equation (2.4.24) results 1.35 · 107 (1/m). Thecurve of the resulting temperature distribution along the structure is displayedin figure 2.14. Several boundary temperatures at the end of the structure havebeen considered. This figure demonstrates that a linear approximation of thecurves does not lead to great errors, especially if the temperature at the endof the structure is near the ambient temperature. Hence, the structure can beprofitable approximated with a lumped thermal network. This is the approachthat will be followed in the next chapter in the thermal model of the FinFET.

0 10 n 20 n 30 n 40 n 50 nx

20

30

40

50

60

70

Tem

pera

ture

TL=25TL=30TL=35TL=45TL=55TL=65

Figure 2.14: Temperature curves along the rectangular material stripe with nona-diabatic lateral surfaces, for several boundary temperatures at the end of thestructure

2.5 Conclusions

In this chapter, heat transfer theory and modeling have been presented. In typi-cal semiconductor problems, the most important heat flow mechanism is the heatconduction, whose differential equations can be solved with both analytical and

2.5 Conclusions 31

numerical methodologies: several approaches have been summarized and the so-lutions in simple cases have been derived. The obtained simple expressions arethe basis for the building of a thermal compact network for the FinFET in thenext chapter, which can be used in a circuit simulator to model the thermal partof the component model.

Chapter 3

Thermal model for the FinFET

3.1 Introduction

During the last years, several methodologies for the extraction of thermal compactnetworks for both bipolar and planar MOS transistors have been presented. In thescientific literature some ideas for the compact modeling of double-gate transistors(in particular FinFETs) can be found, but no complete networks are referenced.As a result, this work will start almost from scratch in its effort to proposea complete solution for these new structures. Since the final objective of thework is the circuit simulation, throughout the chapter big care will be givento the feasibility of the implementation of the networks in a circuit simulationenvironment.

In the first part of this chapter, the 3d model and geometry of the FinFETunder analysis will be presented. The whole geometry will be then partitionedin basic blocks whose combination will lead to the complete thermal networkof the FinFET. The decomposition of the geometry facilitates enormously thestudy of both mono-finger and multi-finger devices (which in fact consist of theparallel between a given number of fingers). As a final result, we will end up witha resistive network which represents the static thermal behaviour of the device.For arbitrary number of fingers, two external nodes will be available (figure 3.1):the heat source (input node used to feed the thermal network with a current equalto the power dissipated in the transistor) and the hotspot (output node used tosense the temperature increase in the transistor due to power dissipation).

In this chapter no numerical values are introduced, only general purpose for-mulas are provided. In the next chapter these formulas will be applied to thegeometric dimensions of a typical FinFET (geometry based on the design rulesfor the second FinFET testchip planned at Infineon) and the whole structure willbe simulated with a circuit simulator.

3.2 Description of the FinFET geometry

In this section the geometry of the structure under analysis will be presented.In the modeling of the transistor several assumptions and simplifications will

33

34 Thermal model for the FinFET

delta temperature hotspot

heat source

ambient temperature

power

networkthermal

Figure 3.1: General thermal network of a transistor. Two external nodes areavailable: the heat source is employed for the injection of the power dissipated inthe device whilst the hotspot represents the temperature of the device

be made. The final objective is to obtain a good trade-off between structurecomplexity and easiness of computation.

The simplest structure that can be considered is displayed in figure 3.2. Amono-finger device consists of a fin (whose sidewalls are the channels where thecurrent flows), an oxide layer, a polysilicon line that wraps the fin (the so calledpoly gate), two active areas (source and drain), a polysilicon pad, contacts andmetals. The metals should (and will) be considered for the modeling of cross-heating between adjacent transistors connected by means of metal lines. Fur-thermore, they cannot be neglected in the study of self-heating itself, since theirinfluence in determining the temperature rise of a single isolated transistor willbe proved to be not trivial. Figure 3.2 shows the 3d views of the device and theaxis orientation (these information will be useful later when the geometry will bepresented in more detail). Figure 3.3 depicts the side views of the transistors.Figures 3.4 and 3.5 display simplified top and cross views of the 1-finger FinFET.The dimensions are not drawn to scale and represent only the typical topologyof the problem under analysis.

As already pointed out before, the compact model proposed in the followingsections can be with little effort used to represent even multi-finger devices, bysimple proper combination of the basic blocks. The geometry of a typical multi-finger device is presented in figure 3.6. The overall geometry is similar to theone considered for the mono-finger device, except for the presence of several fins(used to achieve higher current drives) and contacts.

3.2 Description of the FinFET geometry 35

(a) 3d view of the 1-finger FinFET

(b) Zoomed 3d view of the 1-finger FinFET

Figure 3.2: Geometry under analysis: 1-finger FinFET


(a) yz-plane view of the 1-finger FinFET

(b) xy-plane view of the 1-finger FinFET

(c) Top view of the 1-finger FinFET

Figure 3.3: Geometry under analysis: views of the 1-finger FinFET

3.2 Description of the FinFET geometry 37

finfinfin drain_contactsource_contact

gate_pad

drain_padsource_pad

poly_gate_line

contact

Figure 3.4: Simplified top view of the 1-finger FinFET

poly_silicon

poly_silicon_line poly_silicon_line

buried_oxide_layer

ONO_hard_mask

gate_oxide

silicon_fin

gate_oxide

bottom_silicon

Figure 3.5: Simplified cross view of the 1-finger FinFET


(a) Zoomed 3d view of the 16-finger FinFET

(b) Top view of the 16-finger FinFET

Figure 3.6: Geometry under analysis: views of the 16-finger FinFET

3.3 Thermal resistance 39

3.3 Thermal resistance

The simplest way to represent the static thermal behaviour of an electronic deviceis to define its thermal resistance. In this thesis, according to the well-knownanalogy between electrical and thermal properties of materials already presentedin the previous chapter, the thermal resistance Rth of a transistor is defined asthe static temperature rise ∆T of the heated volume for a unit quantity of heatsupplied Q, that is:

Rth =∆T

Q(3.3.1)

The quantity of heat equals the DC power dissipated in the component. Inthis definition, the position of the hotspot (the location where the temperatureincrement is sensed) must be carefully chosen. This reference point can alsorepresent the average value of a set of points or a volume.

Thermal coupling (or thermal interference) between transistors occurs whena heated device causes a temperature rise in another temperature dependentelectrical component. Generally, the total temperature rise can be expressed as:

∆T = Rth,11Q1 + Rth,21Q2 (3.3.2)

where Q1 is the heat flow generated by the component itself and Q2 is the heat flowgenerated by another component. Rth,11 is the thermal resistance and representsthe self-heating of the component, whilst Rth,12 is the thermal cross-resistance orthermal transfer resistance between the two devices.

3.4 Basic blocks of the thermal compact net-

work

The geometries (both mono-finger and multi-finger) just introduced are very com-plex and the exact solution of the thermal dissipation would require the studyof heat conduction in a three-dimensional environment. Hence, the analyticalsolution of the heat conduction equations in such geometry cannot be easily car-ried out. Even in the scientific literature only very simple geometries have beenanalytically solved for the calculation of the thermal resistance. In this work nocomplex mathematic methodology will be employed, but a more practical ap-proach will be applied: considering the main heat flow paths, the whole geometrywill be cut in simpler basic blocks whose thermal resistance can be easily cal-culated with the analytical expressions derived in chapter 2. As a result, thewhole structure will be considered as a proper combination of rectangular andtrapezoidal stripes. This assumption must be verified (finite-elements simulationsshould be employed for this purpose), but as a first order approximation it looksreasonable (and the simulation results agree with the measurements presentlyavailable).

This section now proceeds with the presentation of the thermal networks forthe simple basic blocks, whose combination will represent the thermal networkfor the whole transistor.


3.4.1 Metal line

As already introduced in the previous section, a metal line is modeled by a simpleπ2 structure (node C left floating). In fact, it is nothing more than a metallicstripe and, as a first order approximation, the nearest ambient-temperature sur-face can be considered the bottom silicon. With these assumptions, figures 3.7should be easy to understand. The π2 structure representing the metal line ischaracterized by the following parameters:

L = lmetal

W = wmetal

H = tmetal

tbottom = hcontact + hfin + tBOX

kinner = kmetal

kbottom = kox

(3.4.1)

Even though some assumptions might be considered too simplifying (the absenceof nearby metal lines which can interfere with our line, the actual thermal con-ductivity of the material that surrounds the metal line, and so on), from thesimulations presented in the next chapters it will be clear that the metal linesare not so critical in determining the thermal resistance of the whole structure.Hence, these assumptions can be considered reasonable.

3.4.2 Poly gate termination

This structure represents the combination of the polysilicon line connected tothe poly gate, the poly gate pad and the gate contact. Figure 3.8(a) displaysthe geometry of this structure, whose external node is located at the top of thegate contact. Figures 3.8(b) and 3.8(c) depict the complete thermal networkassociated to the poly gate termination. The poly stripe is modeled with a π2

structure, whose parameters are the following:

L = lpoly

W = wpoly

H = tpoly

tbottom = tBOX

kinner = kpoly

kbottom = kox

(3.4.2)

As displayed in figure 3.9, the path from the end of the poly line to the base ofthe contact is modeled with a trapezoidal material stripe:

Rpolypad,trapezoid =

wz,polypad−wz,contact

2

kpoly · tpoly · wpoly

·ln

(wx,contact

wpoly

)wx,contact

wpoly− 1

(3.4.3)

3.4 Basic blocks of the thermal compact network 41

T_amb

k_ox t_BOX

h_fin

h_contact

t_metalk_metal

w_metal

l_metal

BA

(a) Metal line geometry

A B

(b) Thermal compact network of the metal line, consisting of a π2 structure

L=l_metalW=w_metal

k_inner=k_metalk_bottom=k_ox

t_bottom=h_contact+h_fin+t_BOXH=t_metal

BA

(c) π2 structure of the metal line

Figure 3.7: Geometry and thermal model of the metal line


k_contact

B

A

k_oxk_poly

h_poly

h_fin

h_polycontact

w_z,contact

w_x,contactw_z,polypad

w_x,polypad

t_BOX

l_poly

h_polyw_poly

(a) Poly gate termination geometry

R_polypad,contact

R_polypad,bottomR_polypad,trap

Pi_2

B

A

(b) Thermal compact network of the poly gate termination

L=l_polyW=w_polyH=t_poly

t_bottom=t_BOXk_inner=k_polyk_bottom=k_ox

BR_polypad,trapezoid

R_polypad,bottom

R_polypad,contactA

(c) Complete thermal network of the poly gate termination: the poly line is repre-sented with a π2 structure

Figure 3.8: Geometry and thermal model of the poly gate termination


ActiveArea

Contact

w_z

,con

tact

w_f

in

Fin

Figure 3.9: Heat flowing from the poly line end to the contact

The resistances associated to the contact and to the heat flow from the poly padto the bottom are calculated in the usual way:

Rpolypad,bottom =tBOX

kox · wx,polypad · wz,polypad

(3.4.4)

Rpolypad,contact =hpolypad contact

kcontact · wx,contact · wz,contact

(3.4.5)

3.4.3 Source-drain contact

The source-drain contacts (Figure 3.10) are the plugs between the active areasand the metal, the pads are not included. Even though a contact can be mod-eled with a simple thermal resistance and hence could be easily included in othermore complex blocks, the final decision was to consider them as separate blocks.The reason for this decision is the need in multi-finger devices to have a certaindegree of flexibility concerning the locations where the contacts are connected tothe active areas. In fact, from the design rules it is clear that in multi-finger tran-sistors there is one contact every four fingers. Leaving several available externalnodes from the active areas, with this approach the contacts can be connected tothe active areas in almost arbitrary locations. The formula for the source-draincontact is the following:

RSD,contact =hcontact

kcontact · wx,contact · wz,contact

(3.4.6)

3.4.4 1 finger

This is the core of the thermal compact model for the FinFET. It representsthe network for 1 finger, without considering source-drain contacts, poly gateterminations and metal lines. Hence, this structure must not be confused with the


h_contactk_contact

w_z,contact

w_x,contact

A

B

(a) Source-drain contact geometry

R_SD,contact

A

B

(b) Thermal compact network of the source-drain contact

BAR_SD,contact

(c) Thermal resistance of the source-drain contact

Figure 3.10: Geometry and thermal compact model of the source-drain contact.The structure does not include the pad but only the plug between the active areaand the metal line


poly_gatew

_z

w_x,contact

w_x,activew

_z,c

onta

ct

l_fin

w_f

in

source_active_area drain_active_area

d_gatecenter,hotspot

d_gatecenter,heatsource

w_poly=l_gate

t_po

ly,w

rap

(a) 1-finger structure, top view and geometry. The source-drain pads (without the contacts)are parts of the structure

t_BOX

bottom_silicon

t_poly

t_ONO

t_poly,wrap

t_poly,wrap t_poly,wrap

k_poly

k_ox

k_ox

k_siliconh_fin

t_GOXt_GOX

(b) 1-finger structure, cross view of the fin below the poly gate

Figure 3.11: Geometry of the 1-finger structure


thermal network of the whole 1-finger transistor. In fact, as it will be explainedin the following pages, the thermal network of two fingers is the parallel betweenthat of two 1-finger, but this is not true for the network of the whole 2-fingertransistor, which is not the parallel between two 1-finger transistors.

Since the most important part of the heat dissipation occurs in the surround-ings of the heat source, the main assumptions made to model this structure arevery critical in determining the final results. Hence, particular attention must beemployed at this stage.

One of the biggest concerns is related to the shape and position of the heatsource. In principle, the heat source point (or region) should correspond with theposition of maximum vector product between electric field and current density.TCAD simulations should be employed for a more reliable assessment of theheat source. The final decision in this work was to consider the heat source asa rectangular planar surface across the fin. Any position along the fin can beconsidered, but in this work the possibilities have been restricted to the areabelow the poly gate, towards the drain. Little effort can be spent to extendthis assumption to an arbitrary position along the fin. Several papers investigatethe shape and location of the heat source in MOS transistors. Even though thecommon feeling suggests a heat source located below the gate and towards thedrain, in [25] Montecarlo simulations suggested that heat generation takes placeoutside the gate. One possible solution could be to consider that heat is generatedin two planes along the side-walls of the fin, in correspondence of the channel.However, this case cannot be easily solved in an analytical way. Better answerscan be provided by means of finite elements simulations (not available at themoment of the writing of this thesis).

The hotspot is the point where the temperature is sensed. Even the decisionof its location is an issue that must be well-pondered. In principle, the hotspotshould be chosen as the point where the temperature influences the current. Inabsence of further TCAD simulations, in this model the choice was to considera spot located between the center of the fin and the heat source. However, thisis one of the points that must be better investigated in the future by means offinite element simulations.

The top view of the structure is displayed in figure 3.11(a). As explainedbefore, source and drain contacts are not part of the geometry. The wz parameterrepresents the z-width of the structure. It influences the distance between fingersin multi-finger devices and it strongly depends on the number of fingers (accordingto design rules). Figure 3.11(b) depicts the cross view of the geometry underanalysis. In this figure the geometries are not drawn to scale.

The complete thermal compact network of the structure is presented in figure3.12. In order to avoid too much confusion in the figure, no labels for the thermalresistances are inserted. They are completely displayed in figures 3.13, whichshows several side views and selected slices of the whole network. As for thethermal modeling, once again the main heat flow paths are considered, and theclassical formulas for the material stripes are used. The resulting expressions arethe following:

Rgate center,hotspot =dgate center,hotspot

ksil · wfin · hfin

(3.4.7)


sour

ce1

sour

ce2

sour

ce_f

in_1

sour

ce_f

in_2

hots

pot

poly

2

heat

_sou

rce

poly

1

drai

n_fi

n_2

drai

n_fi

n_1

drai

n1

drai

n2

sour

ce_c

ente

rdr

ain_

cent

er

Pi2Pi2

Pi2

Pi2

Figure 3.12: Complete thermal compact network of the 1-finger structure (fin andsource-drain pad). The Pi2 blocks are the π2 structures presented in section 2.4.3.The upper and lower nodes can be used to connect several fingers in parallel inmulti-finger devices.


Pi2Pi2poly1poly2

R_gatecenter,bottom

R_gatecenter,top

R_gatecenter,side2 R_gatecenter,side1

(a) 1-finger structure, view of the fin below thepoly gate. Heat can flow through the gate ox-

ide and reach the poly gate line

source_gate_edge

R_source,fin2

R_source,fin1

R_source,trapezoid

X_source_fin

R_source,bottom

R_source2

R_source1

source1

source2

source_center

source_fin_2

source_fin_1

Pi2

(b) 1-finger structure, view of the source activearea. Heat can flow through the fin and reach

the source active area

R_gatecenter,bottom

R_heatsource,draingateedge

R_hotspot,heatsource

R_gatecenter,hotspot

R_gatecenter,sourcegateedge

R_gatecenter,top

drain_gate_edgesource_gate_edge

source_fin drain_fin

bottom_silicon

BOX

ONO

poly_wrap

(c) 1-finger structure, cross view of the fin be-low the poly gate. Heat generated in the heatsource point can flow towards the drain, source,

gate and bottom silicon

Figure 3.13: Thermal compact network of the 1-finger structure (fin and source-drain pad)


Rhotspot,heat source =dgate center,heat source − dgate center,hotspot


(3.4.8)

Rheat source,drain gate edge =lgate

2− dgate center,heat source


(3.4.9)

Rgate center,source gate edge =lgate

2


(3.4.10)

Rgate center,bottom =tBOX

kox · lgate · wfin

(3.4.11)

Rgate center,top =tONO

kox · lgate · wfin

(3.4.12)

Rgate center,side 1 = Rgate center,side 2 =tGOX

kox · lgate · hfin

(3.4.13)

Rgate center,side 2 =tGOX

kox · lgate · hfin

(3.4.14)

Xdrain fin and Xsource fin are π2 structures with:

L =lfin − lgate

2W = wfin

H = hfin

hbottom = tBOX

kinner = ksil

kbottom = kox

(3.4.15)

Xpoly 1 and Xpoly 2 are π2 structures with:

L =wz − wfin

2− tpoly wrap

W = wpoly

H = hpoly

hbottom = tBOX

kinner = kpoly

kbottom = kox

(3.4.16)

Rdrain,fin 1 = Rdrain,fin 2 = Rsource,fin 1 = Rsource,fin 2 =wz−wfin

2

kox · lfin−lgate2

· hfin

(3.4.17)

In the active areas trapezoidal resistances are considered, similar to those for thepoly pad:

Rdrain,trapezoid = Rsource,trapezoid =wx,active−wx,contact

2

ksil · hfin · wfin

·log

(wz,contact

wfin

)wz,contact

wfin− 1

(3.4.18)


Rdrain,bottom = Rsource,bottom =tBOX

kox · wx,active · wz

(3.4.19)

Rdrain1 = Rdrain2 = Rsource1 = Rsource2 =wz

2

ksil · wx,active · hfin

(3.4.20)

In figure 3.12, upper and lower nodes can be used to connect several fingers inparallel in multi-finger devices.

3.4.5 2 fingers

The complete thermal network for one finger presented in the previous sectionnatively supports multi-finger networks, since it is possible to simply put severalfingers in parallel and connect the corresponding nodes (upper and lower nodesin figure 3.12) to obtain the complete network of 2 fingers (figure 3.14). The final

1 FINGER

1 FINGER

Hotspot2

Heatsource2

HeatSource1

Hotspot1

Figure 3.14: How to obtain the network of the 2-finger structure from the com-bination of two fingers

structure has two heat sources and two hot spots, one for each finger. The left andright-side nodes can be used to properly connect the source-drain contacts. Topand bottom external nodes are left available for the connection of other fingersor to connect the poly gate termination.

Figure 3.15 displays the resistance topology of two fingers. The complexity ofthe network increases with the number of fingers, and this will not let us to finda final thermal resistance expression based on geometric parameters. Hence, thewhole structure will be simulated with a circuit simulator and the value of Rth

extracted from the results in terms of voltages and currents.

3.5 Thermal compact network for the FinFET 51

Pi2

Pi2

Pi2Pi2

Pi2

Pi2

Pi2

Pi2

Figure 3.15: Complete thermal compact network of 2 fingers. The Pi2 blocks arethe π2 structures presented in section 2.4.3

3.4.6 n fingers

The basic idea for the modeling of an arbitrary number of fingers follows the onefor the 2-finger network: the parallel between a certain number of fingers mustbe considered. Any sort of combination is allowed (e.g. a 4-finger network can beobtained with the parallel between either four 1-finger networks or two 2-fingernetworks). The n-finger network has n hotspots and n heat sources. The finalcomplete thermal network is displayed in figure 3.16. The source-drain contactscan be placed according to where we expect to have them (usually one contactevery 4 fingers). The large number of nodes on the lateral sides of the networkare mainly used for this purpose.

3.5 Thermal compact network for the FinFET

In the previous sections the basic blocks of the thermal model of a transistorhave been introduced. In this section, these blocks are combined to build up thecomplete network for both mono-finger and multi-finger transistors.

3.5.1 1-finger transistor

The complete thermal network of the 1-finger transistor is displayed in figure3.17. It consists of the thermal network of one finger, a poly gate termination,source-drain contacts and metal lines (that cannot be neglected in the typicalworking configuration of the transistor). Several nodes of the 1-finger block are


Pi2

Pi2

Pi2

Pi2

Pi2Pi2

Pi2

Pi2

Pi2

Pi2

Pi2

Pi2

Pi2Pi

2Pi

2Pi2

Pi2

Pi2

Pi2

Pi2

Pi2

Pi2

Pi2

Pi2

Figure 3.16: Complete thermal compact network of n fingers. The Pi2 blocks arethe π2 structures presented in section 2.4.3

3.5 Thermal compact network for the FinFET 53

Hotspot

Heat Source

Source Metal

Drain Metal

MetalPoly Gate

TerminationPoly Gate

Source Contact

1 FINGER Drain Contact

Figure 3.17: Complete thermal network of the 1-finger transistor

left floating, hence properly dummy resistances must be added for the implemen-tation of the network in a circuit simulator. This means that the correspondentfloating resistances are not considered in determining the temperature rise in thedevice. The ends of the metal lines are connected to ambient temperature. Forsimulation purposes, two nodes are externally available: the heat source and thehot spot.

3.5.2 2-finger transistor

The main topology of the 2-finger transistor (figure 3.18) looks very similar to thatof the 1-finger device). Further considerations must be presented for the nodesavailable as outputs. For simulation purposes, only two external nodes must beavailable: one for the heat source and one for the hotspot. Multi-finger deviceshave several inner heat sources and hotspots, one for each finger. To solve thisproblem, the total power dissipated in the device is equally distributed betweenthe two fingers, hence the external heat source must be split in two inner heatsources. The same considerations occur for the hotspot. In this case, the solutionis to provide to the outside world the average of the inner hotspot temperatures.

3.5.3 n-finger transistor

The n-finger modeling requires the generalization of the methodology employedfor the 2-finger device. As an example, figure 3.19 shows the resulting networkfor a 16-finger device. The number of internal nodes and resistors enormouslyincreases for a transistor with a large number of fingers. One restriction of thismodel is that the formula for the trapezoidal structure depicted in figure 3.9 is


Drain Metal

Source Metal

2 FINGERWin/2

Win/2

Heat Source 1

Heat Source 2

Hotspot 1

Hotspot 2

(Vhotspo1+Vhotspot2)/2

1

Win

Hotspot

Heat Source

Metal

Source Contact

Poly GateTermination

Poly Gate

Drain Contact

Figure 3.18: Complete thermal network of the 2-finger transistor

used to compute the thermal resistance between the fin end and the center ofthe source-drain pad even if no contact is present. This is a simplification thatshould be investigated in more detail.

3.6 Comparison with existing works

At the moment of the writing of this thesis, not many similar works can befound in the scientific literature. The main concerns regard the technology itself,with manufacturing issues that have still to be solved before the FinFET canbe employed in mainstream applications. Regarding the thermal model, somepapers confirm the assumptions considered in this work.

Eric Pop et al in [25] present a thermal compact model for both ultra-thinbody FETs and dual-gate devices. The whole structures are divided in simplerblocks and the thermal resistances are calculated with simple one-dimensionalformulas. The approach is similar to that carried out in this thesis, even thoughthe resulting thermal compact network is much simpler than ours and consists ofonly seven thermal resistances. Only mono-finger devices are investigated by Popet al. In addition, they consider an equivalent gate oxide thickness of 20nm dueto strong interface resistances and Montecarlo simulations which suggest a heatsource position well inside the drain. These assumptions have been consideredeven in the model presented in this thesis. Unlike our work, Pop et al investigatein detail the sub-100nm region along the ITRS roadmap.

Yu et al in [29] do not investigate multi-gate devices, but they confirm that inSOI technologies the thermal coupling between devices occurs mainly by means ofheat flow through metal and poly lines. They suggest that the heat flow throughthe buried oxide is negligible. These results agree with those presented in thisthesis. In addition, they present a typical geometry configuration for metal andpoly lines very similar to that considered in our work.

Other papers confirm some of the assumptions of the thermal model presented

3.6 Comparison with existing works 55

Met

al

Dra

in C

onta

ct

Dra

in C

onta

ct

Dra

in C

onta

ct

Dra

in C

onta

ct

Dra

in M

etal

16 F

ING

ER

Hot

spot

[1..1

6]

para

llel o

f 16

Hea

tSou

rce[

1..1

6]

Win

/16

sour

ces

1

Win

Hea

t Sou

rce

Hot

spot

Sum

(Hot

spot

[1..1

6])/

16

Poly

Gat

ePo

ly G

ate

Ter

min

atio

n

Sour

ce C

onta

ct

Sour

ce C

onta

ct

Sour

ce C

onta

ct

Sour

ce C

onta

ct

Sour

ce M

etal

Figure 3.19: Complete thermal network of the n-finger transistor. Example: n=16


in this thesis. In particular, Lee et al in [26] and Yamane et al in [27] confirm thatultra-thin oxide layers exhibit very high interface thermal resistances. However,they employ metal gates whilst our devices have polysilicon gates.

3.7 Conclusions

In this chapter a complete methodology to build a compact network for FinFETtransistors (both mono-finger and multi-finger devices) has been described. Sincethe final objective is the circuit simulation of the networks, in all the steps ofthe modeling particular attention has been paid to the feasibility of circuit im-plementation of the network. As a final result of this work, complete thermalnetworks have been developed for devices with arbitrary number of fingers. Allthese subcircuits have two external nodes (heat source and hot spot) that can beused for simulation purposes.

Chapter 4

Application to template FinFETs

4.1 Introduction

In the previous chapter a complete thermal network for mono-finger and multi-finger FinFETs has been presented. All the thermal resistances of the networkare expressed as a function of the geometry of the device. For transistors witha large number of fingers, the final network consists of up to some thousands ofnodes and resistances. It is clear that an analytical expression for the thermalresistance of the whole structure cannot be easily derived. Hence, in this chaptera different approach is carried out. The complete resistance networks presentedin the previous chapter are implemented in a circuit simulator. According tothe electro-thermal similarity (table 2.3), the circuit is fed with a current sourcerepresenting the heat generated in correspondence of the heat generation point.The resulting simulations give the current flows through the resistances and thevoltages of the internal nodes. The currents represent the internal heat flows andcan be used to evaluate which are the most important paths for heat dissipation.The voltages represent the temperature rises in the internal nodes of the transis-tor. A proper understanding of these quantities can give important hints on themain heat flow paths and temperature rises in the geometry under analysis.

In the second part of the chapter, the thermal compact model is used to per-form a sensitivity analysis. The approach is to start from the reference transistorgeometric dimensions and then to study the effects of the alteration of each rele-vant parameter separately. In the figures of these sections, the markers representthe value obtained with the reference transistor. The purpose of these analyses isto investigate the influence of the geometric dimensions on the normalized ther-mal resistance and hence on the self-heating of the devices. The results of thesestudies can be used as a guideline for future improvements of the fabrication pro-cess in order to reduce the self-heating of the devices. The simulated curves willbe used in the next chapter also to setup an analog circuit simulator environmentto let the designers work with a new transistor subcircuit with self-heating andcross-heating effects included.

57

58 Application to template FinFETs

4.2 Geometry of the reference device

In this section the geometry of the reference transistor is presented. As a usefulguideline, the design rules available for the second FinFET testchip on stage atInfineon AG are considered. A brief summary of the design rules is presented intable 4.1. In order to have results comparable with the available measurements,some geometric dimensions have been accordingly modified. The available mea-surements revealed not to be reproducible and reliable, hence the results mustbe interpreted carefully. Since the measurements concern devices with 10 fingers,particular attention will be paid to the modeling and simulation of multi-fingertransistors. Regarding this topic, the layouts of the first FinFET testchip revealthe use of one source-drain contact every four fingers.

Number Value DescriptionDR1 90nm Minimum gate lengthDR3 55nm Minimum fin widthDR4 150nm Minimum fin spacingDR5 200nm Gate edge to S/D pad edge spacingDR7 350nm Minimum active to active spacingDR13 350nm Contact sizeDR14 450nm Spacing between adjacent contactsDR15 200nm Active enclosure of contactDR17 250nm Minimum Metal 1 line widthDR20 350nm VIA size

Table 4.1: Most important design rules for the second FinFET testchip

4.2.1 1-finger reference transistor

The general geometry of the 1-finger device has been presented in the previouschapter. According to the design rules, the values displayed in table 4.2 repre-sent the reference transistor under analysis. Some of the dimensions have beenmodified in order to match the values of the measured devices, thus allowing acomparison between model and experimental results.

Concerning the dimensions displayed in table 4.2, some remarks must be high-lighted:

• The distance between the center of the gate (equal to the center of the fin)and the heat source is one fourth of the gate length, towards the drain.This asymmetry is well-documented in literature (e. g. in [25]). HoweverTCAD simulations should be performed to obtain more reliable hints forour particular geometry.

4.2 Geometry of the reference device 59

Geometric Parameter Symbol Formula ValueNumber of fingers nfinger 1Channel length lchannel 100nmGate length lgate lchannel 100nm

CenterGate-HeatSource dist. dCGHSolgate

425nm

CenterGate-HotSpot distance dCGHSp 0nmFin length lfin 650nmFin width wfin 55nmFin height hfin 88nmChannel width wchannel 2 · hfin · nfinger 176nmPoly gate thickness tpoly 100nmPoly gate wrap thickness tpoly,wrap 50nmPoly gate length lpoly 550nmPoly gate width wpoly lgate 100nmDevice z-width wz 750nmBuried oxide thickness tBOX 200nmGate oxide thickness tGOX 2nmActive areas x-width wx,active 750nmPoly pad x-width wx,polypad 750nmPoly pad z-width wz,polypad 750nmContact x-width wx,contact 350nmContact z-width wz,contact 350nmContact height hcontact 902nmPoly pad contact height hpolypad contact hcontact + hfin − tpoly 890nmONO hardmask thickness tONO 44.5nmMetal length lmetal 6µmMetal thickness tmetal 350nmMetal width wmetal 750nm

Table 4.2: Dimensions of the reference transistor

• The hotspot is located just in correspondence of the center of the gate. Thisis not the hottest node along the fin, which corresponds to the heat source.With this choice, we consider that the current is controlled by the averagetemperature along the channel. Even in this case, more indications couldbe obtained from finite elements simulations.

• The value of the fin length is that of the measured devices. In the finallayout, shorter fins can be included.

• The buried oxide thickness is that of the measured devices. The technologytarget value is slightly thinner, thus resulting in better heat dissipationthrough this layer.

• The physical gate oxide thickness for the FinFET under analysis is 2nm. Inspite of this value, in literature several references have been found ([25], [26]and [27]) which refer to strong thermal interface resistances in correspon-dence of very thin oxide layers. They propose to use an equivalent thermal


Thermal conductivity Symbol Formula Value(

Wm·K

)Silicon ksil 141Oxide kox 1.38Polysilicon kpoly 141Tungsten ktungsten 170Contact kcontact ktungsten 170Aluminum kaluminum 235Metal kmetal kaluminum 235

Table 4.3: Reference transistor material properties

gate oxide thickness of 20nm. This value proved to be not dependent onthe physical value, hence in this work the proposed value is accepted.

• In this model, the fin height equals the height of the active areas. This isthe present situation of the technology, but some papers (e.g. [28]) have re-cently highlighted the benefits of raised active areas both from an electricaland thermal point of view. Future transistors will take advantage of thisfabrication option.

• In determining the self-heating of the device, even metal lines must beconsidered. In a typical analog circuit the length of these lines depends onthe layout and cannot be determined in advance. In this work, a standardmetal length of 6µm is considered for gate, drain and source terminations,as a typical value that can occur in a typical analog circuit.

The values displayed in table 4.2 are then employed for the calculation of thethermal resistances presented in the previous chapter. In particular, for 1-fingerdevices the complete thermal network simplifies a lot, since several nodes are leftfloating and no current flows through the correspondent floating thermal resis-tances (in a circuit simulator proper dummy resistances must be added). Hence,in this case the network consists of a smaller number of nodes and resistancesand a graphical representation is possible. Figure 4.1 clearly highlights the fourmain heat flow paths: towards drain, towards gate, towards source and towardsbottom silicon.

Parameter Symbol Formula Value

Target sat. current ION,NMOS 800 µAµm

Target sat. curr., 1 fing. ION,1 finger NMOS ION,NMOS · wchannel 140.8µA

Supply voltage VDD 1.2V

Diss. power, 1 finger Pdiss ION,1 finger NMOS · VDD 169µW

Ambient temperature TAMB 25C

Table 4.4: External sources and boundary conditions for the reference transistorproblem

4.2 Geometry of the reference device 61

R_drain,trapezoid

R_drain,bottom

R_drain,contact

Drain_Metal

Poly_Gate_TerminationExternal_Poly

Gate_Metal

Drain_Side _External_Fin

R_source,bottom

R_source,contact

Source_Metal

R_gatecenter,sourcegateedge

Fin_Below_Poly_Gate

R_heatsource,draingateedge

Source_Side _External_Fin

Source_Active_Area_And_ContactDrain_Active_Area_And_Contact

R_source,trapezoid

R_hotspot,heatsource

Hotspot Gate_Center

R_gatecenter,hotspot

Heat_Source

Poly2

R_polypad,trapezoid

R_polypad,bottom

R_polypad,contact

R_g

atec

ente

r,bot

tom

R_g

atec

ente

r,sid

e1

R_g

atec

ente

r,sid

e2

R_g

atec

ente

r,top

Poly1

Figure 4.1: Complete thermal network of the reference 1-finger FinFET


Regarding the material properties, they can be found in literature articles([19], [22], [23] and [24]) and are summarized in table 4.3. The external sourcesand boundary conditions are summarized in table 4.4.

4.2.2 Multi-finger reference transistor

As for the modeling of multi-finger devices, the geometric dimensions presented intable 4.2 have been used. Some specific problems and changes must be explained.In particular, we know that in mono-finger devices the wz parameter representsthe z-width of the 1-finger structure. This width includes the z-width of thecontact (350nm), which is a limit to the reduction of the parameter. In multi-finger devices this limit is not present, since each source-drain contact relates tomore than one finger (the design rules reveal a standard structure of one contactevery four fingers). In order to consider realistic multi-finger devices, wz must bereduced according to the increased number of fingers. The design rules indicatesthe following scale factor:

• wz = 750nm for 1-finger transistors,

• wz = 375nm for 2-finger transistors,

• wz = 205nm for transistors with more than 2 fingers.

This correction cannot be neglected, otherwise cross-heating between fingerswould not be modeled correctly.

The material properties are the same as those used for the 1-finger device. Aspecial attention must be paid to the external sources. In multi-finger devicesthe current is split between the device fingers. Since the target current displayedin table 4.4 applies to 1-finger devices, the external current source in multi-fingerdevices must be n-times higher, where n is the number of fingers.

4.3 Simulation results

The geometric dimensions presented in the previous section are used to calculatethe thermal resistances of the complete network according to the formulas alreadyintroduced. The network derived in this way is then simulated with an electricalcircuit simulator in order to evaluate the temperature increase in the hotspot dueto heat dissipation under typical working conditions. In our case, the Infineonin-house circuit simulator Titan has been employed. As for the 1-finger device,the simulation gives the results summarized in table 4.5.

The overall thermal resistance results to be 182.3k KW

. It is defined by the seriesand parallel combination of the thermal resistances in which the whole geometryhas been split. A summary of the calculated resistances is presented in figure4.2. Figure 4.3 displays the same resistances, sorted based on their values. Thisfigure is useful to understand which are the main barriers and which the preferredpaths for the heat to flow inside the transistor. A first glance at the bar graphproves that the heat flow towards the buried oxide (BOX) is strongly obstructed

4.3 Simulation results 63

1.22M

1.22M1.22M

48.7k

48.7k

48.7k

48.7k

95.8k95.8k

257.7k

4.80M4.80M

47.9k47.9k

47.9k47.9k

43.3k43.3k

257.7k

1.22M

73.2k

48.6k

48.6k

96.2k

48.1k

48.1k

42.5k

256.5k

71.1k

195.0k

195.0k

1.316M

658.3k

658.3k

105.5k

105.5k

105.5k

105.5k

2.44M2.44M

101.1k

Drain_Metal


Gate_Metal

External_PolyPoly_Gate_Termination

Poly2Poly1

Gate_CenterHotspotHeat_Source


101.1k

2.40M

201.5k

201.5k

2.40M

201.5k

201.5k

2.40M

2.40M

5.86M 1.65M1.65M26.3M

0k

36.6k

36.6k

Fin_Below_Poly_Gate

Source_Metal

Drain_Active_Area_And_Contact Source_Active_Area_And_Contact

Figure 4.2: Thermal resistances (K/W) in the 1-finger FinFET


Reference transistor results Symbol Formula Value

Hotspot temperature Thotspot 55.8C

Temperature increase Thotspot,∆ Thotspot − TAMB 30.8K

Thermal resistance RthThotspot−TAMB

Pdiss182.3k K

W

Normalized thermal resistance Rth0 Rth · wchannel 0.03208m·KW

Table 4.5: Simulation results of the reference 1-finger FinFET

by the low thermal conductivity of this layer. On the contrary, the small thermalresistances for silicon and metal lines facilitates the heat flow towards the drainand source metals. As a further confirmation of these results, recent papersagree with the assumption of weak heat flow (and hence cross-coupling betweentransistors) through the buried oxide (see [29]). As a further confirmation, theheat flows across the thermal resistances are evaluated and the results displayedin figure 4.4. Figure 4.5 in turn displays the sorted heat flows. Once again,it is clear that most of the heat flows through the silicon fin and reaches themetal lines. The heat flow that passes through the gate oxide and the one thatreaches the bottom silicon are very small. To complete the investigation of the

Figure 4.3: Sorted thermal resistances of the 1-finger FinFET. The high thermalresistances between the fin and the bottom silicon inhibit the heat flow towardsthe bulk.


Fin_Below_Poly_Gate

Pin=169uW73.15u

13.20u

Gate_Center

Poly1 Poly2

Poly_Gate_TerminationExternal_Poly

Gate_Metal


Drain_Metal


Source_Active_Area_And_ContactDrain_Active_Area_And_Contact

Source_Metal

11.62u

40.78u

25.61u

5.11u

15.17u

59.95u

4.08u

55.87u

3.46u

52.40u

HotspotHeat_Source

0.48u

1.42u

0.94u

60.91u

10.99u

7.17u

5.83u

1.08u

3.81u

2.39u

33.96u

9.67u

21.33u

4.25u

12.63u

8.38u

3.40u

2.88u

49.91u

46.52u

43.63u4.88u

4.16u1.17u

5.28u5.28u

16.49u 6.68u

10.06u

95.81u 95.81u14.79u

14.79u

14.56u

2.59u

4.80u

1.34u

0.95u

1.93u 2.35u

4.33u

4.33u

Figure 4.4: Heat flows (W) in the 1-finger FinFET


Figure 4.5: Sorted heat flows in the 1-finger FinFET. The heat flow from the finto the bottom silicon is obstructed by the insulator layer.

whole thermal network, figure 4.6 displays the temperature increase of the innernode. From this figure, it is clear that the temperature increase towards the polygate contact is far less important than those for the drain and source. Figure 4.7summarizes this behaviour and highlights the strong influence of the gate oxide inblocking the heat flow through the poly gate. The biggest temperature increase istowards the drain, due to our assumption of having an asymmetrical heat source.Figure 4.8 shows the temperature profile along the fin. From these figures, itseems that the temperature rises at the top of the contacts (and then in metallines) are really low (a few degrees). This is true only in mono-finger devices,since simulations for multi-finger devices proved that much higher temperaturescan be achieved in these configurations. To this purpose, Figure 4.9 denotes thatcross-heating between transistors occurs mainly through the metal lines and thatmulti-finger devices are more affected by this phenomenon.

Finally, figure 4.10 shows the hotspot temperatures for the different fingers ofa 20-finger device. The figure proves the importance of contacts and poly linesin determining a heat flow path. Their locations correspond to the temperatureminimum points that are visible in the figure.


19.55

31.63 6.436

30.8034.31 30.80

Pin=169uW

Fin_Below_Poly_Gate

Source_Metal

Drain_Active_Area_And_Contact Source_Active_Area_And_Contact


Drain_Metal


Gate_Metal

External_PolyPoly_Gate_Termination

8.293

0.407

1.022

2.493

6.905

16.28

26.33

0.046

0.115

0.277

0.624

1.762

5.274

5.730

3.160

4.696

0.489

1.227

2.944

Poly2Poly1

Gate_CenterHotspotHeat_Source

Figure 4.6: Node temperature increments (K) in the 1-finger FinFET


Figure 4.7: Temperature profile along the three main heat flow paths in the1-finger FinFET

-600 n -400 n -200 n 0 200 n 400 n 600 nX Coordinate [m]

0

10

20

30

40

50

60

70

80

Tem

pera

ture

[°C

]

HotSpot

HeatSource

GateEdges

SourceFinEnd DrainFinEnd

Source Drain

AmbientTemperature

Figure 4.8: Temperature profile along the fin of the 1-finger FinFET


Figure 4.9: Terminal temperatures as a function of the number of fingers. Thedrain, gate and source temperatures are evaluated at the top of the contacts.The hotspot temperature is the average value of the hotspot temperatures of thefingers

0 5 10 15 20 Finger

44

45

46

47

48

Del

ta T

empe

ratu

re [K

]

source-drain contacts

poly gate line

Figure 4.10: Finger temperatures in a 20-finger device. The contacts are impor-tant heat flow paths and contribute to the lowering of the finger temperatures


4.4 Validation of the results

In the scientific literature, two main measurement methodologies are employedfor the thermal characterization of a transistor: pulsed measurements ([30], [31],[32] and [33]) and the output conductance technique ([34], [35] and [36]).

The results presented in this chapter refer to both mono-finger and multi-fingertransistors taken as reference. The geometric dimensions have been chosen ac-cording to presently available design rules and measured devices. At the momentof the writing of this thesis, the technology is not mature and even the produc-tion process is being continuously modified and improved in order to overcomeall the issues that are coming out. Hence, an extensive measurement activity hasnot been performed at the moment. In this situation, several transistors are notworking at all and even the measurement setup is improving day after day.

Measurements revealed to give not reliable and reproducible results. However,a rough validation of the simulated results can be carried out. The DC tempera-ture increases versus the power dissipated in the transistor have been obtained bymeans of pulsed measurements, following the already mentioned methodologies.In particular, the data in our possession regard 10-finger devices with gate lengthsof 250nm. An example of these pulsed measurements is displayed in figure 4.11.Some remarks are necessary:

• The thermal resistance of the transistor can be extracted from figure 4.12 asthe slope of the curves. The normalized thermal resistance is then calculatedby simply multiplying Rth and the channel width. From figure 4.12 it isclear that the slope is not fixed. In this case, our decision was to consideran average slope.

• Measurements revealed a certain dependence of the thermal resistance onthe gate voltage. In the model presented in this work, the thermal resistancedepends only on the geometry of the problem.

The extracted Rth0,10finger,measured is in the order of 0.05(

m·KW

). The main effect in

FinFET transistors is a current decrease in the order of 8% for supply voltagesof 1.2V. Further agreement with these preliminary results could be provided byfinite elements simulations. The Rth0 value derived from measurements must becompared to the results of the simulations with the thermal network of a 10-fingerdevice with a gate length of 250nm:

Rth0,10finger,simulated =∆T

Pdiss

·wchannel =63.3− 25

10 · 140 · 10−6·10·2·88·10−9 = 0.048

(m ·KW

)(4.4.1)

Even considering the major problems encountered with the pulsed measurementssetup, this result looks encouraging and can be considered a good confirmationof the correctness of the thermal compact network presented in this thesis.

4.4 Validation of the results 71

Figure 4.11: Pulsed measurements results of a 10-finger device with a gate lengthof 250nm

Figure 4.12: Temperature versus power curves extracted from pulsed measure-ments of a 10-finger device with a gate length of 250nm


4.5 Effect of changing geometric parameters

An extensive sensitivy analysis on the thermal model is now presented. Startingfrom the geometry of the reference FinFET (table 4.2), the most important pa-rameters are altered and their influence on the thermal resistance is investigated.

4.5.1 Gate length

The simulated dependence of the normalized thermal resistance Rth0 on the gatelength is displayed in figure 4.13 (the length of the fin is left unaltered). The

0 100 n 200 n 300 n 400 n 500 n 600 nGate Length [m]

0.010

0.015

0.020

0.025

0.030

0.035

0.040

Rth

0 [m

*K/W

]

Figure 4.13: Gate length dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2

maximum gate length is limited by the fin length that, for the reference transistorunder analysis, is 650nm. Even very short gate lengths are investigated, in orderto prove the expected future trends due to further scaling of the technology. Asthe gate length increases, more heat flows from the fin to the poly gate terminationthrough the gate oxide, thus determining smaller temperature increase in thedevice. The results prove a great influence of the gate length on the self-heatingin FinFETs. The preferred choice of long gates is in contrast with the need ofshort gate lengths for high current drives. This figure is very important and willbe used in the next chapter for the parameterization of Rth as a function of L.

4.5 Effect of changing geometric parameters 73

4.5.2 Hotspot and heat source position

In this work, the assumptions concerning the location of hotspot and heat sourceshave been already explained in the previous sections. More precise answers will beobtained from the TCAD simulations planned in the near future. The simulatedresults are presented in figures 4.14 and 4.15. The heat source has been placed

0 10 n 20 n 30 n 40 n 50 nGateCenter-HeatSource Distance [m]

0.029

0.030

0.031

0.032

0.033

0.034

0.035

Rth

0 [m

*K/W

]

Figure 4.14: GateCenter-HeatSource distance dependence of the normalized ther-mal resistance. The hotspot is assumed at the center of the gate. The otherparameters are reported in table 4.2

in arbitrary points between the center of the gate and the gate edge towardsdrain. A recent paper [25] presented Montecarlo simulations which suggest thatthe heat source is located at the drain outside the gate edge. The compact modelpresented in this thesis can be easily extended to simulate even this eventuality.The hotspot is placed in arbitrary points between the center of the gate and theheat source of the reference transistor, which is considered in correspondence ofone fourth of the gate towards drain.

The results are reasonable. The heat source is the hottest spot in the device,hence as soon as the hotspot moves far from it, the normalized thermal resistancedecreases. Furthermore, larger distances between the center of the gate and thehotspot lead to decreased thermal resistances, mainly due to the shorter heatflow path from the heat source to the drain termination. However, figures 4.14and 4.15 show that the position of the heat source and hotspot are not critical indetermining the value of the normalized thermal resistance.


0 5 n 10 n 15 n 20 n 25 nGateCenter-HotSpot Distance [m]

0.032

0.033

0.034

0.035

Rth

0 [m

*K/W

]

Figure 4.15: GateCenter-HotSpot distance dependence of the normalized thermalresistance. The heat source is assumed at three-fourths of the gate length, towardsthe drain. The other parameters are reported in table 4.2

4.5.3 Fin length

The apparently strange behaviour of the curve displayed in figure 4.16 can beeasily explained. Two contrary effects define the thermal resistance dependenceon the fin length. On one hand, a long fin determines a higher resistance dueto the added material that the heat flow has to pass through. On the otherhand, a long fin determines increased heat flows from the fin towards the buriedoxide layer, so that the overall resistance decreases. The combination of thesetwo effects determines the resulting curve displayed in figure 4.16. Device scalingwill degrade the effects of self-heating.

4.5.4 Fin width

Figure 4.17 shows the strong influence of the fin width in determining the heatingof the device. This issue will be much more relevant with the further device scalingplanned in the next years.

4.5.5 Fin height

As displayed in 4.18 the fin height is another technology parameter whose furtherscaling will lead to much higher temperatures inside the transistor. This suggests


0 1 µ 2 µ 3 µ 4 µ 5 µFin Length [m]

0.020

0.025

0.030

0.035

Rth

0 [m

*K/W

]

Figure 4.16: Fin length dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2

0 100 n 200 n 300 n 400 n 500 nFin Width [m]

0.000

0.010

0.020

0.030

0.040

0.050

Rth

0 [m

*K/W

]

Figure 4.17: Fin width dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2


0 100 n 200 n 300 n 400 n 500 nFin Height [m]

0.000

0.010

0.020

0.030

0.040

0.050

0.060

Rth

0 [m

*K/W

]

Figure 4.18: Fin height dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2

that self-heating will be one of the most important issues in the application offuture FinFETs.

4.5.6 Z-width and finger spacing

In the transistor thermal model presented in this thesis, the z-width parameterrepresents the width of the 1-finger structure displayed in figure 3.11. In mono-finger devices this parameter represents the width of the source-drain pads andits lower limit is the width of the source-drain contact. In multi-finger devicesthis assumption cannot be applied, since from layout examples it is clear that thebasic structure consists of one contact every four fingers. From figure 4.19, theinfluence of cross-heating between fingers (through the fin side-walls but especiallythrough the active areas) is clear in determining the overall temperature increasein multi-finger transistors. These results point out the importance of having well-separated fingers, but once again further scaling will worsen the overall thermalbehaviour of the device.

4.5.7 Buried oxide thickness

In SOI technologies the buried oxide layer is the main obstacle to heat removal. Itsvery low thermal conductivity is a big barrier for the heat flow towards the bottom


0.0 500.0 n 1.0 µ 1.5 µ 2.0 µZ-Width [m]

0.030

0.035

0.040

0.045

0.050

Rth

0 [m

*K/W

]

1 Finger Transistor10 Finger Transistor

Figure 4.19: Z-width dependence of the normalized thermal resistance. The otherparameters are reported in table 4.2

100 n 1 µBOX Thickness [m]

0.020

0.025

0.030

0.035

0.040

0.045

0.050

Rth

0 [m

*K/W

]

Figure 4.20: Buried oxide thickness dependence of the normalized thermal resis-tance. The other parameters are reported in table 4.2


silicon, hence the thickness of this layer is very important in determining the totalthermal resistance of the device. Figure 4.20 confirms these considerations. Theburied oxide thickness of the device under analysis is 200nm, while the target forthe technology is 145nm. Hence, better heat dissipation through the BOX layershould be achieved in the next testchips.

4.5.8 Gate oxide thickness

As already explained in the previous sections, while the physical gate oxide thick-ness of the device is 2nm, several papers ([25], [26] and [27]) report the necessityto consider an interface thermal resistance that is equivalent to a thermal gateoxide thickness of 20nm. This high interface resistance has been measured. Infigure 4.21 two curves are plotted. The upper relates to a 10-finger transistor,while the lower one relates to a mono-finger transistor. The figure shows thatthe choice of employing a thermal gate oxide thickness of 20nm is critical onlyfor transistors with a reduced number of fingers. In multi-finger transistors itsinfluence on the thermal resistance is less relevant.

0 50 n 100 nEquivalent Gate Oxide Thickness [m]

0.020

0.030

0.040

0.050

Rth

0 [m

*K/W

]

1 Finger Transistor10 Finger Transistor

Figure 4.21: Equivalent gate oxide thickness dependence of the normalized ther-mal resistance. The other parameters are reported in table 4.2


4.5.9 Contact width

The influence of the source-drain contacts geometry is now investigated. Theirgeometry influences the metal height itself, hence in this case we are also includingthe dependence on the metal layer. The contacts are studied with respect to theirwidth and height. The analyses of the material will be presented later on in thischapter.

The results presented in figure 4.22 show the importance of having large con-tacts, since it means that large heat flows outside the transistor. The maximumcontact width is limited by the dimensions of the active areas.

0 200 n 400 n 600 n 800 nContact X-Width and Z-Width [m]

0.025

0.030

0.035

0.040

0.045

Rth

0 [m

*K/W

]

Figure 4.22: Contact width dependence of the normalized thermal resistance.The other parameters are reported in table 4.2

4.5.10 Contact height

The source-drain contact height influences also the distance between the metalline and the buried oxide. The results displayed in figure 4.23 must be interpreted:if we consider higher contacts, the increment of the thermal resistance is mainlydue to the reduced heat flow from the metal lines to the bottom silicon.

4.5.11 Metal length

Figure 4.24 highlights a behaviour similar to that seen for the fin length depen-dence. On one hand, longer metal lines result in an increased thermal resistance


0 2 µ 4 µ 6 µ 8 µ 10 µContact Height (~Metal Height) [m]

0.031

0.032

0.033

0.034

0.035

0.036R

th0

[m*K

/W]

Figure 4.23: Contact and metal height dependence of the normalized thermalresistance. The other parameters are reported in table 4.2

1 µ 10 µ 100 µ 1 m 10 mMetal Length [m]

0.0315

0.0316

0.0317

0.0318

0.0319

0.0320

0.0321

0.0322

Rth

0 [m

*K/W

]

Figure 4.24: Metal length dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2


due to the added materials that the heat must flow through. On the other hand,longer metal lines enhance the heat flow from the metal towards the bottom ox-ide. The combined effect is that displayed in figure 4.24. Despite this particularbehaviour, it is clear that the length of metal lines is not critical in determiningthe total thermal resistance of the device. Our choice to consider a typical metallength of 6µm is not critical, since the normalized thermal resistance is almostunaffected by this parameter.

4.5.12 Metal thickness

Figure 4.25 confirms that thicker metal lines enhance the heat flow along the line.However, the overall influence is rather small.

0 1 µ 2 µ 3 µ 4 µ 5 µMetal Thickness [m]

0.0316

0.0317

0.0318

0.0319

0.0320

0.0321

0.0322

0.0323

Rth

0 [m

*K/W

]

Figure 4.25: Metal thickness dependence of the normalized thermal resistance.The other parameters are reported in table 4.2

4.5.13 Metal width

Similar to metal thickness, even metal width is not critical in determining thetemperature increase in the device. Larger lines enable not only heat flow throughthe metal, but even heat flow from the metal to the bottom silicon. Figure 4.26summarizes this behaviour.

In summary, figures 4.23, 4.24, 4.25 and 4.26 prove that the normalized ther-mal resistance Rth0 is almost unaffected by the metal lines.


0 1 µ 2 µ 3 µ 4 µ 5 µMetal Width [m]

0.0316

0.0318

0.0320

0.0322

0.0324

Rth

0 [m

*K/W

]

Figure 4.26: Metal width dependence of the normalized thermal resistance. Theother parameters are reported in table 4.2

4.5.14 Properties of the materials

Figure 4.27 investigates how the choice of the materials can affect the total ther-mal resistance of the FinFET. In this work, the most important material propertyis the thermal conductivity. In the typical FinFET, five different materials areemployed:

• fin and active areas material (silicon),

• buried oxide layer (silicon dioxide),

• gate termination (polysilicon),

• metal lines (aluminum),

• contacts (tungsten).

The thermal conductivity values for these materials can be easily found in liter-ature ([19], [22], [23] and [24]) and they are summarized in table 4.3. To studythe influence of materials, several thermal conductivity values have been consid-ered for each of the five materials. The resulting normalized thermal resistancesare displayed in figure 4.27. This figure clearly highlights the importance of thesilicon and silicon dioxide thermal conductivities. The other parameters are farless critical. These results suggest that one method to reduce the self-heating of


FinFET transistors is the development and employment of new materials withenhanced thermal conductivities.

0.01 0.10 1.00 10.00 100.00Actual Thermal Conductivity / Real Thermal Conductivity

0.000

0.020

0.040

0.060

0.080

Rth

0 [m

*K/W

]

SiliconPoly SiliconOxideContactMetal

Figure 4.27: Materials dependence of the normalized thermal resistance. Thethermal conductivity of each material has been modified separately. The otherparameters are reported in table 4.2

4.5.15 Number of fingers

With the fixed design rules in our possession, there is a direct correspondencebetween the number of fingers and the channel width (we deal with double-gatedevices with a fixed height of 88nm controlled by the fabrication process). Hence,figure 4.28 represents even the normalized thermal resistance dependence on thechannel width. It will be used in the next chapter for the parameterization of thethermal resistance with respect to the channel width.

In figure 4.28 two curves are plotted. In the lower one, the only parameterthat has been modified between the several simulations is the number of fingers.The z-width parameter of the 1-finger structure presented in the previous chapteris left unaltered as 750nm, correspondent to the design rule value for mono-fingerdevices. This is not the most realistic situation, since in multi-finger transistorseven the z-width must be properly changed according to the design rules. Thefollowing rules are applied in the upper curve:

• for 1-finger transistors: wz,1 = 750nm;

• for 2-finger transistors: wz,2 = 375nm;


0 50 100Number of Fingers

0.030

0.035

0.040

0.045

0.050

0.055

0.060

Rth

0 [m

*K/W

]

Z-Width Not CorrectedZ-Width Properly Corrected

Figure 4.28: Number of fingers dependence of the normalized thermal resistance.The other parameters are reported in table 4.2. In the upper curve, the fingerspacing is modified according to the design rules. In the lower curve, only thenumber of fingers is altered

• for transistors with more than 2 fingers: wz,n≥3 = 205nm.

This choice affects the distance between the fingers in multi-finger devices. If wedo not consider this correction, the cross-heating between fingers would be un-derestimated. Figure 4.28 clearly shows the importance of cross-heating betweenfingers in determining the overall temperature increase in correspondence of thehotspot.

Some remarks must be added here:

• In multi-finger transistors the device temperature is assumed to be theaverage fin temperature.

• In order to have realistic results, the power used to feed the thermal net-works has been accordingly changed as a function of the number of fingers

4.6 Conclusions 85

in the following way:

Pin = nfinger · Ids,target,1 finger · Vds,analog applications =

= nfinger · Ids,target · ngate · hfin · Vds,analog appications =

= nfinger · 800

(µA

µm

)· 2 · 88 (nm) · 1.2 (V) =

= 140.8 (µA) · 1.2 (V) · nfinger

= 169 (µW) · nfinger

(4.5.1)

This is exactly the case in which all the fingers have the same dimensionsand it is not completely true in our devices, where the two external fins arealways thinner due to fabrication constraints.

4.5.16 Other parameters

Other parameters such as the ONO hard mask thickness, the poly line length,the poly line thickness, etc., resulted of far less importance in determining theoverall self-heating of the device. Hence their plots are not included in this work.

4.5.17 General scaling of the geometry

In the results presented in the previous sections, only one parameter at a time hasbeen changed, whilst the other dimensions have been left unaltered. In order tounderstand the effect of an overall device scaling, a further simulation with all thedimensions divided by two has been performed. The simulated normalized ther-mal resistance is 0.0843, almost three times the value obtained with the presentdesign rules. This result shows that the temperature increments in FinFETs willbe much higher as the device feature continues to scale down.

4.6 Conclusions

In this chapter, the thermal network derived in this thesis has been applied toa typical transistor whose geometric dimensions have been chosen according tothe design rules for the second FinFET testchip at Infineon. The results of thesimulation have been compared to the pulsed measurements in our possession,showing a good agreement between simulated and measured data. In the nearfuture, more reliable measurements for a wide range of devices and geometricdimensions are expected, which will permit a more precise validation of the model.

In the second part of this chapter a complete and extensive sensitivity analysishas been presented. The thermal compact network has been fed with an externalheat source in a circuit simulator and the results evaluated as a function of thegeometry of the device. The purpose of this analysis is to understand whether ornot the network is able to describe a realistic behaviour of the device and to giveinteresting hints concerning the perspective of the further technology scaling,under the self-heating point of view. The results confirm that self-heating inFinFETs will be a great concern as the feature size continues to scale down.

Chapter 5

Temperature-Aware AnalogCircuit Simulation

5.1 Introduction

In the previous chapters a thermal network for mono-finger and multi-finger Fin-FETs has been proposed. It has been applied to reference transistors whosedimensions have been derived from the design rules of the FinFET testchip de-scribed in section 4.2. The final purpose of this work is to deliver a circuitsimulation environment to analog designers, capable to handle self-heating andcross-heating effects between devices. The network presented in the previouschapters is not suitable to be easily included in a subcircuit, its main drawbackbeing that the thermal network topology depends on the number of fingers andthat the thermal network is not easily scalable. Hence, the only way to directlyuse that network would be to have a different subcircuit for each number of fin-gers. From the design rules in our possession, transistors with arbitrary evennumber of fingers can be manufactured. Thus, this methodology is not verypractical. In this chapter a different approach will be pursued and a completelyscalable subcircuit will be derived, which can be easily implemented in any circuitsimulator.

5.2 Brief overview of the Titan simulator

Titan is the Infineon in-house network analysis program for nonlinear electricalcircuits. Regarding the temperature analysis, Titan provides the option to sim-ulate circuits at various fixed global temperatures, which affects the behaviourof the instantiated elements. In addition, it offers an electro-thermal couplingmode for DC and transient simulations. Taking advantage of the well-knownelectro-thermal analogy (table 2.3), a thermal network consisting of electricalcomponents can be used to calculate the voltage representing the temperatureof the device. This voltage can be fed back to the instantiated component, thusaffecting its electrical behaviour.

The objective of this work is to provide a new transistor model representingthe modern FinFETs taking into account self-heating effects. Inside the Titan

87

88 Temperature-Aware Analog Circuit Simulation

libraries, two transistor models representing the electrical part of the device aresuitable to be employed as the starting point of our electro-thermal model: theBSIM model version 4 (BSIM4) and the BSIM Fully Depleted model version 2(BSIMFD2). Both of them have advantages and drawbacks for the employmentin our electro-thermal analysis. In order to understand the reasons of our choice,they will be briefly presented in the following paragraphs.

5.2.1 BSIM4 model

BSIM4 is the latest evolution of a family of transistor models developed at theUniversity of Berkeley (documentation and source code are freely available on[37]). The Berkeley Short-channel IGFET Model version 4 (BSIM4) has beenintroduced in 2000 for the accurate simulation of sub-micron bulk CMOS tech-nology. BSIM4 still considers the operating regions described in MOS level 3, butprovides perfect continuity between these regions. Up to 300 parameters concurin defining the device behaviour.

BSIM4 includes neither self-heating modeling nor any kind of electro-thermalimplementation. In spite of this, the effects of the static temperature on the deviceparameters are quite accurately modeled. The main parameters influenced by thetemperature are the threshold voltage and the mobility, even though other lessimportant dependencies must be considered.

5.2.1.1 Temperature dependence of the mobility

A higher temperature leads to a reduced mobility, so that the main effect is adrain current lowering. Among the several effects of the temperature on thedevice behaviour, this is the most important one, since it determines the well-known current lowering effect in MOS transistors due to high temperatures.

In BSIM4, there are four temperature dependent parameters affecting the mo-bility: U0 (low-field mobility), UA (coefficient of first-order mobility degradationdue to vertical field), UB (coefficient of second-order mobility degradation dueto vertical field) and UC (coefficient of mobility degradation due to body-biaseffect). UA, UB and UC have a temperature dependence defined by UA1, UB1 andUC1 parameters. The particular relations depend on the value of the TEMPMODparameter, but since their effect is far less important than that of U0 they can beconsidered negligible. Thus, the most important relation describing the depen-dence of mobility on temperature is assumed to be that of U0, which does notdepend on TEMPMOD and it is modeled with the following formula:

U0(T ) = U0(Tnom)

(T

Tnom

)UTE

(5.2.1)

where Tnom is the temperature at which parameters are extracted and UTE is themobility temperature exponent. Typical values of UTE are −1.5 ÷ −2 so thatthe general effect of a temperature increase is a reduced mobility and hence adecreased current. Figure 5.1 displays this behaviour and highlights that UTEparameter is very important in determining the temperature dependence of mo-bility.

5.2 Brief overview of the Titan simulator 89

1 1.2 1.4 1.6 1.8 2T/Tnom

0

0.2

0.4

0.6

0.8

1

U0(

T)/U

0(Tn

om)

UTE=-1.0UTE=-1.5UTE=-2.0UTE=-2.5

Figure 5.1: Temperature dependence of the mobility in BSIM4

5.2.1.2 Temperature dependence of the threshold voltage

Threshold voltage decreases when temperature increases, thus leading to higherdrain currents. In spite of this, the opposite effect due to mobility dependenceon temperature results in an overall current decrease. This is one of the mostimportant self-heating effects which may be a concern in analog design.

In BSIM4, the temperature dependence of the threshold voltage is modeledwith the following formula

Vth(T ) = Vth(Tnom) +

(KT1 +

KT1L

Leff

+ KT2Vbseff

)·(

T

Tnom

− 1

)(5.2.2)

where KT1 is the temperature coefficient for threshold voltage, KT1L is the channellength dependence of the temperature coefficient for threshold voltage, KT2 is thebody-bias coefficient of threshold voltage temperature effect, Leff is the effectivechannel length and Vbseff is the effective bulk-source voltage. If we consider typicalvalues for the parameters (KT1 = −0.11(V), KT1L = 0(V·m), KT2 = 0.022,Leff = 100(nm) and Vbseff = 0(V)), the resulting curve is displayed in figure 5.2.

5.2.1.3 Other temperature dependent quantities

Even though the most important parameters are the mobility and threshold volt-age, other secondary temperature dependent quantities are modeled in BSIM4.They can be summarized as follows:


1 1.2 1.4 1.6 1.8 2T/Tnom

-0.125

-0.1

-0.075

-0.05

-0.025

0

Vth

(T)-

Vth

(Tno

m) [

V]

Vth(T)-Vth(Tnom)=(Kt1+Kt1l/Leff+Kt2*Vbseff)*(T/Tnom-1)Kt1=-0.11(V), Kt1l=0(V*m), Kt2=0.022, Leff=100(nm), Vbseff=0(V)

Figure 5.2: Temperature dependence of the threshold voltage in BSIM4

• saturation velocity Vsat, which involves the parameter AT

• resistance of the lightly doped portion of the drain, which involves theparameter PRT

• IV of the junction diode, which involves the parameters XTIS and XTID

• CV of the junction diode, which involves the parameters TCJ, TCJSW, TCJSWG,TPB, TPBSW and TPBSWG

• energy-band gap of silicon Eg

• intrinsic carrier concentration of silicon ni

Since they are less important in affecting the drain current, their curves are notinvestigated in more detail in this thesis.

5.2.2 BSIMFD2 model

BSIMFD2 model is part of BSIMSOI family [38] from Berkeley University ofCalifornia. BSIMSOI is an international standard transistor model which sharesits core equations with the well-tested BSIM3v3 model. In addition, it includesseveral enhanced features in order to better match the circuit behaviour of SOItechnologies [39]:

• floating-body model

5.3 Analog simulation environment for FinFETs in Titan 91

• self-heating model (in DC, AC and transient simulations)

• body-contact model

These advanced features unfortunately cause long computation time and conver-gence slowness, due for example to electro-thermal interaction.

Unlike BSIM4 model, BSIMSOI implements the auxiliary thermal subcircuitin its source code. Its topology is quite simple and consists of the simple par-allel between a thermal resistance and a thermal capacitance whose values arecalculated as follows:

Rth =Rth0

W ′eff + Wth0

(5.2.3)

Cth = Cth0 (W ′eff + Wth0) (5.2.4)

where Rth0 is the normalized thermal resistance, Cth0 is the normalized thermalcapacitance, Wth0 is the minimum width for thermal resistance calculation. Theresulting model can be used in both DC, AC and transient simulations withself-heating effects taken into account.

In particular, BSIMFD is the Fully-Depleted (FD) mode of BSIMSOI. LikeBSIMSOI, it includes the electro-thermal subcircuit representing self-heating inmodern SOI technologies. Even though the thermal subcircuit topology is thesame as in BSIMSOI, the formulas for the calculation of thermal resistance andthermal capacitance are slightly different:

Rth =Rth0

√Tbox

Tsi

Weff

(5.2.5)

Cth = Cth0Weff (5.2.6)

where Tbox is the thickness of the buried oxide, Tsi is the thickness of the topsilicon and Weff is the effective channel width.

5.3 Analog simulation environment for FinFETs

in Titan

For the implementation of the FinFET subcircuits in Titan, several strategicaldecisions have to be taken. The most important idea is that a completely scalablemodel is needed, with respect to the channel length and channel width (and thennumber of fingers, since the height of the fin cannot be modified with the presenttransistor manufacturing flow and then wchannel = 2 · hfin · nfin). The geometricdimensions can be considered fixed, since they have been derived from designrules presently available. As already written before, this approach does not allowus to implement the thermal network presented in the previous chapters directlyin Titan because the network topology itself depends on the number of fingers.The use of a different subcircuit for each possible number of fingers is not themost elegant solution. In this section, the results obtained from the simulationof the thermal network presented in the previous chapters will be used for thederivation of completely scalable Titan subcircuits.


5.3.1 Circuit modeling strategy

5.3.1.1 Electrical model

The first important choice regards the model representing the electrical part ofthe component. At the moment of the writing of this thesis, neither BSIM4 norBSIMFD2 model were available for the FinFET transistor under analysis. Someideas for a parameter extraction methodology for these models can be foundin their respective user’s manuals [37] [38], but a complete strategy cannot bepursued in the time frame of this thesis. Then, a compromise is the modificationof an existing model for a mature technology of Infineon, with a special emphasison the FinFET target values in terms of saturation current. This approach failsin representing several peculiarities of the new multi-gate technologies, but aFinFET model will soon be available and it will be very easy to include it in thesubcircuits developed during this thesis.

Regarding the choice of the transistor model, both BSIM4 and BSIMFD2 havetheir advantages and drawbacks, mainly derived from their particular implemen-tation in Titan. In particular, BSIM4 does not allow to perform AC simulationsin the electro-thermal coupling mode, since the problem depicted in figure 5.3occurs: the thermal feedback from the thermal network to the electrical networkis not considered in AC analyses when a BSIM4 model is employed. Furthermore,

ELECTRICALNETWORK Temperature

Power

AC simulations

NETWORK

THERMALNETWORK

ELECTRICALNETWORK Temperature

Power

DC and TRANSIENT simulations

THERMAL

Figure 5.3: Electro-thermal malfunctioning in Titan AC simulations when aBSIM4 model is employed

BSIM4 is a bulk CMOS model, then several effects typical of SOI cannot be prop-erly modeled. In spite of this, its advantage consists in leaving the possibility toimplement externally the thermal part of the component, which gives great flex-ibility in implementing the thermal model. On the other hand, BSIMFD2 canbetter represent the typical behaviour of fully depleted SOI devices, but its inter-nal modeling of the thermal subnetwork and the absence of an external thermal


node does not allow proper modeling of cross-heating between transistors. Thisis the reason that forced us to employ the BSIM4 model: as demonstrated inthe previous chapters, in FinFETs the main heat flow path is through the metallines, since the very low thermal conductivity of the buried oxide layer does notallow a proper heat dissipation through the substrate. This means that cross-heating must be properly modeled for the correct estimation of analog designsperformance. The impossibility to perform AC simulations can be an importantlimiting factor of this solution, especially if this kind of simulation is required forthe analog circuits under analysis. In case of simple simulations, a temporarysolution can be employed: AC analysis can be obtained with transient simula-tions with small sine-wave input signals in order to reduce the nonlinearities ofthe device. A final solution can be delivered only by Titan developers, since thisTitan malfunctioning can be corrected only with the modification of the sourcecode itself.

5.3.1.2 Subcircuits topology

The final objective of this thesis is to deliver FinFET subcircuits suitable to beemployed in analog designs. In order to give to analog designers a certain level offlexibility, several topologies of different complexities have been considered. Theyare shortly presented in the following sections.

5.3.1.2.1 FinFET subcircuit without self-heating effects. In principle,in low-power circuits the transistors work at low voltages and/or low currents.In these situations, self-heating can be considered negligible, so that the pos-sibility to employ simplified FinFET subcircuits without self-heating modelingmust be considered. Furthermore, the electro-thermal interaction requires longercomputation time and convergence problems may emerge. For this purpose, asubcircuit without thermal network is proposed (figure 5.4). Three nodes areexternally available: drain, gate and source. In FinFETs the bulk is floating and

Source

Drain

GateBulkBSIM43

Figure 5.4: FinFET subcircuit without self-heating effects


this is the cause of the well-documented floating-body effects [3]. In this work,the bulk and source nodes are connected, since Titan does not allow a floatingnode for this element. Hence, some of the typical behaviour of SOI technologiesare not properly modeled. BSIMSOI models can provide a solution to these prob-lems. With this topology, the device is always considered at the global ambienttemperature, which affects the calculation of the parameters of the BSIM4 model,but no electro-thermal interaction and then no temperature increments due todissipated power are modeled.

5.3.1.2.2 FinFET subcircuit with self-heating effects: classical ver-sion. Figure 5.5 depicts the classical way to model the electro-thermal interac-tion in circuit simulators [40]. The overall thermal behaviour of the device can berepresented with a simple equivalent subcircuit, that is a single impedance for ACanalysis that reduces to a single resistance for DC analysis. The electro-thermalanalogy is here employed to build the thermal network as a simple parallel be-tween a thermal resistance and a thermal capacitance, where:

P = IdVds =T − T0

Rth

+ Cthd(T − T0)

dt(5.3.1)

The thermal capacitance affects also the transient simulations. The thermalsubcircuit is fed with a current source representing the dissipated power in thetransistor, modeled with the product between the drain-source current and drain-source voltage. The calculated temperature rise is fed back to the electricalpart of the device, thus affecting its parameters, its current and voltage andthen its dissipated power. The result is the so-called electro-thermal interaction,whose convergence determines the steady-state operating point of the device withself-heating effects taken into account. The temperature node is left externallyavailable for the sensing of the temperature of the device and the modeling ofcross-heating between transistors. Since the power dissipated in the transistorcontrols the temperature increment compared to the ambient temperature, aproper internal voltage source representing the ambient temperature must be

Ambient Temperature

Temperature

Rth Cth

Power

Temperature

Bulk

Source

Drain

Gate BSIM43

Figure 5.5: FinFET subcircuit with self-heating effects: classical version


employed. The most important drawbacks of this implementation are increasedcomputation times (due to the electro-thermal iterations), possible convergenceproblems (especially with the employment of BSIM4 for the electrical part ofthe network), self-heating effects represented by a single time constant and thepresence of a single external node representing the temperature of the wholedevice, which complicates the modeling of cross-heating between devices.

5.3.1.2.3 FinFET subcircuit with self-heating effects: enhanced ver-sion. The topology presented in the previous section is the classical way em-ployed for the modeling of self-heating with one dominant time constant. Inthis thesis, a new topology is proposed (figure 5.6). In FinFETs, the heat flowgenerated in correspondence of the heat source follows four main paths: towardsbottom silicon, towards drain metal, towards source metal and towards gate.Since the heat flow towards bottom is obstructed by the low thermal conductiv-ity of the buried oxide layer, heat mainly flows through contacts to metal lines.This behaviour has been demonstrated in the previous chapters of this thesis. Inorder to properly model this behaviour, an enhanced topology is here proposed:the injected power can flow through four main heat flow paths. Three thermalnodes are externally available (thermal drain, thermal gate and thermal source)which can be used to model cross-heating between adjacent transistors with theemployment of thermal networks for the metal lines. The extraction of the ther-mal resistances of the proposed thermal network is presented in the followingsections.

Thermal Source

GateBulkBSIM43

Temperature

Thermal DrainDrain

Thermal Gate

Rth,source

Rth,gate

Rth,bott

Rth,drain

Ambient Temperature

Cth

Power

Temperature

Source

Figure 5.6: FinFET subcircuit with self-heating effects: enhanced version

5.3.2 Implementation of the FinFET subcircuits in Titan

5.3.2.1 Electrical model extraction

At the moment of the writing of this thesis, a BSIM4 model for the FinFET is notyet available, furthermore a complete extraction procedure (as the one proposed


in BSIM4 user’s manual [37]) cannot be carried out in the time frame of thiswork, even though it is presently under development. As a temporary solution,an empirical approach has been taken: a BSIM4 model already available for amature Infineon technology has been employed, with the proper modificationof some of its parameters in order to hit the target saturation current for theFinFET technology. The complete procedure comprises the alteration of thefollowing parameter:

• Geometric parameters such as the electrical equivalent gate oxide thicknessTOXE (m) and the physical equivalent gate oxide thickness TOXP (m)have been modified with the values for the FinFET technology

• The source-bottom junction capacitance per unit area at zero bias CJS(F/m2) and the drain/bottom junction capacitance per unit area at zerobias CJD (F/m2) have been switched off (value=0), since the devices arefully depleted

• The threshold voltage for long-channels at Vbs = 0, VTH0 (V), has beenset to the threshold voltage target for the FinFET

• The low-field mobility U0 (m2/V·s) has been modified in order to hit thetarget for the saturation drain current of the FinFET technology

• The mobility temperature exponent UTE has been corrected in order toobtain a saturation current decrease of 8% due to temperature effects whenthe transistor operates at VGS = 1.2V and VDS = 1.2V, according to themeasurements presented in section 4.4 (∆T ≈ 30C).

This methodology has been applied to both N-channel and P-channel devices.Figure 5.7 displays the output characteristics simulated with the derived BSIM4model, for various values of global temperature and gate voltage.

5.3.2.2 Thermal resistances extraction

The topologies of the subcircuits representing a FinFET device have already beendescribed in section 5.3.1.2. The parameterization of the thermal resistances asa function of the channel length and channel width is now presented. Startingfrom the simulation of the thermal network of the FinFET described in chapter3, completely scalable models are derived, suitable to be easily implemented in acircuit simulator.

5.3.2.2.1 FinFET subcircuit without self-heating effects. The topologyof the subcircuit without self-heating effects is displayed in figure 5.4. Since theelectro-thermal iterations of the subcircuits 5.5 and 5.6 are affected by longercomputation time and convergence issues, analog designers can employ this modelwhen self-heating can be considered negligible, such as in low-power applications.

This model does not require any thermal resistance extraction and can bedirectly implemented into a circuit simulator. The Titan subcircuit for the N-channel device is hereunder reported:


T Vgs=0.05

T

Id [A]

Vds [V]

65

85

105

T [C]

−155

2545

T

PMOS

NMOS

Vgs=0.6

Vgs=1.2

Vsg=0.05

Vsg=0.6

Vsg=1.2

Figure 5.7: Output characteristics of N-channel and P-channel transistors ob-tained with the modified BSIM4 model (nfinger = 1, L = 100nm)

001 ** Nfinfet without Self-Heating

002

003 .subckt nfinfet_nosh (d g s)

004 + lgate = 100e-9

005 + nfinger = 1

006

007 v_dummy d d1 dc 0

008

009 mnmos d1 g s s nfinfetmodel

010 + l = ’lgate’

011 + w = ’nfinger*2*88e-9’

012

013 .ends nfinfet_nosh

The dummy voltage source Vdummy is employed for the drain current measurementof the device. The internal MOS element is the BSIM4 transistor, with the bulknode connected to the source node since in Titan it cannot be left floating (as itshould be in FinFETs).

5.3.2.2.2 FinFET subcircuit with self-heating effects: classical ver-sion. The topology of the subcircuit with the classical implementation of self-


heating and cross-heating effects is displayed in figure 5.5. The thermal resistanceand the thermal capacitance must be extracted and parameterized as a functionof the channel length and the channel width, starting from the simulation of thethermal compact network. The following procedure has been carried out:

• The thermal resistance dependence on the channel length for a fixed valueof channel width (1 finger) has been calculated from the simulation of thethermal compact network. With the employment of a simple curve-fit pro-gram, the results have then been parameterized as a function of the channellength in the following way (all the measures are expressed in meters):

Rth(W, L) = Rth(W = 176 · 10−9, L) =0.06730

L + 276.8 · 10−9(5.3.2)

The resulting curve is displayed in figure 5.8.

100 n 200 n 300 n 400 n 500 n 600 nchannel length L [m]

100000

150000

200000

250000

Rth

(W=1

76nm

,L) [

K/W

]

Figure 5.8: Curve fit of the thermal resistance versus the channel length L, for afixed value of channel width W = 176nm

• The procedure explained in the previous point has then been employed forthe extraction of the dependence of the thermal resistance on the channelwidth (number of fingers) for a fixed value of channel length:

Rth(W, L) = Rth(W, L = 100 · 10−9) =0.04446

W + 69.5 · 10−9(5.3.3)

The resulting curve is displayed in figure 5.9.

• The thermal resistance dependence on arbitrary channel lengths and widths


0 5 µ 10 µ 15 µ 20 µ 25 µchannel width W [m]

0

50000

100000

150000

200000

Rth

(W,L

=100

nm) [

K/W

]

Figure 5.9: Curve fit of the thermal resistance versus the channel width W, for afixed value of channel length L = 100nm

has been derived in the following way:

Rth(W, L) =Rth(W, L) ·Rth(W, L)

Rth(W, L)

=Rth(W = 176 · 10−9, L) ·Rth(W, L = 100 · 10−9)

Rth(W = 176 · 10−9, L = 100 · 10−9)

= 5.56 · 10−6

(0.04446

W + 69.5 · 10−9

) (0.06730

L + 276.8 · 10−9

) (5.3.4)

The equation (5.3.4) represents a good extension of the curves (5.3.2) and(5.3.3) to a surface. In fact, if we evaluate (5.3.4) in W = W we have

Rth(W, L)|W=W =Rth(W, L) ·Rth(W, L)

Rth(W, L)

∣∣∣∣W=W

=

=Rth(W, L) ·Rth(W, L)

Rth(W, L)= Rth(W, L)

(5.3.5)

and similarly

Rth(W, L)|L=L =Rth(W, L) ·Rth(W, L)

Rth(W, L)

∣∣∣∣L=L

=

=Rth(W, L) ·Rth(W, L)

Rth(W, L)= Rth(W, L)

(5.3.6)

Since Rth(W, L) is never 0 in our cases, the equation (5.3.4) can be consid-ered a good parameterization of the thermal resistance versus the channel


width and the channel length. Figure 5.10 shows the plot of the curvederived with this procedure.

40000 60000 80000

100000 120000 140000

Rth(W=176nm,L) 160000 180000

Rth

L: Channel Length W: Channel Width

Rth(W,L=100nm)

5.56e−6*0.04446/(x+69.5e−9)*0.06730/(y+276.8e−9)

20000 0

6e−07 5e−07

4e−07 3e−07

2e−07 1e−07

2e−05 1.5e−05

1e−05 5e−06

Figure 5.10: Transistor subcircuit, classical topology: thermal resistance as afunction of channel width (number of fingers) and channel length, as obtainedfrom the model of equation (5.3.4)

• The value of the thermal capacitance is obtained from the evaluation of thetime constants associated to the thermal effects as follows:

Cth(W, L) =τ th

Rth(W, L)(5.3.7)

From measurements, the typical τ th value is in the order of 100ns for SOItechnologies [30], with arbitrary channel lengths and channel widths.

These formulas can be directly employed in a circuit simulator for the calcu-lation of the thermal resistance and thermal capacitance. The implementation inTitan is the following:

001 ** Nfinfet with Self-Heating, Classical Version

002

003 .subckt nfinfet_shclass (d g s temp_node)

004 + lgate = 100e-9

005 + nfinger = 1

006 + ambienttemperature = 25

007

008 mnmos d_ii g s s nfinfetmodel

009 + l = ’lgate’

010 + w = ’nfinger*2*88e-9’


011 + temp = v(temp_node)

012

013 v_dummydrain d_i d_ii dc 0

014

015 r_sense d d_i 1e-3

016

017 g_powersource temp_node_i temp_ambient_node

018 + poly(2) d_i s d d_i 0 0 0 0 ’-1e3’

019

020 v_dummypowersource temp_node_i temp_node dc 0

021

022 Rth temp_node temp_ambient_node_i

023 ’5.56e-6*(0.04446/(nfinger*2*88e-9+69.5e-9))*

024 (0.06730/(lgate+276.8e-9))’

025

026 v_dummyrth temp_ambient_node_i temp_ambient_node dc 0

027

028 Cth temp_node temp_ambient_node

029 ’100e-9/(5.56e-6*(0.04446/(nfinger*2*88e-9+69.5e-9))*

030 (0.06730/(lgate+276.8e-9)))’

031

032 v_temp_ambient temp_ambient_node 0 ambienttemperature

033

034 .ends nfinfet_shclass

The sense resistance Rsense is used to translate the drain current in a voltage,since Titan implements current sources controlled by the product between twovoltages but there is no option to consider the product between a voltage anda current. Several dummy voltages have been inserted for debugging purposes,since they can be employed as current probes.

5.3.2.2.3 FinFET subcircuit with self-heating effects: enhanced ver-sion. For the modeling of the topology displayed in figure 5.6 four resistancesmust be extracted. They have been called Rth,drain, Rth,gate, Rth,source and Rth,bottom,and represent the heat flowing in these four directions. In principle, their extrac-tion and parameterization as a function of the channel length and width have beencarried out with the methodology introduced in the previous section. Metal linesof 6µm have been employed and the following formulas applied to the simulationresults:

Rth,drain =Ttempnode − Ttermal drain

Pthermal drain

(5.3.8)

Rth,gate =Ttempnode − Ttermal gate

Pthermal gate

(5.3.9)

Rth,source =Ttempnode − Ttermal source

Pthermal source

(5.3.10)


Rth,bottom =Ttempnode − Tambient

Pin − Pthermal drain − Pthermal gate − Pthermal source

(5.3.11)

where Ttermal drain, Ttermal gate and Ttermal source are the absolute temperatures at thetop of the contacts and Pthermal drain, Pthermal gate, Pthermal source are the heats thatflow from the contacts to the metals. According to the methodology introducedin the previous section, these quantities have been evaluated:

• as a function of the channel length, for a fixed value of channel width (onefinger)

• as a function of the channel width (number of fingers), for a fixed value ofchannel length

These curves have then been extended to a two-dimensional surface with theapproach already introduced in equation 5.3.4. The derived parameterizationsare the following:

Rth,drain(W, L) = 1.4058 · 10−6

(0.2475

W + 171.9 · 10−9

) (832315− 1.2097 · 1012 · L

)(5.3.12)

Rth,gate(W, L) = 1.2528 · 10−7

(1593042 +

2.023 · 10−7

W 2

) (1796543 +

0.6058

L

)(5.3.13)

Rth,source(W, L) = 1.1429 · 10−6

(0.2936

W + 165.6 · 10−9

) (908224− 1.778 · 1011 · L

)(5.3.14)

Rth,bottom(W, L) = 2.9581 · 10−6

(0.06781

W + 23.6 · 10−9

) (0.10414

L + 209.5 · 10−9

)(5.3.15)

with L ≤ 650nm. The curves represented by equations (5.3.12), (5.3.13), (5.3.14)and (5.3.15) are displayed in figures 5.11, 5.12, 5.13 and 5.14.

The thermal capacitance is extracted, as in the previous section, consideringa thermal time constant of 100ns [30] in the following way:

Cth =τ th

Rth,drain ‖ Rth,gate ‖ Rth,source ‖ Rth,bottom

(5.3.16)


200000

300000

400000

500000

600000

700000 Rthd(W=176nm,L)

800000

Rthd

L: Channel Length W: Channel Width

Rthd(W,L=100nm)

1e−07

100000

0

6e−07 5e−07

4e−07 3e−07

2e−07

2e−05 1.5e−05

1e−05 5e−06

1.4058e−6*0.2475/(x+171.92e−9)*(832315−1.20969e12*y)

Figure 5.11: Transistor subcircuit, enhanced topology: drain thermal resistanceas a function of channel width (number of fingers) and channel length, as obtainedfrom the model of equation (5.3.8)

2e+06

3e+06

4e+06

5e+06

6e+06

7e+06

W: Channel Width

8e+06

Rthg

Rthg(W,L=100nm)

Rthg(W=176nm,L)

L: Channel Length

1e−07

1e+06

0

6e−07 5e−07

4e−07 3e−07

2e−07

2e−05 1.5e−05

1e−05 5e−06

1.2528e−7*(1593042+2.0227e−7/x/x)*(1786543+0.60576/y)

Figure 5.12: Transistor subcircuit, enhanced topology: gate thermal resistance asa function of channel width (number of fingers) and channel length, as obtainedfrom the model of equation (5.3.9)


200000 300000 400000 500000 600000 700000

W: Channel Width

800000 900000

Rths

Rths(W,L=100nm)

Rths(W=176nm,L)

L: Channel Length

1.1429e−6*0.29363/(x+165.55e−9)*(908224−1.778e11*y)

100000 0

6e−07 5e−07

4e−07 3e−07

2e−07 1e−07

2e−05 1.5e−05

1e−05 5e−06

Figure 5.13: Transistor subcircuit, enhanced topology: source thermal resistanceas a function of channel width (number of fingers) and channel length, as obtainedfrom the model of equation (5.3.10)

50000

100000

150000

200000

250000

300000

W: Channel Width

350000

Rthbott

Rthbott(W,L=100nm)

Rthbott(W=176nm,L)

L: Channel Length

1e−07

0

6e−07 5e−07

4e−07 3e−07

2e−07

2e−05 1.5e−05

1e−05 5e−06

2.9581e−6*0.067806/(x+23.61e−9)*0.10414/(y+209.54e−9)

Figure 5.14: Transistor subcircuit, enhanced topology: bottom thermal resistanceas a function of channel width (number of fingers) and channel length, as obtainedfrom the model of equation (5.3.11)


The Titan subcircuit implementing this procedure is the following:

001 ** Nfinfet with Self-Heating, Enhanced Version

002

003 .subckt nfinfet_shenh (d g s td tg ts)

004 + lgate = 100e-9

005 + nfinger = 1

006 + ambienttemperature = 25

007

008 mnmos d_ii g s s nfinfetmodel

009 + l = ’lgate’

010 + w = ’nfinger*2*88e-9’

011 + temp = v(temp_node)

012

013 v_dummydrain d_i d_ii dc 0

014

015 r_sense d d_i 1e-3

016

017 g_powersource temp_node_i temp_ambient_node

018 + poly(2) d_i s d d_i 0 0 0 0 ’-1e3’

019

020 v_dummypowersource temp_node_i temp_node dc 0

021

022 v_temp_ambient temp_ambient_node 0 ambienttemperature

023

024 Rthbott temp_node temp_ambient_node_i

025 ’2.9581e-6*0.067806/(nfinger*2*88e-9+23.61e-9)

026 *0.10414/(lgate+209.54e-9)’

027

028 v_dummyrthbott temp_ambient_node_i temp_ambient_node dc 0

029

030 Cth temp_node temp_ambient_node

031 ’100e-9/(1/(1/(1.4058e-6*0.2475/(nfinger*2*88e-9+171.92e-9)

032 *(832315-1.20969e12*lgate))+1/(2.9581e-6*0.067806

033 /(nfinger*2*88e-9+23.61e-9)*0.10414/(lgate+209.54e-9))

034 +1/(1.2528e-7*(1593042+2.0227e-7/(nfinger*2*88e-9)

035 /(nfinger*2*88e-9))*(1786543+0.60576/lgate))

036 +1/(1.1429e-6*0.29363/(nfinger*2*88e-9+165.55e-9)

037 *(908224-1.778e11*lgate))))’

038

039 Rthd temp_node td_i ’1.4058e-6*0.2475

040 /(nfinger*2*88e-9+171.92e-9)*(832315-1.20969e12*lgate)’

041 Rdummyd td 0 1e20

042

043 v_dummyrthd td_i td dc 0

044

045 Rthg temp_node tg_i ’1.2528e-7*(1593042+2.0227e-7


046 /(nfinger*2*88e-9)/(nfinger*2*88e-9))*(1786543+0.60576/lgate)’

047 Rdummyg tg 0 1e20

048

049 v_dummyrthg tg_i tg dc 0

050

051 Rths temp_node ts_i ’1.1429e-6*0.29363/

052 (nfinger*2*88e-9+165.55e-9)*(908224-1.778e11*lgate)’

053 Rdummys ts 0 1e20

054

055 v_dummyrths ts_i ts dc 0

056

057 .ends nfinfet_shenh

The sense resistance is used as current to voltage translator. The dummy voltagesources are employed as current probes.

5.3.3 Simple simulations of the FinFET subcircuits

The three subcircuits representing the FinFETs have been compared in simpleDC and transient simulations. The transistor described by the enhanced modelhas typical metal lines of 6µm connected to the thermal nodes of the device.

The results of the simulation of the output characteristic of a device with onefinger and a gate length of 100nm are displayed in figure 5.15. The drain current

T [C]

S−H enhanced

S−H classical

without S−H

S−H enhanced

S−H classical

without S−H

Vds [V]

Vds [V]

Id [A]

Figure 5.15: Output characteristic and temperature increments comparison be-tween the three subcircuits (Vgs = 1.2V, nfinger = 1 and L = 100nm). The curvesobtained with the classical and enhanced topologies are almost superimposed

5.4 Analog circuit example: Miller Op Amp 107

decrease due to self-heating effects is in the order of 8%, with both the classicaland the enhanced subcircuit (their curves are almost superimposed). The temper-ature increments in the device are approximately 30 degrees for VDS = VGS = 1.2Vand agree with the simulation results presented in table 4.5. The two subcircuitsimplementing the self-heating of the device exhibit very similar curves.

The results of a transient simulation are displayed in figure 5.16. The drainvoltage is periodically set to 0V and 1.2V. The curves obtained with the classicaland enhanced model exhibit transient current decreases in the order of 8% dueto self-heating effects with a time constant of 100ns. As expected, the curves ofthe subcircuits with self-heating effects are almost superimposed.

T [C]

I [A]

T [C]

t [s]

t [s]

t [s]

t [s]

t [s]

without S−H

S−H classical

S−H classical

S−H enhanced

S−H enhanced

I [A]

I [A]

Figure 5.16: Comparison between the three subcircuits in a transient simulation.An 8% current decrease with a time constant of 100ns due to self-heating isobserved, as expected

5.4 Analog circuit example: Miller Op Amp

The FinFET subcircuits presented in this chapter are now employed for the sim-ulation of a typical analog block: the Miller Op Amp. The objective is to un-derstand whether or not the behaviour of this circuit is adversely affected byself-heating and cross-heating effects.

The schematic of the circuit is displayed in figure 5.17. It employs transistorswith 8, 64 and 128 fingers. The block has been implemented with:


Figure 5.17: Miller Op Amp schematic

• transistor subcircuits without self-heating

• transistor subcircuits with the classical implementation of self-heating andwithout thermal coupling between devices (the thermal nodes of differenttransistors are not connected)

• transistor subcircuits with the classical implementation of self-heating andperfect thermal coupling between the transistors M8-M9, M12-M13 andM10-M11-M15, according to the matching recommendations reported infigure 5.17

• transistor subcircuits with the enhanced implementation of self heating:the metal lengths have been extracted from a layout of the Miller Op Ampemployed in the first FinFET testchip (figure 5.18). The resulting netlist isthe following:


Figure 5.18: Miller Op Amp layout from the first FinFET testchip

xm13 node01 node01 VDD! node101 node102 node103 pfinfet_shenh lgate=100e-9 nfinger=8

xm12 node02 node01 VDD! node104 node105 node106 pfinfet_shenh lgate=100e-9 nfinger=8

xm08 node01 inn node03 node107 node108 node109 nfinfet_shenh lgate=100e-9 nfinger=8

xm09 node02 inp node03 node110 node111 node112 nfinfet_shenh lgate=100e-9 nfinger=8

xm10 node03 node04 VSS! node113 node114 node115 nfinfet_shenh lgate=100e-9 nfinger=8

xm11 out node04 VSS! node116 node117 node118 nfinfet_shenh lgate=100e-9 nfinger=64

xm15 node04 node04 VSS! node119 node120 node121 nfinfet_shenh lgate=100e-9 nfinger=8

xm14 out node02 VDD! node122 node123 node124 pfinfet_shenh lgate=100e-9 nfinger=128

c2 node02 out 10p

r6 VDD! node04 100k

The metal lines extracted from the layout are hereunder presented:

xmetal001 node202 node108 metalline_enh lmetal=’3.5u’








xmetal009 node104 node206 metalline_enh lmetal=’51u’





















The voltage sources representing the nodes at ambient temperature are thefollowing:

vthermalvdd node201 0 temp_amb

vthermalvss node204 0 temp_amb

vthermalinn node202 0 temp_amb

vthermalinp node203 0 temp_amb

vthermalout node205 0 temp_amb

vthermalc1 node206 0 temp_amb

vthermalc2 node207 0 temp_amb

vthermalr1 node208 0 temp_amb

vthermalr2 node209 0 temp_amb

The results of the simulations are presented in figure 5.19, which displays the DCoutput characteristic, the small signal gain and the temperature increments ofthe hottest transistor (M11). As expected, in this circuit the self-heating effectsare not critical with the present FinFET dimensions, since the high resistanceR forces very low currents in the mirrors and hence the power dissipated in thedevices is very low. Temperature increments of no more than 0.7 degrees occurin the circuit. As a result, the curves obtained are almost superimposed.

As an example, the thermal resistance of the M11 transistor in the classicalversion of the subcircuit is calculated with the formula (5.3.4) and the result is:

Rth(W, L)|W=64·2·88·10−9,L=100·10−9 = 3 896

[K

W

](5.4.1)

The thermal resistances of the M11 transistor in the enhanced version of thesubcircuits are calculated with the formulas (5.3.12) (5.3.13), (5.3.14) and (5.3.15)and the results are:

Rth,drain(W, L)|W=64·2·88·10−9,L=100·10−9 = 21 642

[K

W

](5.4.2)

Rth,gate(W, L)|W=64·2·88·10−9,L=100·10−9 = 1 569 150

[K

W

](5.4.3)

Rth,source(W, L)|W=64·2·88·10−9,L=100·10−9 = 26 142

[K

W

](5.4.4)

Rth,bottom(W, L)|W=64·2·88·10−9,L=100·10−9 = 5 979

[K

W

](5.4.5)


T(M11,hotspot)

T(M11,thermal nodes)

derivative(Vout)Vdiff [V]

Vdiff [V]

Vdiff [V]

Vdiff [V]

without S−HS−H classicalS−H enhanced

S−H classical, no coupling

S−H classical, coupling

S−H enhanced

hotspot

thermal drain

thermal source

thermal gate

Vout [V]

without S−HS−H classicalS−H enhanced

Figure 5.19: Results of the Miller Op Amp simulation with the three subcircuits:DC output characteristic, small signal gain and temperature of the M11 transistor


In the enhanced topology, the thermal nodes of the transistors are connectedwith metal lines whose thermal behaviour is simulated with the structure alreadypresented in section 3.4.1. If we consider a typical metal length of 6µm, the ther-mal resistances of the structure are calculated according to the formulas (2.4.10),(2.4.11) and (2.4.12) and the results are:

R1 = R3 = 47 907

[K

W

](5.4.6)

R2 = 95 814

[K

W

](5.4.7)

R4 = R5 = 81 053

[K

W

](5.4.8)

These results demonstrate that even though most of the heat flows towards thebottom silicon, in principle the cross-coupling through the metal lines is notnegligible, especially if we consider the drain and source metals.

Even though the self-heating is not important (figure 5.19) in a Miller Op Ampimplemented with devices with the present geometry (as displayed in table 4.2),in section 4.5.17 we have proved that a general geometry scaling of the deviceof a factor of two leads to a normalized thermal resistance three times higherthan that calculated with the reference dimensions. Hence, the temperatures willrise very rapidly if we consider devices with reduced dimensions. In order tounderstand whether or not the increased temperatures in very small devices canbe a concern in the Miller Op Amp, further simulations have been performed,where the normalized thermal resistance has been altered by hand. In this case,the normalized thermal resistance Rth0 has been considered constant for arbitrarychannel widths and the thermal resistance of the transistor has been calculatedwith the simple parameterization Rth = Rth0

wchannel. Only the influence of self-heating

has been evaluated, for different values of Rth0 which must be compared to thesimulation results in sections 4.3 and 4.4. The results are displayed in figure 5.20.High temperatures will adversely degrade the small signal gain of the operationalamplifier. As the transistors continue to scale down, self-heating effects will be agreater and greater concern for analog designers.

5.5 Conclusions

In this chapter, completely scalable models for the FinFET have been derivedand implemented in Titan. They can be employed in analog designs for theevaluation of the self-heating influence on the behaviour of analog circuits. TheFinFET subcircuits have been simulated and proved to correctly represent thetypical effects of self-heating in DC and transient characteristics. A Miller OpAmp has been simulated: especially with aggressive geometry scaling, self-heatingeffects resulted in a small signal gain reduction which dramatically degrades theperformance of this widely employed analog block.

5.5 Conclusions 113

Rth0

Rth0 Rth0

Rth0

Rth0

Rth0

Vdiff [V]

Vdiff [V]

Vdiff [V]

temperature(M11,hotspot)

derivative(Vout)

Vout [V]

Figure 5.20: Results of the Miller Op Amp simulation with increasing thermalresistances. RTH0ALTER is the normalized thermal resistance Rth0 expressed in(

m·KW

). Cross-heating has been neglected

Chapter 6

Conclusions

This work has presented an in-depth investigation of self-heating and cross-heating in modern multi-gate SOI technologies. A new thermal model is proposed,capable to represent the steady-state temperature increments in both mono-fingerand multi-finger FinFETs. The results have been validated with pulsed measure-ments, even though they revealed to be not completely reliable and reproducible.The proposed networks are the starting point for the development of completelyscalable FinFET models, which provide the electrical and thermal characteris-tics of the device and can easily be implemented in electrical circuit simulators.These models can be profitably employed for the investigation of self-heating andcross-heating effects in complex analog blocks. To demonstrate the capabilitiesof the model, a Miller Op Amp has been simulated in detail according to presentday design rules. Due to the low dissipated power, the thermal effects were foundnegligible. However, further investigation has demonstrated that with more ag-gressive scaling the thermal coupling will adversely affect the static characteristicof this block, which is widely employed in analog designs. Hence, we can con-clude that self-heating in multi-gate SOI technologies will play a major role indevice and circuit characterization, especially with the planned reduction of thetransistor feature size. Analog designers cannot neglect these effects in theirsimulations.

Some hints for the future development of the work presented in this thesis arehereunder summarized:

• In this work, the dynamic behaviour of the FinFET is represented witha single thermal time constant obtained from measured curves. A moreprecise dynamic characterization should be provided, with the modeling ofa capacitive network based on the geometry of the problem under analysis.

• The assumptions made for the heat source and hotspot position and shapeshould be investigated in more detail by means of TCAD simulations. Fur-thermore, they should be employed for a better estimation of the heat flowthrough the insulator layer and the metal lines.

• Regarding the validation of the sensitivity analysis of the thermal model,a more extensive measurement strategy should be carried out. For thispurpose, an improvement of the pulsed measurements setup is necessary.

115

116 Conclusions

• Accurate models describing the electrical behaviour of multi-gate transistorsare not yet available. The models presently available fail in characterizingsome of the peculiarities of these devices, hence further improvements areexpected in this direction during the next years. Furthermore, even param-eters for a BSIM4 model (bulk CMOS) are not yet available for FinFETs,although already under development.

• The effects of self-heating and cross-heating in particular in analog circuitsshould be investigated in more detail, with the study of a larger set of basiccircuits representing the most relevant building blocks employed in analogdesign.

• The assumptions concerning the interface thermal resistances of ultra-thinoxide layers should be investigated in more detail. In particular, the ac-tual thermal resistance of the thin gate oxide is critical in determining thetemperature increments in mono-finger devices. The interface thermal resis-tances in correspondence of the surfaces of the different materials employedfor the metal lines and contacts should also be quantified, since in SOI tran-sistors the cross-coupling between devices occurs mainly through the metallines.

• The source-drain regions of the device are modeled in terms of trapezoidalmaterial stripes. This choice should be improved with more precise solutionsof the heat conduction equations, accounting for the presence or absence ofcontacts.

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