Verilog Modeling

Module 1.2 Introduction to Verilog

UNIT 1 : Introduction to Verilog

Levels of AbstractionThere are four different levels of abstraction in verilog:

Behavioral /AlgorithmicData flowGate levelSwitch level.

We will cover Gate level, Data flow and Behavioral Level modeling

Behavioral level

This level describes a system by concurrent algorithms (Behavioral).

Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other.

Functions, Tasks and Always blocks are the main elements.

There is no regard to the structural realization of the design.

module and_gate (out, in1, in2); input in1, in2; output out; reg out;

always @(in1 or in2) begin out = in1 & in2; endendmodule

Simple Behavioral Model: the always block

always block◦ Always waiting for a change to a trigger signal◦ Then executes the body

Not a real register!!A Verilog registerNeeded because of assignment in always block

Specifies when block is executed I.e., triggered by which signals

Register-Transfer Level / Data flow

Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers.

An explicit clock is used. RTL design contains exact timing possibility, operations are scheduled to occur at certain times.

Modern definition of a RTL code is "Any code that is synthesizable is called RTL code".

Data Flow ModelingContinuous assignment statement is used.

Keyword assign is used followed by =

Most common operator types are

Operator Types Operator Symbol

Operation performed

Number of Operands

Arithmetic * / + -

Multiply Divide Add Subract

Two Two Two two

Bitwise Logical ~ & | ^ ^~ or ~^

Bitwise negation Bitwise and Bitwise or Bitwise xor Bitwise xnor

One Two Two Two two

Shift >> <<

Shift right Shift left

Two Two

Concatenation { }

Concatenation Any number

Conditional ?: Conditional three

Examples1. assign x = a + b;2. assign y = ~ x ; // y=x’3. assign y = a & b; // y= ab4. assign w = a ^ b; //y= a b5. assign y = x >> 1; //shift right x by

16. assign y = {b, c}; //concatenate b

with c e.g. b = 3’b101, c =3’b 111 y = 101111 assign {cout , sum} = a + b + cin; //concatenate

sum and cout

module and_gate (out, in1, in2); input in1, in2; output out;

assign out = in1 & in2;

endmodule

Data flow ModelCombinational logic

◦ Describe output as a function of inputs◦ Note use of assign keyword: continuous

assignment

Output port of a primitive mustbe first in the list of ports

Restriction does not apply tomodules

Gate Level/ Structural

Within the logic level the characteristics of a system are described by logical links and their timing properties.

All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`).

The usable operations are predefined logic primitives (AND, OR, NOT etc gates).

Using gate level modeling might not be a good idea for any level of logic design.

Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend.

Gate Level Modeling/Structural

In gate level modeling a circuit can be defined by use of logic gates.

These gates predefined in verilog library.

The basic gates and their syntax is as follows:and gate_name(output, inputs);

or gate_name(output, inputs);

not gate_name (output, inputs);

xor gate_name(output, inputs);

nor gate_name(output, inputs);

nand gate_name(output, inputs);

xnor gate_name(output, inputs);

module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2;

inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2);

endmodule

Structural Model◦ Composition of primitive gates to form more

complex module◦ Note use of wire declaration!

By default, identifiersare wires

Structural vs BehavioralSupports structural and behavioral

descriptionsStructural

◦ Explicit structure of the circuit◦ How a module is composed as an interconnection

of more primitive modules/components◦ E.g., each logic gate instantiated and connected

to othersBehavioral

◦ Program describes input/output behavior of circuit◦ Many structural implementations could have

same behavior◦ E.g., different implementations of one Boolean

function

Modeling typesThe module describes a

component in the circuitTwo ways to describe:

◦Structural Verilog List of components and how they are connected Just like schematics, but using text Hard to write, hard to decode Useful if you don’t have integrated design tools

◦Behavioral Verilog Describe what a component does, not how it does it Synthesized into a circuit that has this behavior

Structural ModelExample of full-adder

module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin;endmodule

module adder4 (A, B, Cin, S, Cout); input [3:0] A, B; input Cin; output [3:0] S; output Cout; wire C1, C2, C3; full_addr fa0 (A[0], B[0], Cin, S[0], C1); full_addr fa1 (A[1], B[1], C1, S[1], C2); full_addr fa2 (A[2], B[2], C2, S[2], C3); full_addr fa3 (A[3], B[3], C3, S[3], Cout);endmodule

Data flow

Structural