vlsi,mos inverter switching characterisitcs, gtu

Gujarat Technological University Subject: VLSI Technology & Design Code:2161101 Topic_2_Fabrication of MOSFET

Compiled By: Prof G B RathodBVM Engineering CollegeET DepartmentV V Nagar-Gujarat-India-388120Email: [email protected]

Gujarat Technological UniversitySubject: VLSI Technology & DesignCode:2161101Topic_5_MOS Inverter: Switching Characteristics and Interconnect Effects

OutlinesIntroduction Delay-time definitions Calculation of Delay times Inverter design with delay constraints Estimation of Interconnect Parasitic Calculation of interconnect delay Switching Power Dissipation of CMOS Inverters OutcomesReferences

03-May-16BVM ET2

Introduction03-May-16BVM ET3In this chapter, we will investigate the dynamic (time-domain) behavior of the inverter circuits.The switching characteristics of digital integrated circuits and, in particular, of inverter circuits, essentially determine the overall operating speed of digital systems.Consider the cascade connection of two CMOS inverter circuits shown in Fig. 6.1. The parasitic capacitances associated with each MOSFET are illustrated individually.

Introduction03-May-16BVM ET4

Introduction03-May-16BVM ET5The problem of analyzing the output voltage waveform is fairly complicated, even for this relatively simple circuit, because a number of nonlinear, voltage-dependent capacitances are involved.To simplify the problem, we first combine the capacitances seen in Fig. 6.1 into an equivalent lumped linear capacitance, connected between the output node of the inverter and the ground. This combined capacitance at the output node will be called the load capacitance, Cload

Introduction03-May-16BVM ET6The delay times calculated using Cload may slightly overestimate the actual inverter delay, but this is not considered a significant deficiency in a first-order approximation.

Delay Time Definitions03-May-16BVM ET7The input and output voltage waveforms of a typical inverter circuit are shown in Fig. 6.3.The propagation delay times TPHL and TPLH determine the input-to-output signal delay during the high-to-low and low-to-high transitions of the output, respectively.TPHL is the time delay between the V50%-transition of the rising input voltage and the V50 -transition of the falling output voltage. TPLH is defined as the time delay between the V50 -transition of the falling input voltage and the V50%-transition of the rising output voltage.

Delay Time Definitions03-May-16BVM ET8

Delay Time Definitions03-May-16BVM ET9The voltage point V50% is defined as follows.

The average propagation delay Tp of the inverte characterizes the average time required for the input signal to propagate through the inverter.

Delay Time Definitions03-May-16BVM ET10Propagation average Time

We will refer to Fig. 6.4 for the definition of output voltage rise and fall times.

Delay Time Definitions03-May-16BVM ET11The rise time Trise is defined here as the time required for the output voltage to rise from the V10% level to V90% level.Similarly, the fall time Tfall is defined here as the time required for the output voltage to drop from the V90% level to V10% level. The voltage levels V10% and V90% are defined as

Calculations of Delay Times03-May-16BVM ET12The simplest approach for calculating the propagation delay times TPHL and TPLH is based on estimating the average capacitance current during charge down and charge up, respectively.

Calculations of Delay Times03-May-16BVM ET13Note that the average current during high-to-low transition can be calculated by using the current values at the beginning and the end of the transition.

Similarly, the average capacitance current during low-to-high transition is

Calculations of Delay Times03-May-16BVM ET14The circuit given in Fig. 6.2 can now be reduced to a single nMOS transistor and a capacitor, as shown in Fig. 6.5. The, input and output voltage waveforms during this high-to-low transition are illustrated in Fig. 6.6.

Calculations of Delay Times03-May-16BVM ET15

Calculations of Delay Times03-May-16BVM ET16After considering the various parameters of nMOS transistor, we can able to get the both the equations of the propagation delay as follows,

Inverter design with delay constraints03-May-16BVM ET17CMOS Ring Oscillator CircuitConsider the cascade connection of three identical CMOS inverters, as shown in Fig. 6.9, where the output node of the third inverter is connected to the input node of the first inverter.As such, the three inverters form a voltage feedback loop. It can be found by simple inspection that this circuit does not have a stable operating point.In fact, a closedloop cascade connection of any odd number of inverters will display astable behavior

Inverter design with delay constraints03-May-16BVM ET18

Inverter design with delay constraints03-May-16BVM ET19such a circuit will oscillate once any of the inverter input or output voltages deviate from the unstable operating point, Vth. Therefore, the circuit is called a ring oscillator.Figure 6.10 shows the typical output voltage waveforms of the three inverters during oscillation.It can be seen from Fig. 6.10 that each inverter triggers the next inverter in the cascade connection, and the last inverter again triggers the first, thus sustaining the oscillation.

Inverter design with delay constraints03-May-16BVM ET20

Inverter design with delay constraints03-May-16BVM ET21In' this three-stage circuit, the oscillation period T of any of the inverter output voltages can be expressed as the sum of six propagation delay times (Fig. 6.10).we can also express the oscillation period T in terms of the average propagation delay Tp, as

Inverter design with delay constraints03-May-16BVM ET22Generalizing this relationship for an arbitrary odd number (n) of cascade-connected inverters, we obtain

Thus, the oscillation frequency (f) is found to be a very simple function of the average propagation delay of an inverter stage.

Estimation of Interconnect Parasitics03-May-16BVM ET23The classical approach for determining the switching speed of a logic gate is based on the assumption that the loads are mainly capacitive and lumped.The conventional delay estimation approaches seek to classify three main components of the output load, all of which are assumed to be purely capacitive, as: (i) internal parasitic capacitances of the transistors, (ii) interconnect (line) capacitances, and (iii) input capacitances of the fan-out gates.Figure 6.11 shows a simple situation where an inverter is driving three other inverters, linked by interconnection lines of different length and geometry.

Estimation of Interconnect Parasitics03-May-16BVM ET24

Estimation of Interconnect Parasitics03-May-16BVM ET25The (length/width) ratio of the wire usually dictates that the parameters are distributed, making the interconnect a true transmission line.The following is a simple rule of thumb which can be used to determine when to use transmission-line models.

Estimation of Interconnect Parasitics03-May-16BVM ET26The capacitance components associated with parallel interconnection lines (in two different configurations) are depicted in Fig. 6.20.This coupling between the interconnect lines is mainly responsible for signal crosstalk, where transitions in one line can cause noise in the other lines.Figure 6.22 shows the cross-section view of a double-metal CMOS structure, where the individual parasitic capacitances between the layers are also indicated.



Calculation of Interconnect Delay03-May-16BVM ET29An interconnect line can be modeled as a lumped RC network if the time of flight across the interconnection line is significantly shorter than the signal rise/fall times.This is usually the case in most on-chip interconnects, thus, we will mainly concentrate on the calculation of delay in RC networks, in the following.The simplest model which can be used to represent the resistive and capacitive parasitics of the interconnect line consists of one lumped resistance and one lumped capacitance (Fig. 6.23(a)).

Calculation of Interconnect Delay03-May-16BVM ET30

Calculation of Interconnect Delay03-May-16BVM ET31The transient behavior of an interconnect line can be more accurately represented using the RC ladder network, shown in Fig. 6.24.

Calculation of Interconnect Delay03-May-16BVM ET32The Elmore DelayConsider a general RC tree network, as shown in Fig. 6.25. Note that (i) there are no resistor loops in this circuit, (ii) all of the capacitors in an RC tree are connected between a node and the ground, and (iii) there is one input node in the circuit.Also notice that there is a unique resistive path, from the input node to any other node in the circuit.

Calculation of Interconnect Delay03-May-16BVM ET33

Calculation of Interconnect Delay03-May-16BVM ET34Assuming that the input signal is a step pulse at time t = 0, the Elmore delay at node i of this RC tree is given by the following expression.

Calculation of the Elmore delay is equivalent to deriving the first-order time constant (first moment of the impulse response) of this circuit.The procedure to calculate the delay at any node in the circuit is very straightforward. For example, the Elmore delay at node 7 can be found according to the above equation

Calculation of Interconnect Delay03-May-16BVM ET35We get,

Similarly, the Elmore delay at node 5 can be calculated as

Switching Power Dissipation of CMOS Inverters03-May-16BVM ET36During switching events where the output load capacitance is alternatingly charged up and charged down, on the other hand, the CMOS inverter inevitably dissipates power.Consider the simple CMOS inverter circuit shown in Fig. 6.27. We will assume that the input voltage is an ideal step waveform with negligible rise and fall times.Typical input and output voltage waveforms and the expected load capacitor current waveform are shown in Fig. 6.28.

Switching Power Dissipation of CMOS Inverters03-May-16BVM ET37

Switching Power Dissipation of CMOS Inverters03-May-16BVM ET38

Switching Power Dissipation of CMOS Inverters03-May-16BVM ET39Assuming periodic input and output waveforms, the average power dissipated by any device over one period can be found as follows:

Since during switching, the nMOS transistor and the pMOS transistor in a CMOS inverter conduct current for one-half period each, the average power dissipation of the CMOS inverter can be calculated as the power required to charge up and charge down the output load capacitance.

Switching Power Dissipation of CMOS Inverters03-May-16BVM ET40We get,

Noting that f= 1/T, this expression can also be written as:

It is clear that the average power dissipation of the CMOS inverter is proportional to the switching frequency f Therefore, the low-power advantage of CMOS circuits becomes less prominent in high-speed operation, where the switching frequency is high.

Outcomes03-May-16BVM ET41From this unit, we come to know about MOS inverters. And specifically the interconnect effect of the MOS circuit.When we talk about interconnect effect, the more focus on the delay of the output or we can say delay of the signals. Here the effects of capacitances were also discussed.The effect of parasitics and also the calculations of the propagation delay time with the detailed understanding is represented.

References03-May-16BVM ET42Book: CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Y. Leblebici.