© digital integrated circuits 2nd inverter digital integrated circuits a design perspective the...
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© Digital Integrated Circuits2nd Inverter
Digital Integrated Digital Integrated CircuitsCircuitsA Design PerspectiveA Design Perspective
The InverterThe InverterJuly 30, 2002
© Digital Integrated Circuits2nd Inverter
CMOS InverterCMOS Inverter
Polysilicon
In Out
VDD
GND
PMOS 2
Metal 1
NMOS
OutIn
VDD
PMOS
NMOS
Contacts
N Well
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Two InvertersTwo Inverters
Connect in Metal
Share power and ground
Abut cells
VDD
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CMOS Inverter: Transient ResponseCMOS Inverter: Transient Response
tpHL = f(Ron.CL)
= 0.69 RonCL
VoutVout
Rn
Rp
VDDVDD
Vin 5 VDDVin 5 0
(a) Low-to-high (b) High-to-low
CLCL
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Voltage TransferVoltage TransferCharacteristicCharacteristic
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CMOS Inverter Load CharacteristicsCMOS Inverter Load Characteristics
IDn
Vout
Vin = 2.5
Vin = 2
Vin = 1.5
Vin = 0
Vin = 0.5
Vin = 1
NMOS
Vin = 0
Vin = 0.5
Vin = 1Vin = 1.5
Vin = 2
Vin = 2.5
Vin = 1Vin = 1.5
PMOS
© Digital Integrated Circuits2nd Inverter
CMOS Inverter VTCCMOS Inverter VTC
Vout
Vin0.5 1 1.5 2 2 .5
0.5
11.
52
2.5
NMOS resPMOS off
NMOS satPMOS sat
NMOS offPMOS res
NMOS satPMOS res
NMOS resPMOS sat
© Digital Integrated Circuits2nd Inverter
Switching Threshold as a function Switching Threshold as a function of Transistor Ratioof Transistor Ratio
100
101
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
MV
(V
)
Wp
/Wn
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Determining VDetermining VIHIH and V and VILIL
VOH
VOL
Vin
Vout
VM
VIL VIH
A simplified approach
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Gain as a function of VDDGain as a function of VDD
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin
(V)
Vou
t(V
)
0 0.5 1 1.5 2 2.5-18
-16
-14
-12
-10
-8
-6
-4
-2
0
Vin
(V)
gain
© Digital Integrated Circuits2nd Inverter
Impact of Process VariationsImpact of Process Variations
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
Vo
ut(V
)
Good PMOSBad NMOS
Good NMOSBad PMOS
Nominal
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Propagation DelayPropagation Delay
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CMOS Inverter Propagation DelayCMOS Inverter Propagation DelayVDD
Vout
Vin = VDD
Ron
CL
tpHL = f(Ron.CL)
= 0.69 RonCL
t
Vout
VDD
RonCL
1
0.5
ln(0.5)
0.36
© Digital Integrated Circuits2nd Inverter
0 0.5 1 1.5 2 2.5
x 10-10
-0.5
0
0.5
1
1.5
2
2.5
3
t (sec)
Vou
t(V)
Transient ResponseTransient Response
tp = 0.69 CL (Reqn+Reqp)/2
?
tpLHtpHL
© Digital Integrated Circuits2nd Inverter
Design for PerformanceDesign for Performance
Keep capacitances small: Cload, Cgate, Cdiff
Increase transistor sizes: W/L watch out for self-loading!
Increase VDD (????)
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Delay as a function of VDelay as a function of VDDDD
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VDD
(V)
t p(nor
mal
ized
)
© Digital Integrated Circuits2nd Inverter
2 4 6 8 10 12 142
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8x 10
-11
S
t p(sec
)
Device SizingDevice Sizing
(for fixed load)
Self-loading effect:Intrinsic capacitancesdominate
© Digital Integrated Circuits2nd Inverter
1 1.5 2 2.5 3 3.5 4 4.5 53
3.5
4
4.5
5x 10
-11
t p(sec
)
NMOS/PMOS ratioNMOS/PMOS ratio
tpLH tpHL
tp = Wp/Wn
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Inverter SizingInverter Sizing
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Inverter ChainInverter Chain
CL
If CL is given:- How many stages are needed to minimize the delay?- How to size the inverters?
May need some additional constraints.
In Out
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Inverter DelayInverter Delay
• Minimum length devices, L=0.25m• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays• Analyze as an RC network
WNunit
Nunit
unit
PunitP RR
W
WR
W
WRR
11
tpHL = (ln 2) RNCL tpLH = (ln 2) RPCLDelay (D):
2W
W
unitunit
gin CW
WC 3Load for the next stage:
© Digital Integrated Circuits2nd Inverter
Inverter with LoadInverter with Load
Load (CL)
Delay
Assumptions: no load -> zero delay
CL
tp = k RWCL
RW
RW
Wunit = 1
k is a constant, equal to 0.69
© Digital Integrated Circuits2nd Inverter
Inverter with LoadInverter with Load
Load
Delay
Cint CL
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)= Delay (Internal) + Delay (Load)
CN = Cunit
CP = 2Cunit
2W
W
© Digital Integrated Circuits2nd Inverter
Delay FormulaDelay Formula
/1/1
~
0int ftCCCkRt
CCRDelay
pintLWp
LintW
Cint = Cgin with 1f = CL/Cgin - effective fanoutR = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
© Digital Integrated Circuits2nd Inverter
Apply to Inverter ChainApply to Inverter Chain
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
jgin
jginunitunitpj C
CCRt
,
1,1~
LNgin
N
i jgin
jginp
N
jjpp CC
C
Cttt
1,
1 ,
1,0
1, ,1
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Optimal Tapering for Given Optimal Tapering for Given NN
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
- each stage has the same effective fanout (Cout/Cin)- each stage has the same delay
1,1,, jginjginjgin CCC
© Digital Integrated Circuits2nd Inverter
Optimum Delay and Number of Optimum Delay and Number of StagesStages
1,/ ginLN CCFf
When each stage is sized by f and has same eff. fanout f:
N Ff
/10N
pp FNtt
Minimum path delay
Effective fanout of each stage:
© Digital Integrated Circuits2nd Inverter
ExampleExample
CL= 8 C1
In Out
C11 f f2
283 f
CL/C1 has to be evenly distributed across N = 3 stages:
© Digital Integrated Circuits2nd Inverter
Optimum Number of StagesOptimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
ff
fFtFNtt pN
pp lnln
ln1/ 0/1
0
0ln
1lnln2
0
f
ffFt
f
t pp
For = 0, f = e, N = lnF
f
FNCfCFC in
NinL ln
ln with
ff 1exp
© Digital Integrated Circuits2nd Inverter
Optimum Effective Fanout Optimum Effective Fanout ffOptimum f for given process defined by
ff 1exp
fopt = 3.6for =1
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Buffer DesignBuffer Design
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
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Power DissipationPower Dissipation
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Where Does Power Go in CMOS?Where Does Power Go in CMOS?
• Dynamic Power Consumption
• Short Circuit Currents
• Leakage
Charging and Discharging Capacitors
Short Circuit Path between Supply Rails during Switching
Leaking diodes and transistors
© Digital Integrated Circuits2nd Inverter
Dynamic Power DissipationDynamic Power Dissipation
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Need to reduce CL, Vdd, and f to reduce power.
Vin Vout
CL
Vdd
Not a function of transistor sizes!
© Digital Integrated Circuits2nd Inverter
Node Transition Activity and PowerNode Transition Activity and PowerConsider switching a CMOS gate for N clock cycles
EN CL Vdd 2 n N =
n(N): the number of 0->1 transition in N clock cycles
EN : the energy consumed for N clock cycles
Pavg N lim
ENN
-------- fclk= n N
N------------
N lim
C
LVdd
2fclk
=
0 1
n N N
------------N
lim=
Pavg = 0 1 C
LVdd
2 fclk
© Digital Integrated Circuits2nd Inverter
Short Circuit CurrentsShort Circuit Currents
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
© Digital Integrated Circuits2nd Inverter
How to keep Short-Circuit Currents Low?How to keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,but can’t do this for cascade logic, so ...
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Minimizing Short-Circuit PowerMinimizing Short-Circuit Power
0 1 2 3 4 50
1
2
3
4
5
6
7
8
tsin
/tsout
Pno
rm
Vdd =1.5
Vdd =2.5
Vdd =3.3
© Digital Integrated Circuits2nd Inverter
Static Power ConsumptionStatic Power Consumption
Vin=5V
Vout
CL
Vdd
Istat
Pstat = P(In=1).Vdd . Istat
• Dominates over dynamic consumption
• Not a function of switching frequency
Wasted energy …Should be avoided in almost all cases,but could help reducing energy in others (e.g. sense amps)
© Digital Integrated Circuits2nd Inverter
Leakage CurrentsLeakage Currents
Vout
Vdd
Sub-ThresholdCurrent
Drain JunctionLeakage
Sub-Threshold Current Dominant FactorSub-threshold current one of most compelling issuesin low-energy circuit design!
© Digital Integrated Circuits2nd Inverter
Reverse-Biased Diode LeakageReverse-Biased Diode Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS A
JS = 1-5pA/m2 for a 1.2m CMOS technology
Js double with every 9oC increase in temperature
JS = 10-100 pA/m2 at 25 deg C for 0.25m CMOSJS doubles for every 9 deg C!
© Digital Integrated Circuits2nd Inverter
Total Power ConsumptionTotal Power Consumption
Ptot = Pdyn + Pdp + Pstat
= (CLVDD + VDD Ipeak ts)f0-1 + VDD Ileak
Ipeak = Maximum short circuit currentTs = 0-100% transition time of IpeakIleak = The current that flows between the supply rails in
the absence of switching activity.
2
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Principles for Power ReductionPrinciples for Power Reduction
Prime choice: Reduce voltage! Recent years have seen an acceleration in
supply voltage reduction Design at very low voltages still open question
(0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance
Device Sizing: for F=20– fopt(energy)=3.53, fopt(performance)=4.47
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Impact ofImpact ofTechnology Technology ScalingScaling
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Goals of Technology ScalingGoals of Technology Scaling
Make things cheaper: Want to sell more functions (transistors)
per chip for the same money Build same products cheaper, sell the
same part for less money Price of a transistor has to be reduced
But also want to be faster, smaller, lower power
© Digital Integrated Circuits2nd Inverter
Technology ScalingTechnology Scaling
Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating
frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
Die size used to increase by 14% per generation
Technology generation spans 2-3 years
© Digital Integrated Circuits2nd Inverter
Technology Evolution (2000 data)Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
18617717116013010690Max P power [W]
1.4
1.2
6-7
1.5-1.8
180
1999
1.7
1.6-1.4
6-7
1.5-1.8
2000
14.9-3.6
11-37.1-2.53.5-22.1-1.6Max frequency
[GHz],Local-Global
2.52.32.12.42.0Bat. power [W]
109-10987Wiring levels
0.3-0.60.5-0.60.6-0.90.9-1.21.2-1.5Supply [V]
30406090130Technology node
[nm]
20142011200820042001Year of
Introduction
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
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ITRS Technology RoadmapITRS Technology Roadmap
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TerminologyTerminology
ITRS: International Technology Roadmap for Semiconductors. It is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment
DRAM Half-pitch: The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch has been reduced to 130 nm (.13 micron).
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Half PitchHalf Pitch
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Technology Scaling (1)Technology Scaling (1)
Minimum Feature SizeMinimum Feature Size
1960 1970 1980 1990 2000 201010
-2
10-1
100
101
102
Year
Min
imum
Fea
ture
Siz
e (m
icro
n)
Propagation DelayPropagation Delay
tp decreases by 13%/year 50% every 5 years!
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Technology Scaling (2) Technology Scaling (2)
Number of components per chipNumber of components per chip
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Technology Scaling Models Technology Scaling Models
• Full Scaling (Constant Electrical Field)
• Fixed Voltage Scaling
• General Scaling
ideal model — dimensions and voltage scaletogether by the same factor S
most common model until recently —only dimensions scale, voltages remain constant
most realistic for todays situation —voltages and dimensions scale with different factors
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Scaling Relationships for Long Channel DevicesScaling Relationships for Long Channel Devices
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Transistor ScalingTransistor Scaling(velocity-saturated devices)(velocity-saturated devices)
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Processor ScalingProcessor Scaling
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
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Processor PowerProcessor Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
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Processor PerformanceProcessor Performance
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
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2010 Outlook2010 Outlook
Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock
Size No of transistors: 2 Billion Die: 40*40 mm
Power 10kW!! Leakage: 1/3 active Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001
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Some interesting questionsSome interesting questions
What will cause this model to break? When will it break? Will the model gradually slow down?
Power and power density Leakage Process Variation