1. IC Fabrication Process Steps

The fabrication of integrated circuits consists basically of the following process steps:

1. Oxidation2. Lithography3. Etching4. Diffusion5. Ion Implantation 6. Epitaxy7. Metalization

Oxidation: In the oxidation process oxygen (dry oxidation) or H2 O (wet oxidation) molecules convert silicon layers on top of the wafer to silicon dioxide.

It serves as a mask against implant or diffusion dopant into silicon.It provides surface passivation.Isolates one device from another.Acts as a component in MOS structure.

There are various techniques to form the oxide layer some of these are Thermal oxidation, Vapour phase technique(CVD) and Plasma Oxidation.

DIAGRAM

Photo Lithography: The process for pattern definition by applying thin uniform layer of viscous liquid (photo-resist) on the wafer surface. The photo-resist is hardened by baking and than selectively removed by projection of light through a reticle containing mask information.

Lithography process is used to transfer patterns from the mask on to the surface of wafer.

Etching: Selectively removing unwanted material from the surface of the wafer. The pattern of the photo-resist is transferred to the wafer by means of etching agents.

In wet etching ,the wafers are immersed in a chemical solution at a predetermined temperature. In this process the material to be etched is removed equally in all directions . Because of this ,some material is etched from the regions where it is to be left.

DIAGRAM

Diffusion: The process of introduction of impurities into selected regions of a wafer to form active regions and junctions called diffusion.

Ion Implantation: Most widely used technique to introduce dopant impurities into semiconductor. The ionized particles are accelerated through an electrical field and targeted at the semiconductor wafer.

DIAGRAM

Metalization: The process used to provide interconnections and external connections . Al is the bettr choice for macking connections because

1. Easy to evaporate2. Can be easily etched3. Not expensive

DIAGRAM

Deposition: Films of the various materials are applied on the wafer. For this purpose mostly two kind of processes are used, physical vapor deposition (PVD) and chemical vapor deposition (CVD).

Chemical Mechanical Polishing: A planarization technique by applying a chemical slurry with etchant agents to the wafer surface.

2.A ) NMOS Fabrication:

The process starts with the oxidation of the silicon substrate , in which a

relatively thick silicon dioxide layer, also called field oxide, is created on the surface

. Then, the field oxide is selectively etched to expose the silicon surface on which

the MOS transistor will be created . Following this step, the surface is covered with a

thin, high-quality oxide layer, which will eventually form the gate oxide of the MOS

transistor . On top of the thin oxide, a layer of polysilicon (polycrystalline silicon) is

deposited. Polysilicon is used both as gate electrode material for MOS transistors

and also as an interconnect medium in silicon integrated circuits. Undoped

polysilicon has relatively high resistivity. The resistivity of polysilicon can be

reduced, however, by doping it with impurity atoms.

After deposition, the polysilicon layer is patterned and etched to form the

interconnects and the MOS transistor gates (Fig. 8(f)). The thin gate oxide not

covered by polysilicon is also etched away, which exposes the bare silicon surface

on which the source and drain junctions are to be formed (Fig. 8(g)). The entire

silicon surface is then doped with a high concentration of impurities, either through

diffusion or ion implantation (in this case with donor atoms to produce n-type

doping). Figure 8(h) shows that the doping penetrates the exposed areas on the

silicon surface, ultimately creating two n-type regions (source and drain junctions) in

the p-type substrate.

The impurity doping also penetrates the polysilicon on the surface, reducing

its resistivity. Note that the polysilicon gate, which is patterned before doping

actually defines the precise location of the channel region and, hence, the location of

the source and the drain regions. Since this procedure allows very precise

positioning of the two regions relative to the gate, it is also called the self-aligned

process.

Once the source and drain regions are completed, the entire surface is again

covered with an insulating layer of silicon dioxide . The insulating oxide layer is

then patterned in order to provide contact windows for the drain and source junctions

. The surface is covered with evaporated aluminum which will form the

interconnects .Finally, the metal layer is patterned and etched, completing the

interconnection of the MOS transistors on the surface . Usually, a second (and third)

layer of metallic interconnect can also be added on top of this structure by creating

another insulating oxide layer, cutting contact (via) holes, depositing, and patterning

the metal.

2.B BiCMOS TECHNOLOGY FABRICATION

The MOS technology lies in the limited load driving capabilities of MOS transistors. This is due to the limited current sourcing and current sinking abilities associated with both p- and n- transistors.

Bipolar transistors provide higher gain and have generally better noise and high frequency characteristics than MOS transistors and have effective way of speeding up VLSI circuits.

When considering CMOS technology, there is difficulty in extending the fabrication processes to include bipolar as well as MOS transistors.

Indeed, a problem of p-well and n-well CMOS processing is that parasitic bipolar transistors are formed as part of the outcome of fabrication.

The production of npn bipolar transistors with good performa nce characteristics can be achieved by extending the standard n-well CMOS processing to include further masks to addtwo additional layers such as the n+ subcollector and p+ base layers.

The npn transistors is formed in an n- well and the additional p+ base region is located in the well to form the p-base region of the transistor.

The second additional layer, the buried n+ subcollector (BCCD), is added to reduce the n-well (collector) resistance and thus improve the quality of the bipolar transistor. The arrangement of BiCMOS npn transistor is shown in fig .

3.A) The p-well process

A common approach to p-well CMOS fabrication is to start with moderately doped n-type substrate (wafer), create the p-type well for the n-channel devices, and build the p-channel transistor in the native n-substrate. The processing steps are,

1. The first mask defines the p-well (p-tub) n-channel transistors (Fig. 1.4a) will be fabricated in this well. Field oxide (FOX) is etched away to allow a deep diffusion.

2. The next mask is called the “thin oxide” or “thinox” mask (Fig. 1.4b), as it defines where areas of thin oxide are needed to implement transistor gates and allow implantation to form p- or n-type diffusions for transistor source/drain regions.

The field oxide areas are etched to the silicon surface and then the thin oxide areas is grown on these areas. .

3. Polysilicon gate definition is then completed. This involves covering the surface with polysilicon (Fig 1.4c) and then etching the required pattern (in this case an inverted “U”). “Poly” gate regions lead to “self-aligned” source-drain regions.

4. A p-plus (p+) mask is then used to indicate those thin-oxide areas (and polysilicon) that are

to be implanted p+. Hence a thin-oxide area exposed by the p-plus mask (Fig. 1.4d) will become a p+ diffusion area. If the p-plus area is in the n-substrate, then a p-channel transistor or p- type wire may be constructed. If the p-plus area is in the p-well, then an ohmic contact to the p-well may be constructed.

5. The next step usually uses the complement of the p-plus mask, although an extra mask is normally not needed. The “absence” of a p-plus region over a thin-oxide area indicates that thearea will be an n+ diffusion or n-thinox. n-thinox in the p-well defines possible ntransistors and wires. An n+ diffusion (Fig. 1.4e) in the n-substrate allows an ohmic contact to be made. Following this step, the surface of the chip is covered with a layer of Sio2.

6. Contacts cuts are then defined. This involves etching any Sio2 down to the contacted surface, these allow metal (Fig. 1.4f) to contact diffusion regions or polysilicon regions.

7. Metallization (Fig. 1.4g) is then applied to the surface and selectively etched.

8. As a final step, the wafer is passivated and openings to the bond pads are etched to allow for wire bonding. Passivation protects the silicon surface against the ingress of contaminants.

Basically the structure consists of an n-type substrate in which p-devices may be formed by suitable masking and diffusion and, in order to accommodate n-type devices, a deep p-well is diffused into the n-type substrate.

This diffusion must be carried out with special care since the p-well doping concentration and depth will affect the threshold voltages as well as the breakdown

voltages of the n-transistors.

To achieve low threshold voltage (0.6 to 1.0 V), deep well diffusion or high well resistivity is needed.

However, deep wells require larger spacing between the n- and p-type transistors and wires because of lateral diffusion resulting in larger chip areas.

High resistivity can accentuate latch-up problems. In order to achieve narrow threshold voltage tolerances in a typical p-well process, the well concentration is made about one order of magnitude higher than the substrate doping density, thereby causing the body effect for n-channel devices to be higher than for p-channel transistors.

In addition, due to this higher concentration, n-transistors suffer from excessive source/drain to p-well capacitance will tends to be slower in performance.

The well must be grounded in such a way as to minimize any voltage drop due to injected current in substrate that is collected by the p-well.

The p-well act as substrate for then-devices within the parent n-substrate, and, provided polarity restrictions are observed, the two areas are electrically isolated such that there are in affect two substrate, two substrate connections (VDD and VSS) are required.

4.A)

Transconductance is the ratio of the change in drain current to the change in gate voltage .

The symbol for transconductance is gm. The unit is the siemens, the same unit that is used for direct-current (DC) conductance.

Trans conductance mg

Trans conductance is defined as tcons

dsV

gsIdsI

mg tan

Trans conductance in terms of transistor parameters:

ds

QdsI

since

dsV

Lds

2

2L

dsQV

dsI

gsgc VCQce sin

2L

dsV

gsV

gC

dsI

hence

2L

dsV

gC

gs

dsm V

Ig

In saturation ,

tgsDS VV

tVgsVL

gC

mg

2

D

WLoins

gCtVgsV

DL

Woins

mg

Alternatively tVgsV

mg

Since gm is proportional to width ( W ),it can be increased by increasing width but it increases input capacitance and area occupied .The output conductance g ds can be expressed as

2L

gsV

gC

dsVdsI

dsg

4.B ) DC TRANSFER CHARACTERISTICS OF CMOS INVERTER

The general arrangement and characteristics are illustrated in

Fig. 1 . 1 . The current/voltage relationships for the MOS transistor may be written as,

Figure 1.1 CMOS inverter

Where Wn and Ln, Wp and Lp are the n- and p- transistor dimensions respectively. The CMOS inverter has five regions of operation is shown in Fig.1.2 and in Fig. 1.3.

Figure 1.2 Transfer characteristics

Considering the static condition first, in region 1 for which Vin = logic 0, the p-transistor fully turned on while the n-transistor is fully turned off. Thus no current flows through the inverter and the output is directly connected to VDD through the p-transistor.

In region 5 Vin = logic 1, the n-transistor is fully on while the p-transistor is fully off. Again, no current flows and a good logic 0 appears at the output.

In region 2 the input voltage has increased to a level which just exceeds the threshold voltage of the n-transistor. The n-transistor conducts and has a large voltage between source and drain. The p- transistor also conducting but with only a small voltage across it, it operates in the unsaturated resistive region.

Figure 1.3 CMOS inverter current versus Vin

In region 4 is similar to region 2 but with the roles of the p- and n- transistors reversed.

The current magnitudes in region 2 and 4 are small and most of the energy consumed in switching from one state to the other is due to the large current which flows in region 3.

In region 3 is the region in which the inverter exhibits gain and in which both transistors are in saturation.

Write

The currents in each device must be the same since the transistors are in series. So we may

I dsp = - Idsn

Vin in terms of the β ratio and the other circuit voltages and currents

Vin = VDD + Vtp +Vtn (βn + βp)1/2

1+ (βn + βp)1/2

Since both transistors are in saturation, they act as current sources so that the equivalent circuit in this region is two current sources so that the equivalent circuit in this region is two current sources in series between VDD and VSS with the output voltage coming from their common point.

The region is inherently unstable in consequence and the change over from one logic level to the other is rapid.

Since only at this point will the two β factors be equal. But for βn= βp the device geometries must be such that

µ p Wp/Lp = µ n Wn/Ln

The motilities are inherently unequal and thus it is necessary for the width to length ratio of the p- device to be three times that of the n-device, namely

Wp/Lp = 2.5 Wn/Ln

The mobility µ is affected by the transverse electric field in the channel and is thus independent onVgs.

6.B ) Silicon on insulator p rocess

Silicon on insulator

(SOI) CMOS processes has several potential advantages such as

higher density, no latch-up p roblems, and lower parasitic capacitances.In the SOI process

a thin layer of single crystal silicon film is epitaxial grown on an

insulator such as sapphire or magnesium aluminates spinal. The steps invol ves are:

Figure 1.7 Silicon on insulator process

1) A thin film (7-8 µ m) of very lightly doped n-type Si is grown over an insulator Sapphire is a commonly used insulator.

2) An anisotropic etch is used to etch away the Si except where a diffusion area will be needed.

3) The p-islands are formed next by masking the n-islands with a photo resist. A p-type dopant (boron) is then implanted. It is masked by the photo resist and at the u unmasked islands. The p-islands will become the n-channel devices.

4) The p-islands are then covered with a photo resist and an n-type dopant, phosphorus, is implanted to form the n-islands .The n-islands will become the p-channel devices.

5) A thin gate oxide (500-600Å ) is grown over all of the Si structures. This is normally done by thermal oxidation.

6) A polysilicon film is deposited over the oxide.

7) The polysilicon is then patterned by photo masking and is etched. This defines the polysilicon layer in the structure

8) The next step is to form the n-doped source and drain of the n-channel devices in the p- islands. The n-island is covered with a photo resist and an n-type dopant (phosphorus) is implanted.

9) The p-channel devices are formed next by masking the p-islands and implanting a p-type dopant. The polysilicon over the gate of the n-islands will block the dopant from the gate, thus forming the p-channel devices.

10) A layer of phosphorus glass is deposited over the entire structure. The glass is etched at contact cut locations. The metallization layer is formed. A final passivation layer of a phosphorus glass is deposited and etched over bonding pad locations.

1.7.5 The advantages

Due to the absence of wells, denser structures than bulk silicon can be obtained.

Low capacitances provide the basis of very fast circuits. No field-inversion problems exist. No latch-up due to isolation of n- and p- transistors by insulating substrate. As there is no conducting substrate, there are no body effect problems Enhanced radiation tolerance.

But the drawback is due to absence of substrate diodes, the inputs are difficult to protect. As device gains are lower, I/O structures have to be larger. Single crystal sapphires are more expensive than silicon and processing techniques tend to be less developed than bulk silicon techniques.

UNIT –II answers

1. a) Calculate rise and fall times of the CMOS inverter with (W/L)n=6,(W/L)p=8 ,Kn=150µ A/V2

,V TN=0.7V ,Kp= 62µA/V2 ,VTP= -0.85V,VDD=3.3V and Total Capacitance = 150 PF.b) Calculate gate capacitance value of 2 µm technology minimum sized transistor with gate to channel

capacitance value of 8 X 104pF/ohm µm2.

2. a) Estimate the total delay when a larger load capacitance is driven by a large inverter gate N which is

driven by a small gate N-1 and so on. b) What is the problem of driving large capacitance load ? Explain a method to drive such load

3. Draw Transistor level , its Stick and lay out diagrams for nMOS NAND & CMOS Inverter.

4. Explain lamda based design rules with example.5. Explain VLSI design flow.6. Explain scaling on various parameters and Limitations.

1. A) and B ) -- Verify d answer in running notes.

2 A. CMOS INVERTER:

Figure : Cascaded CMOS inverter.

FORMAL ESTIMATION OF DELAY

The inverter either charges or discharges the load capacitance CL. We could also estimate the delay by estimating the rise time and fall time theoretically.

Figure: Rise time estimation.

2. B) DRIVING LARGE CAPACITIVE LOAD

The problem of driving large capacitive loads arises when signals must travel outside the

chip. Usually it so happens that the capacitance outside the chip are higher. To reduce the delay

these loads must be driven by low resistance. If we are using a cascade of inverter as drivers the

pull and pull down resistances must be reduced. Low résistance means low L: W ratio. To reduce

the ratio, W must be increased. Since L cannot be reduced to lesser than minimum we end up

having a device which occupies a larger area. Larger area means the input capacitance increases

and slows down the process more. The solution to this is to have N cascaded inverters with their

sizes increasing, having the largest to drive the load capacitance. Therefore if we have 3

inverters,1st is smallest and third is biggest as shown next.

Figure 11: Cascaded inverters with varying widths.

3. Verify d answer in running notes.4. Verify d answer in d running notes.5.

VLSI Design Flow The design process, at various levels, is usually evolutionary in nature. It starts with a given set of requirements. Initial design is developed and tested against the requirements. When requirements are not met, the design has to be improved. If such improvement is either not possible or too costly, then the revision of requirements and its impact analysis must be considered. The Y-chart (first introduced by D. Gajski) shown in Fig. illustrates a design flow for most logic chips, using design activities on three different axes (domains) which resemble the letter Y.

Figure-: Typical VLSI design flow in three domains (Y-chart representation).

The Y-chart consists of three major domains, namely: • behavioral domain, • structural domain, • Physical (geometrical layout) domain. The design flow starts from the algorithm that describes the behavior of

the target chip. The corresponding architecture of the processor is first defined. It is mapped onto the chip surface by floor planning.

The next design evolution in the behavioral domain defines finite state machines (FSMs) which are structurally implemented with functional modules such as registers and arithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface using CAD tools for automatic module placement followed by routing, with a goal of minimizing the interconnect area and signal delays.

The third evolution starts with a behavioral module description. Individual modules are then implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf cells), which can be placed and interconnected by using a cell placement & routing program. The last evolution involves a detailed Boolean description of leaf cells followed by a transistor level implementation of leaf cells and mask generation. In standard-cell based design, leaf cells are already pre-designed and stored in a library for logic design use. The simplified version of the VLSI design flow is shown in figure

.

Figure provides a more simplified view of the VLSI design flow, taking into account the various representations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the verification of design plays a very important role in every step during this process. The failure to properly verify a design in its early phases typically causes significant and expensive re-design at a later stage, which ultimately increases the time-to-market.

Although the design process has been described in linear fashion for simplicity, in reality there are many iterations back and forth, especially between any two neighboring steps, and occasionally even remotely separated pairs. Although top-down design flow provides an excellent design process control, in reality, there is no truly unidirectional top-down design flow. Both top-down and bottomup approaches have to be combined. For instance, if a chip designer defined an architecture without close estimation of the corresponding chip area, then it is very likely that the resulting chip layout exceeds the area limit of the available technology. In such a case, in order to fit the architecture into the allowable chip area, some functions may have to be removed and the design process must be repeated. Such changes may require significant modification of the original requirements. Thus, it is very important to feed forward low-level information to higher levels (bottom up) as early as possible.

6. Scaling – verify d answer in d running notes.

SHORT ANSWER QUESTIONS:

I1. What is Moore’s law?

2. List any four comparisons between CMOS and Bipolar technologies.. CMOS Technology Bipolar technologyLow static power dissipationHigh input impedance (low drivecurrent)Scalable threshold voltageHigh noise marginHigh packing densityHigh delay sensitivity to load (fanoutlimitations)Low output drive currentLow gm (gm Vin)Bidirectional capabilityA near ideal switching device

High power dissipationLow input impedance (high drivecurrent)Low voltage swing logicLow packing densityLow delay sensitivity to loadHigh output drive currentHigh gm (gm eVin)High ft at low currentEssentially unidirectional

3. What are four generations of Integration Circuits?

_ SSI (Small Scale Integration)_ MSI (Medium Scale Integration)

_ LSI (Large Scale Integration)

In the year 1965 Gordon Moore Intel Co-Founder and Chairman predicted that transistors would continue to shrink , allowing :-- Doubled transistors density every 18-24 months-- Doubled performance every 18-24 monthsThe period often quoted as "18 months

_ VLSI (Very Large Scale Integration)

4. Explain about Sheet resistance.

The concept of sheet resistance is being used to know the resistive behavior of the layers that go into formation of the MOS device. Let us consider a uniform slab of conducting material of the following characteristics.

Resistivity-ρ

Width - W

Thickness - t

Length between faces – L as shown next

Figure 1: A slab of semiconductor.We know that the resistance is given by RAB= ρ L/A Ω. The area of the slab considered above is given by A=Wt. Therefore RAB= ρ L/Wt Ω. If the slab is considered as a square then L=W. therefore RAB= ρ /t which is called as sheet resistance represented by Rs. The unit of sheet resistance is ohm per square. It is to be noted that Rs is independent of the area of the slab.

5. Explain about routing capacitance.

Parasitics capacitances are associated with the MOS device due to different layers that

go into its formation. Interconnection capacitance can also be formed by the metal, diffusion and

polysilicon (these are often called as runners) in addition with the transistor and conductor

resistance. All these capacitances actually define the switching speed of the MOS device.

Understanding the source of parasitics and their variation becomes a very essential part of the

design specially when system performance is measured in terms of the speed. The various

capacitances that are associated with the CMOS device are

1. Gate capacitance - due to other inputs connected to output of the device

2. Diffusion capacitance - Drain regions connected to the output

3. Routing capacitance- due to connections between output and other inputs

II1. Why NMOS technology is preferred more than PMOS technology?

N- channel transistors has greater switching speed when compared to PMOS transistors – because electron mobility is higher than hole mobility.

2. Give the different types of CMOS process.

Various cmos technologies are,I) n- well process or n -tub processii) p well process or p-tub processiii) Twin tub processiv) Silicon on Insulator (SOI) process

3. Define Body effect and Threshold voltage.

The threshold volatge VT is not a constant w. r. to the voltage difference between thesubstrate and the source of MOS transistor. This effect is called substrate-bias effect orbody effect.

The Threshold voltage, VT for a MOS transistor can be defined as the voltage appliedbetween the gate and the source of the MOS transistor below which the drain tosource current, IDS effectively drops to zero.

4. Explain the effect of Fan in and Fan out on propagation delay.

The number of other gates that can be connected to the gate's output .

The propagation delay of a CMOS gate deteriorates rapidly as a function of the fan-in. firstly the large number of transistor (2N) increases the overall capacitance of the gate. Secondly a series connection of transistor either in the PUN or PDN slows the gate as well, because the effective (dis)charging resistance is increased .

Fan-out has a lager impact on the gate delay in complementary CMOS than some other logic states. In complementary circuit style, each input connects to both an NMOS and a PMOS device and presents a load to the driving gate equal to the sum of the gates capacitances.Thus we can approximate the influence of fan in and fan-out on propagation delay in omplementary CMOS gate as: Tp= a1 Fin + a2 Fin

2+a3 Fout

Where a1, a2 and a3 are weighing factor which are a function of technology

5. What is Stick Diagram ? Give the various color codings used in stick diagram?

It is used to convey information through the use of color code. Also it is the cartoon of achip layout.

It can be drawn much easier and faster than a complex layout._ These are especially important tools for layout built from large cells

_ Green – n-diffusion _ Red- polysilicon _ Blue –metal _ Yellow- implant

_ Black-contact areas

III1. What is meant by pass transistor logic ?

p-mos can pass strong logic 1 n-mos can pass strong logic 0.

2. What is Channel-length modulation?

The current between drain and source terminals is constant and independent of theapplied voltage over the terminals. This is not entirely correct. The effective length of theconductive channel is actually modulated by the applied VDS, increasing VDS causes the

depletion region at the drain junction to grow, reducing the length of the effectivechannel.

3. What is meant by pull up and pull down devices?

A device connected so as to pull the output voltage to the lower supply voltageusualy 0V is called pull down device.

A device connected so as to pull the output voltage to the upper supply voltage usually

VDD is called pull up device

4. Explain about the Contact cuts.Contact cut is used to make a joint between two MOS layers.When making contacts between poly Si and diffusion in nMOS circuits , occurs in three different ways1. Poly to metal then metal to diffusion .2. Buried contact.3. Butting Contact.When making contacts between poly Si and diffusion in CMOS circuits is using Via.

5. What are two components of Power dissipation

There are two components that establish the amount of power dissipated in a CMOS circuit. These are: i) Static dissipation due to leakage current or other current drawn continuously from the power supply. ii) Dynamic dissipation due to - Switching transient current

- Charging and discharging of load capacitances.

IV1. What is Latch – up and How do you prevent it?

Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.

Latch up problem can be reduced by reducing the gain of parasitic transistors andresistors. It can be prevented in 2 ways• Latch up resistant CMOS program• Layout techniqueThe various lay out techniques areInternal latch up prevention techniqueI/O latch up prevention technique.

2. What are the advantages and disadvantages of SOI process?

Denser transistor structures are possible.• Lower substrate capacitances• No field inversion problem• No latch up

• No body effect problem• Enhanced radiation tolerance

3. What is silicide?

The combination of Silicon and tantalum is known as Silicide. It is used as gate materials

in polysilicon interconnect.4. Define Rise time, Fall time and Delay times

Rise time, r is the time taken for a waveform to rise from 10% to 90% of its steady-state value.

Fall time, f is the time taken for a waveform to fall from 90% to 10% of its steady- State value.

5. What are the different MOS layers?

n-diffusion _ p-diffusion _ Polysilicon

_ Metal