Glossary

Acceptor: A dopant from a lower group than the semiconductor. For elemental semiconductors, acceptors come from group13. When ionized, acceptors create an extra empty state in the valence band of the semiconductor without a correspondingconduction band electron. This significantly increases the conductivity of the material and makes the concentration of holesmuch higher than the concentration of electrons.

Accumulation mode: A mode of the MOS capacitor where the majority carrier of the substrate is accumulated near thesurface. Carrier accumulation occurs when a potential of the appropriate polarity that is higher than the flat band potential isapplied between the gate and the body. This is not a typically encountered mode in MOSFET.

Active-high latch: A latch that is transparent when the clock is high.

Active-low latch: A latch that is transparent when the clock is low.

Active mask: Also known as the diffusion mask. The photomask that defines areas covered by thin oxide in LOCOS. It alsosimultaneously defines areas covered by field oxide as its complement. Sometimes confused for defining areas where heavydoping is implanted, it can only be accurately defined in terms of oxide thickness since it also defines areas under theMOSFET gate.

Active region: A region of operation for BJTs where the BE junction is forward and the BC junction is reverse. The activeregion is chosen for use in amplifiers because the current in the collector is a function mainly of the voltage on the base, thuseffectively turning the transistor into a current source. A large current is injected from the emitter into the base. The collectoris designed so that most of this carrier flux reaches it. Despite the reverse bias at the BC junction, the field is favorable,allowing carriers to flow readily to the collector. The base current is small due to the geometry of the collector, the thinnessof the base, and the asymmetric doping of the emitter.

Address change detector: A circuit that produces a pulse if the address bus of a memory changes over the course of a clockcycle. It is very simple, requiring the use of XOR gates, a large fan-in OR gate and flip-flops. It is used to trigger self-timedreading in memories. This removes the need for an explicit read flag input, with a flag being indicated simply by an addressflipping

Alignment: The process of ensuring the photomask is properly aligned to the wafer. Misalignment can lead to catastrophicresults. There are two levels of alignment, an initial, global alignment. And a relative alignment from mask to mask. Relativealignment is significantly more critical.

Alpha grid: A method of clock distribution where the clock is driven through a dense metal grid. The grid may be drivenfrom multiple directions to reduce skew. Alpha grids aim to reduce absolute skew. They allow easy modification becausethey are agnostic of the underlying structure. However, their area and power cost is high.

Amorphous silicon: Silicon that has no crystal structure, that has very small crystal domains or that is in powdered form.Amorphous silicon has unpredictable and uneven properties, and is thus not suitable for semiconductor circuits. However, ithas some use in solar cells.

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Annealing: A process used to heal cracks in the silicon crystal structure. The wafer is heated to a very high temperature,stopping short of the melting point of silicon. This relaxes atomic bonds, allowing the crystal structure to regroup. Forannealing to happen properly, cooling must be very gradual while heating has to be relatively sudden.

Antenna effect: A damaging effect that can occur during fabrication if antenna rules are not observed. It affects connectionsmade to polysilicon gates through long metal lines. If the metal line goes through multiple layers, there would be multiplesteps in which the connection is not closed and the polysilicon gate is connected to high-impedance metal. The metal can andwill accumulate significant static charge. If the metal has a large area relative to the polysilicon gate, then the total chargewill establish a very large electric field from the polysilicon to the substrate that can break down the thin oxide.

Antenna rules: A special design rule. It imposes a limit on the ratio of the area of all the metal layers but the highest and thearea of a polysilicon gate in a connection. This rule ensures no antenna damage occurs due to the antenna effect duringfabrication.

Architecture (VHDL): The second required part of a VHDL design, the first being an entity. An architecture must beassociated with an entity, but an entity can have multiple associated architectures. An architecture is a description of theinternal construction of the circuit. The bulk of the design lies in the architecture. It consists of two parts: the architecturedeclarations and the architecture body. The architecture declarations include all internal signals, types, subtypes, constants,and components used in the architecture. The architecture body includes instantiations, concurrent statements, sequentialstatements, and function calls that describe the construction of the circuit.

Array (VHDL): A user-defined type in VHDL where the signals are arrays of the same kind of object. Arrays can also bearrays of vectors, creating actual matrices of binary values. Arrays are extremely useful, but must be carefully managed.They are most useful for large storage structures such as shift registers or memories.

Array multiplier: A direct Implementation of binary long multiplication. AND gates are used to create partial products.Half adders and full adders are used to reduce the summands into the product. It is the latter part (adding the summands) thatforms the bulk of multiplier delay and area. Array multipliers have long, nonunique critical paths, and they can dominate thecritical path of any pipeline where they are used.

ASIC: Application-specific integrated circuit. The term is most often applied to integrated circuits designed using standardcells. They are designed to satisfy a certain application defined by the user.

Assert (VHDL): A statement that can be used concurrently or sequentially. It is ignored by synthesis tools and thus can beused within or outside the testbench. The assert statement examines a certain statement, if the statement is true, it produces areport with a certain string, and associates a certain severity level to the string.

Astable circuit: A circuit for which neither logic outputs are stable. It keeps switching between both values, being able tomaintain neither for an arbitrarily sustained time. The most common astable circuit is an odd number of inverters connectedin feedback, forming a ring oscillator.

Asynchronous reset: A reset signal that takes higher priority and thus can override the clock. It is a good design practice toinclude an asynchronous reset for all registers. All such resets should be shorted and connected to a single global reset. Thesignal has to be asynchronous to allow the circuit to be reset without dependence on the clock. The reset is important to beable to return the state of the circuit to a known condition using an external hardware interrupt. Circuits that lack a reset witha global reach cannot be properly initialized and cannot be pushed to a known state if they get stuck.

Asynchronous FIFO: A two port FIFO where each port uses an independent clock. Asynchronous FIFOs can be used tofacilitate synchronization for burst communication. The write port is handled by the transmitter using the transmitter clock.The read port is handled by the receiver using the receiver clock. The empty and full flags can be used to prevent overflowand underflow. The empty and full flags are calculated using the read and write pointers, which come from different clockdomains. Synchronizers are a must to allow the calculation of flags.

Attribute (VHDL): In VHDL, it is a tool that allows the designer to extract information about a named item. The item canbe a type, signal, file, variable, function, or component. Attributes are extremely useful when used by an experienceddesigner, allowing designs to be portable, elegant, and effective. However, the synthesizability of certain types of attributescan be difficult to assess. User-defined attributes are special characteristics attached to a named item by the designer. Theyare most useful in large commercial designs.

594 Glossary

Automatic test equipment: A hardware setup which can automatically test and make judgements about circuits, usuallyfinished and packaged microchips. ATEs are used in commercial settings to sort through a large bulk of chips. It consists of amounting setup for chips, automated loading and unloading robotic arms, and a computer to apply the tests, read theobservations, and make a decision. Binning is the final decision made by ATE, where each part is binned into a separatecontainer based on its performance.

Automatic test pattern generation: The process of automatically generating tests for a circuit under test. ATPG is usuallyassociated with BIST. There are many methods by which these tests can be produced, but using some sort of linear feedbackshift register is very common.

Ball grid array: The IC package of choice for chips with a very large number of pins. Pins are balls of solder at the bottomof the chip. Mounting is done using the flip chip technology and needs specialized equipment.

Band bending: The bending of energy levels under the effect of built-in or external fields. Bending normally refers tononlinear bending which most often affects doped semiconductors due to the formation of space charge regions.

Band model: A model for solid-state materials where the close proximity of a very large number of atoms leads to thecreation of continuums of energy levels rather than discrete levels. Bands form due to level splitting, linking the band modelto Pauli’s exclusion principle and Schrodinger’s wave equations. Bands are separated by forbidden gaps.

Band tilting: A term applied to band bending when it is linear. This is almost exclusively seen in uncharged insulatorsunder the effect of an external field.

Bandgap: A range of energies between the edges of the valence and conduction bands. No electron can reside in thebandgap (unless in an impurity state). For silicon the energy of the bandgap is 1.12 eV. This is the amount of energynecessary for electrons in the valence band to gain to create electron–hole pairs.

Base: The middle area of a BJT. It is n-type in pnp and p-type in npn. The base should ideally be very narrow and lightlydoped. It is the control terminal for the BJT. Base current should be very low in the active region, but can be large insaturation.

Base transport factor: In BJT, the ratio of majority carriers injected from the emitter in active mode that manage to reachthe collector. The ratio should approach 1. Those injected carriers that do not manage to reach the collector form the basecurrent.

Behavioral simulation: A simulation performed on raw HDL. The output is bit-accurate and cycle-accurate. Thus thesimulation allows full confirmation of the functionality of the circuit, and of the integrity of the pipeline. It does not,however, contain any timing information. Thus using any arbitrary clock period will not affect the output of the simulation.

Bipolar Junction Transistor (BJT): A transistor formed by combining two back-to-back asymmetric PN junctions. Whenacting as a transistor, the BJT does not act as two PN junctions, with asymmetries in doping and geometry playing anintegral role in operation. BJTs are rarely used in modern technology. Their integration is difficult and their fan-out is limitedby base current. However, they provide a large current and have favorable parasitics, leading to good frequency response.

Bird’s beak pattern: A triangular (prism-like) pattern formed when growing field oxide in LOCOS. The triangular areaforms because oxidation tapers down toward the sacrificial nitride. The beak lifts the nitride, the thicker the field oxide, themore lift. This introduces a fundamental contradiction between the thickness of field oxide and the device feature length.

Bistable circuit: A circuit for which both logic output values are stable. The circuit can indefinitely maintain either of itsstates. The most common bistable circuit is an even number of CMOS inverters connected in positive feedback. Bistablecircuits form the basic static storage mechanism in CMOS.

Bit (VHDL): The default data type in VHDL. A signal of bit type can only take the values “1” and “0”. Because it does notoffer any subtle information about the electrical state of the signal, this data type is seldom used, with the std_logic typebeing preferred in all cases.

Bit-line: The vertical line that runs across a column of memory. The bit-line is always connected to the outputs of storagecells. Thus bit-lines carry output values from memory. Bit-lines are driven by the cells or the column buffers and feed eitherthe cells or the sense amplifier/column decoder. Bit-lines are usually made of metal to reduce resistive loading. Theexception being DRAMs where bit-lines can be made of diffusion or polysilicon.

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Bit_vector (VHDL): A vector of bits of the “bit” type. This corresponds to a bus of the bit type. The whole bus, ranges, orspecific bits can be referenced.

Body effect: A secondary effect where the source to body potential modulates the threshold voltage of a MOSFET device.The body terminal of all MOSFETs of the same type are shorted. However, sources are defined by circuit connections. Thisleads to disparities in the threshold voltage of devices, having a potentially significant effect on operation. Body effect occursdue to the source impacting the quasi-Fermi levels for inversion in the substrate. In technologies with steep retrogradedoping, the body effect is significantly more pronounced.

Body effect parameter: A technology-determined parameter that controls the impact of body effect. Its unit is square rootof volt. It is affected by the permittivity of silicon, body doping, and oxide capacitance per unit area.

Bohr model: A model for an atom where there is a central immobile nucleus consisting of protons and neutrons orbited byelectrons. The electrons occupy circular orbits whose radius is defined by their energy. Energy takes discrete values.

Booth encoding: A method of encoding binary words to make multiplication simpler. Overlapping pairs of bits aresystematically encoded as 0, 1, or −1. Booth encoding greatly simplifies multiplication when the multiplier (operand) haslong strings of 1’s or 0’s.

Booth multiplication: Multiplication operation performed if the multiplier is Booth encoded. The multiplicand should beleft as vanilla binary. Booth multiplication requires partial products to be formed not only due to multiplication by 0 or 1, butalso by −1. This is not a significant hardware cost.

Boundary scan technique: A testing technique for assembled systems on a printed circuit board. It is analogous to the scantechnique and is usually used in conjunction with it to facilitate testing at different levels. In the boundary scan technique, allpins in a chip are supplemented with boundary scan registers. Three additional pins are used: Test Data In (TDI), Test DataOut (TDO), and Test. The chip pins operate in parallel mode when Test = “0” and operate as a shift register, regardless oftheir type, when Test = “1”. The PCB is supplemented with an independent boundary scan path that connects all chips incascade. This allows pins to be loaded or unloaded independent of normal operation. This increase in controllability andobservability allows individual chips to be tested as well as testing pins and board tracks.

Brent–Kung adder: A type of parallel prefix adder. It is more irregular than Kogge–Stone adders. Its delay also growsslightly faster. It can also impose higher fan-out on some stages. However, BK adders have much simpler routing than KSadders, and their area is lower.

Bridge fault: A type of coupling fault in memories. It is the simplest type. The value in a cell copies the value in anothercell. This is rarely, if ever, due to a physical short defect between the two cells; but is more commonly due to capacitivecoupling. Coupling faults can be reciprocal or directional.

Built-in self test: A test setup that has been built into the hardware of a die. This is normally combined with automatedtesting so that the die can test itself rather than needing an external controller. The BIST setup normally includes ATPG,signature analysis, and a controller.

Built-in field: An internal field built in within the material. Because it does not exist due to external sources, the Fermi levelremains constant and the material remains at thermal equilibrium. No net current flows although current components mayflow and cancel each other out. Built-in fields are often due to the charges in space-charge regions.

Built-in potential: An equivalent potential due to a built-in field. It cannot be externally measured, it does not reflect on theFermi level, and is not associated with net current flow. However, it manifests in the form of band bending.

Bulk potential: The potential corresponding to the energy of the difference between the Fermi level and the intrinsic Fermilevel deep in the bulk of a MOSFET.

Bundle effort: In a gate with multiple inputs, it is the logical effort due to a group of inputs activated simultaneously. This isusually invoked when an input and its complement are present in the gate.

Buried gate: A conceptual gate buried below the channel. The buried gate is not floating, it is shorted to the main gate.Buried gates are not practical structures, but are used in a thought experiment to understand how multi-gate transistorscombat drain induced barrier lowering. This must be distinguished from floating gates in NVMs.

596 Glossary

Carry bit: In an adder, it is an output bit that is produced in the next bit position. Carry logic is fairly simple, being an ANDgate for half adders and a simple sum of products in full adders. In an N-bit binary adder, a carry bit is always an input to afollowing building block, except for the last bit position where it becomes part of the overall adder output.

Carry-bypass adder: A relatively fast N-bit adder. The adder is divided into smaller blocks. The carry chain in each blockis allowed to bypass the entire block if every location within the block is propagating. This can improve the critical path ofthe adder by reducing the slope of linear growth relative to ripple carry adders.

Carry save adder: A relatively fast N-bit adder that sacrifices area for speed. The adder is divided into smaller blocks. Eachcarry chain in a block is duplicated, calculating the outputs given a carry-in of “0” or “1”. Once actual carries begin to exitthe earlier blocks, they can be used to multiplex the outputs of the duplicate chains. If the blocks are of equal size, carry-savedelay grows linearly with the number of bits, albeit at a better slope than ripple carry adders. If blocks of different sizes canbe used, sublinear delay scaling can be designed.

Case (VHDL): A conditional statement construct that can only be used inside a process. Its syntax is very reminiscent ofprogramming languages. It can also be used to create multiplexers. Strictly speaking, case statements create priorityencoders. Case statements are preferable to if-else trees when the number of possible choices is very large.

Cell (memory): The smallest building block of memory, capable of storing a single bit. A cell exists at the intersection of aword-line and bit-line. Each intersection of a word-line and bit-line is a cell regardless of what the cell contains. Cells mustbe maintained small to promote memory density, however, cells are also responsible for driving the huge capacitance ofbit-lines, introducing a major conflict in cell sizing.

Cell delay replica: A dummy circuit that copies the delay of the cell driving the bit-line. It does not have to have the sameconstruction of the cell/bit line, it just needs to mimic their delay. It is used to delay the sense amplifier and enable signal inself-timed memories.

Chain fan-out: For a chain of logic gates, it is the ratio between the output capacitive load the chain is driving, to the inputcapacitance of the first stage in the chain. It is simply the fan-out of the chain if the chain is considered a single black box.

Chain logical effort: In a chain of logic gates, it is the product of the individual logical efforts of the gates in the chain. Itrepresents the total difficulty of driving the complexity of the logic in the chain relative to a chain of inverters.

Chain total effort: The total effort expended over a whole logic chain. It is the product of all the individual stage fan-outsand stage logical efforts. It is also the product of the chain logical effort and the chain fan-out.

Channel length: The length of the MOSFET channel, also the shortest distance between the source and the drain under thegate. Channel length impedes current flow and increases resistance. It is roughly the length of the top plate of the MOScapacitor, typically slightly smaller due to the extension of polysilicon over source and drain.

Channel length modulation: A secondary effect that affects MOSFETs where the saturation current becomes a weakfunction of drain potential. Channel length modulation has many physical causes, including finite depletion region resis-tance, ballistic transport, and tunneling. It is hard to derive, but empirical models exist. Channel length modulation isparticularly dire in short channel transistors.

Channel width: The depth of a channel. The wider the channel, the more current the MOSFET can carry and the lower itsresistance. This is also the width of the top plate of the MOS capacitor.

Characteristic impedance: The ratio of voltage and current of a single wave traveling through a transmission line. In VLSI,this is interesting because it provides a value to which the source of a large wire has to be matched to prevent source-sidereflections.

Charge carrier: A charged particle that is free to move under the effect of a field or concentration gradient. Charge carriersmust have a small effective mass to be able to move. In the context of semiconductors electrons and holes are the chargecarriers. Charge carriers are important because they carry current.

Charge conservation: In a closed system of capacitors, the total charge on the upper plates must be constant regardless ofhow the capacitors are reconfigured. By closed system we mean one where the upper plates have no paths to ground orsupply.

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Charge sharing: In a closed system of capacitors, charge conservation must be observed. Thus, if the capacitors arereconfigured, while keeping the system closed, the total charge remains constant. However, the charge may be shared amongthe capacitors to satisfy the new connections.

Circuit under test: The circuit, sub-circuit, system, subsystem, or unit being tested in a test setup. This can be a chip or anassembled PCB when considering automated testing. It can be a chip core when considering built-in self tests, and it can bean HDL construct during verification.

Clean room: An environment where the flow and exchange of air is controlled so that the contained air has fewer than amaximum limit of particles of a certain size. This is achieved by passing clean air into the room through high efficiencyfilters, and by exchanging the contained air at a very high frequency. Clean environments of the highest order are necessaryfor IC fabrication. Lower quality rooms may be used for packaging, PCB fabrication, and assembly.

Clock: A periodic signal used to time events in a synchronous circuit. The clock is used to time cycles in memories, and toprovide enables for registers, latches, and dynamic logic. Although it is often considered a square wave, the clock is in realitymore akin to a sine wave.

Clock domain: A subsystem or group of circuits where a certain clock is used. Circuits within the clock domain can beconsidered synchronous, skew notwithstanding. Exiting the clock domain requires synchronization.

Clock jitter: A phenomenon where the phase of the clock changes from cycle to cycle. It is a form of phase noise that canoccur at the source of clock generation or in the distribution of the clock. It is a stochastic temporal phenomenon. Clock jitteralways worsens the frequency of operation.

Clock network: A network used to route the clock to all registers and gates in a synchronous circuit. The clock network hasan enormous load due to the large number of registers supplied. The wires in the network are in the metal layer. The aims ofthe clock network are to reduce area, skew, and power, as well as increasing modifiability.

Clock overlaps: Because clock’ is obtained from clock through an inverter there is an inevitable delay between the two.This delay leads to small but very important periods where the two signals have identical values. These periods are known as1–1 overlap and 0–0 overlap. They lead to signal-clock racing if not properly addressed. Clock overlap is the main reason weneed to impose hold-times on signals.

Clock skew: A phenomenon where the clock observed at different registers has a phase shift. This happens not only due todelay in the wires of the clock network but also due to buffer and load mismatches. Clock skew can intensify or alleviatesetup and hold-time conditions depending on the direction the clock is distributed relative to data. Clock distributionnetworks aim to reduce either the absolute skew seen at all registers or the relative skew of neighboring registers. Skew is adeterministic spatial phenomenon.

Clock spine: A line of buffers that distribute a clock signal across a single dimension. The spine can achieve incredibly lowskew, but it can only send the clock across a single line. To distribute the clock to the rest of the circuit, the spine must becombined with another method of clock distribution.

Clock tree: A method of clock distribution where the clock is driven across a tree of branches. Clock trees aim to reducerelative skew only; skew between registers at different levels of the tree can still be significant. Trees are highly coupled tothe underlying design, making modification difficult. However, their area and power consumption is moderate.

Clustered defects: Defects that are concentrated in a certain area of a wafer. This usually indicates a systematic problem inthe fabrication process. Clustered defects may not have as major an impact on yield as random defects.

CMOS: Complementary metal-oxide semiconductor. A ratioless logic family where the nominal outputs are rail to rail.CMOS gates have complementary connections in their pull-up and pull-down networks. They have as many NMOS as thereare PMOS. CMOS gates exhibit excellent noise margins, signal integrity, and steady-state static power consumption.However, they have dismal area and delay performance. Properly designed CMOS gates should observe zero short-circuitcurrent in the steady state.

598 Glossary

CMP: Chemical-mechanical polishing. A process whereby a surface is polished to incredible evenness. A mix of chemicaland mechanical methods are used. Abrasive and corrosive materials are used to aid the process while shaking, vibration, androtation are used to enable polishing. CMP is integral to modern processes due to the need to keep successive metallizationlayers flat. CMP is extremely dirty and is kept separate from the rest of the CMOS process.

Collector: The more lightly doped of the peripheral zones of a BJT. It is n-type in npn and p-type in pnp. The collectorshould have a very large common area with the base to facilitate the collection of injected emitter carriers. In the activeregion, the collector current should approximate and track the emitter current.

Column decoder: A multiplexer used to choose one bit-line out of all the columns in the memory bank. The columndecoder is provided a part of the address bus as select lines. The column decoder can also be used as a demultiplexer inread/write memories to direct the write value from the data-in bus to the column driver of the appropriate bit-line.

Column driver (memories): A large buffer at the end of each column, They are used only with RAMs. They drive thebit-line to a certain drive value, allowing the value to be written to the cell. Column buffers are formed of inverter chainssized using the logical effort technique.

Combinational logic: A logic gate whose output is an unconditional Boolean combination of its inputs. Outputs ofcombinational gates change in response to any of its inputs changing. The change is not instantaneous, and happens after apropagation delay, however, it is unconditional.

Combinational logic block: A block consisting entirely of combinational logic. In a pipeline, a CLB lies sandwichedbetween two registers. A combinational logic block is primarily characterized by its worst and best-case delays.

Common base current gain: The ratio of collector current to emitter current. The balance is wasted on base current. This istightly related to emitter efficiency, the difference being that the currents in common base current gain are total currentsrather than majority carrier flows.

Common emitter current gain: The ratio of collector current to base current. Since the base current should be extremelylow, this ratio should be very high. Three figure CE current gain factors are typical.

Component (VHDL): An entity when it is used as a component in another entity. This is the basis of hierarchical design inVHDL. The component informs the entity where it is declared that instances of the component may be declared within thearchitecture. However, it does not convey information about the number of such instances or their locations and connections.

Concurrent statements: Statements that are executed in parallel. Although the statements are written in a certain sequence,the sequence has no value and can be changed without affecting the result. Concurrent statements are ideal for describinghardware setups, and are thus the foundational philosophy of hardware description language syntax.

Conduction band: The lowest empty energy band in a solid material at 0 K. At temperatures above 0 K, it may containconduction electrons depending on the bandgap. The concept is not well defined for metals.

Conduction band edge: The lowest energy level in the conduction band. Free electrons left to their own devices prefer toreside at this level if it is available. The distance between the Fermi level and this level is a very good indicator of electronconcentration.

Configuration (VHDL): Configurations are VHDL constructs used to manipulate entities in preparation for instantiation.They are used for two purposes. First, to associate instances in the design with certain architecture–entity bindings. Andsecond, to rename entity ports before they are used as components. Configurations are useful in large designs and incommercial settings when multiple teams are involved in the design. In more manageable designs, configurations are rarelyuseful.

Constant (VHDL): In VHDL, it is a named item that holds a constant value of a specific type. Constants can be derivedfrom other constant values through function calls, just as long as all derivations can be resolved at synthesis time. They aredeclared in the architecture.

Contact exposure: A classical exposure mechanism where the photomask is brought in contact with the wafer. Opticalartifacts are avoided, but contact with the photoresist dirties and damages the masks. Features on the mask must correspondone to one to features on the wafer.

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Contact mask: The photomask used to create contacts or vertical holes between the active layer and either poly or Metal1.

Controllability (testing): In the context of testing, it is the ability to impose the state of an internal node. This is usuallynecessary to apply test vectors to subsystems in order to test them. Nodes are normally not controllable unless they areprovided through input ports or pins. Increasing controllability means bringing out nodes to input ports or pins. Thechallenge is how to do this without the number of pins growing out of control.

Controller: A section of a circuit that contains the sequencing and intelligence. It contains no signal processing circuits.

Copper trace (PCB): A wide copper wire etched on a PCB to connect components mounted on the board. Copper tracksare enormous relative to wiring within dies. This introduces an asymmetric capacitive load that needs appropriately designedinterfacing at output pins.

Counter: A sequential circuit that counts in a specific sequence. Counters are very useful in establishing control andsequencing over a circuit. Counters can be declared using variables or signals. Counters can be up, down, or up/down.Special counters can also count in an arbitrary sequence, such as Gray-encoded counting.

Coupling fault: A logic fault, normally associated with memories rather than logic. They are complicated faults, difficult totest for. The value of a cell is affected by the values of a neighbor or a group of neighbors. Coupling faults come in differentflavors: bridge faults, inversion faults, and idempotent faults.

Critical dimension: The minimum dimension that can be realized by a certain exposure method during photolithography.A function of the wavelength of light used, numerical aperture, and the medium in which projection takes place.

Critical field: The value of electric field where a charge carrier reaches its saturation velocity. The critical field is a physicalconstant related to technology. It corresponds to a certain saturation drain potential, which is a function of channel length.

Critical path: In a synchronous pipeline, it is the path with the longest combinational delay between two registers. Thus it isthe maximum propagation delay for any combinational logic block in the pipeline. The critical path determines the operatingfrequency of the circuit, as well as determining whether placement and routing can close.

Crowbar current: Current that flows from the supply to the drain of a gate, typically a CMOS gate, during switching. Itoccurs due to the finite slope of input signals, which causes transistors in the PDN and PUN to be simultaneously active. Thiscurrent is detrimental to delay and power and is increasingly important. It is particularly dangerous in static CMOSespecially with short channel devices due to the increased range of device saturation.

Current: A flux of charge carriers through a conductive cross section. Current could flow due to a field or due to a chargegradient.

Custom attributes: Attributes defined by the user and attached to any named item (see attribute for a definition of a nameditem). Custom attributes are most commonly used by commercial designers to convey tool or design information. Alsoknown as user-defined attribute.

Cutoff region (BJT): A region of operation for BJTs where both junctions are reverse. A primary current does not flowthrough any terminal of the device. However, leakage currents can flow. It is used as the region of the off-switch in bipolarlogic.

Cutoff region (MOSFET): A region of operation of the MOSFET where a channel does not exist between the source andthe drain. No primary current flows between the source and drain regardless of applied source to drain potential. This regionis useful as an off-switch in logic gates.

CVD: Chemical Vapor Deposition. A deposition process in which two materials react over a substrate, yielding a con-densate on the wafer that forms a film. CVD requires heat as a catalyst and often produces toxic byproducts. Additionally,appropriate precursors are not always available for all materials. However, CVD yields incredibly good and even films. CVDis used most often to lay down polysilicon or silicon dioxide for surface features.

Czochralsky process: The most common process for obtaining silicon ingots for semiconductor wafers. High qualitysilicon is melted and suitable dopants are added and mixed in. A small crystal seed is lowered into the melt so that it justtouches it. The seed is raised with rotation, cooling causes silicon to solidify in a crystal aligned along the seed forming anelongated ingot.

600 Glossary

DADDA multiplier: A method of designing multipliers in which the parallelogram shape of partial products is ignored, andonly the relative position of bits is of significance. Half adders and full adders are used to successively compress the partialproducts until only the product remains. DADDA trees use an involved algorithm to determine the number and location ofhalf adders and full adders used at any step. DADDA multipliers offer a more balanced solution in terms of area and speedthan Wallace trees.

Damascene process: A process used to pattern copper in microchips. Copper has no suitable dry etchants. Wet etchingcannot be used due to its isotropic nature. The pattern is etched in the oxide instead, and copper is deposited to overflow thepatterned trenches. CMP is used to polish down to the metal layer. The double damascene process creates copper wire andcopper vias simultaneously

Datapath: A section of a circuit that contains all the digital signal processing sections. The datapath cannot contain anycontrol or sequencing logic. It communicates with the controller through status signals, and is controlled by the controllerthrough control signals.

Decoupling capacitor: A large capacitor introduced between supply and ground in a chip. It helps in resolving ground andsupply bounce. The capacitor is a virtual open circuit for true ground and supply. Large and fast changes in current, however,observe a very low impedance in the capacitor. These currents are thus absorbed in the capacitor, where they can then leakslowly to the pins. If the decoupling capacitor is introduced inside the chip, it can decouple inductances within the package,otherwise it only decouples PCB and pin inductance.

Defect: A physical issue within a die that departs from the expected fabrication outcomes. Defects can occur due to a varietyof reasons including mask misalignment, process variations, temperature variations, electromigration, and a host of otherissues. A defect is not considered significant unless it manifests as a deviation in the behavior of the circuit.

Defect level: The number of defective chips that are shipped to customers. This is a strong function in fault coverage as wellas yield. It is measured in parts per million. A DL of less than 500 ppm is considered acceptable for commercial processes.DL less than 100 ppm is considered very low defect. DL less than 30 ppm is considered virtually zero defect and isassociated with very mature processes or specialty applications.

Delete (adders): A state for a full adder where the carry-out is “0” regardless of the value of carry-in. Whether the FA is indelete state can be deduced exclusively from the operands. So all deletes for all bit positions can be calculated in parallel atthe start of operation. Knowing only two of the three states: generate, delete, and propagate is sufficient. This is because thethree are mutually exclusive, yet form a complete set. Most adders only use generate and propagate signals, with delete statebeing implied by neither generating nor propagating.

Density of states: A function that describes the density of states per unit volume at a certain energy level E. The densitygenerally increases away from the edge of the band.

Density rules: A special design rule which imposes a minimum density of features at every layer. This is most common inthe metal layers, especially in copper patterning. If wires are not dense enough, deep valleys can form when depositingoxide. This causes CMP to fail to create a smooth surface between metal layers. When density falls below a certain limit,dummy lines must be inserted to raise it up to limits.

Depletion load logic: A ratioed logic family where the driver is an NMOS and the load is a depletion mode NMOS.Because the depletion NMOS does not need to be diode connected to function, this family has superior performance toenhancement load logic. Logic low value is nonzero, but logic high value is at supply. Static power dissipation is high.

Depletion mode: A mode of the MOS capacitor where carriers are removed from the surface. Carrier concentration at thesurface drops below flat band levels. They leave behind ions that form an insulating depletion layer. The depth of the layerincreases with the application of more gate potential until strong inversion sets in.

Depletion MOSFET: A MOSFET with an implanted channel. Thus the transistor is on at zero gate voltage. To turn thetransistor off, a negative (for NMOS) gate voltage needs to be applied. This causes the threshold voltage to be the opposite ofthe expected sign, negative for NMOS and positive for PMOS.

Glossary 601

Depletion region: Also known as space-charge region. This is an area of a doped semiconductor in which the majoritycharge carriers have been removed, usually under the effect of an external or built-in field. The depletion region is very lowon charge carriers, thus its conductivity is low (close to that of intrinsic silicon). Because the charge carriers leave behinddopant ions, the depletion region also has net volumetric charge. Depletion regions have insulating properties; they are alsocharged and tend to form built-in fields. However, depletion regions are not strictly insulators because their bandgap energyis moderate. If a favorable field exists and charge carriers exist at the periphery of the depletion region, current will readilyflow through.

Depth of focus: The acceptable range within which a wafer has to be placed so that light from a lens can be projected withacceptable focus.

Design rule check (DRC): One of the final steps of the ASIC design flow. The layout is examined against the design rulesof the vendor. If any violations are found, they are reported as DRC violations. Most vendors will not accept layouts that arenot DRC violation free.

Design rules: A set of rules about the width, separation, density, and enclosure of different layers. Some design rules applyto a single layer, some describe relations between layers. Design rules are necessary to guarantee a nominal yield from theprocess. The rules aid CMP, prevent antenna damage, protect against misalignment, and ameliorate electromigration.

Destructive read (DRAM): In DRAM, it is the effect where reading from a cell leads to the destruction of the stored value.This occurs when the reading mechanism is charge sharing. Destructive reads require each read operation to be followed byrewriting the read value, thus significantly increasing the delay of DRAM. Destructive read is inevitable for one transistorDRAMs.

Development (photoresist): The process of stripping away soluble parts of photoresist from a wafer. Development isachieved by dipping the wafer in a development liquid. Proper development depends on a balance of baking, exposure, anddevelopment liquid dipping.

Diagnosis: When an observation does not match the gold standard, the circuit is judged to have a fault. Diagnosis is theprocess of determining where the fault originates in the circuit.

Die: A square area on a wafer which is sliced and then mounted on a package to form an integrated circuit. The die containsall the core functionality of an IC.

Diffusion: The physical phenomenon in which particles move from areas of higher concentration to areas of lower con-centration. Diffusion stops once there is no gradient left and particle distribution is uniform.

Diffusion (layer): Alternative name for active layer. This is strictly a misnomer since diffusion is not used in either buildingthe thin oxide or in doping the source and drain.

Diffusion (photolithography): A process whereby particles are inserted into a feature by virtue of a high concentrationgradient. Diffusion creates very inaccurate features both in terms of size and concentration. Its main use is in well doping.

Diffusion current: The current resulting from the diffusion of charge carriers through a crystal structure.

Diffusivity: A physical constant that represents how easy it is for charge carriers to diffuse through a crystal. This isprimarily a function of imperfections in the crystal, mainly dopant concentration. It is easier for electrons to diffuse than it isfor holes.

Diode-connected transistor: For BJT, a transistor where the base and collector are shorted. This effectively reduces theBJT to a diode and restricts it to being active if on. For MOSFET, it is a transistor where the gate and drain are shorted.Although the MOSFET will not resemble a diode, the naming is inherited from BJT. The MOSFET is restricted to beingsaturated if on. Diode-connected MOSFETs are used in current mirrors or as active loads.

Direct tunneling: Tunneling that occurs across the entire thickness of an insulator. Direct tunneling is a significant sourceof leakage in deeply scaled CMOS.

Domino logic: A method of building dynamic logic gates where the building block is a dynamic gate followed by a smallstatic CMOS inverter. Domino logic prevents loss of charge associated with cascaded dynamic CMOS stages.

602 Glossary

Donor: A dopant from a higher group than the semiconductor. For elemental semiconductors, donors come from group 15.They donate an extra electron to the semiconductor without creating a corresponding hole. This significantly increases theconductivity of the material and makes the concentration of electrons much higher than the concentration of holes.

Dopant: An intentional impurity inserted at a very low concentration into a semiconductor to fundamentally change itsproperties. For elemental semiconductors, such as silicon, dopants come from groups 13 and 15.

Dot operator: An operator that combines two sets of group generates–propagates into a larger group generate–propagate. Itis, in fact two operators, one that acts on generates, and another that acts on propagates. Both operators are very simpleCMOS gates. The dot operator is not commutative. It is most significant when used on two ranges that are continuous orhave overlaps. Its output would then be the group generate–propagate for the range formed by the union of the two inputranges. The dot operator is instrumental in some of the fastest adders available.

Drain: One of the four terminals of a MOSFET. It is heavily doped n-type in NMOS and heavily doped p-type in PMOS.The drain drains the carriers that flow from the source. Because the MOSFET is a symmetric device, the drain is distin-guished from the source only by circuit operation.

Drain capacitance: The capacitance seen at the drain of a MOSFET. It is primarily the depletion capacitance seen acrossthe reverse-biased PN junction to the body. Depending on the region of operation and the amount of gate-drain overlap, italso includes an oxide capacitance component to the MOSFET gate.

Drain-induced barrier lowering: A phenomenon whereby the gate loses some control on the channel in favor of the drain.DIBL is most clearly observed in shorter channels. It occurs because the application of a high drain potential over thechannel leads to a lowering of the barrier to electron flow at the source, leading to unexpectedly dense channel formation.DIBL can be observed as a drop in the threshold voltage for lower channel lengths, or as a rise in the subthreshold swing.DIBL is one of the most serious short channel effects due to its impact on leakage. It introduces a fundamental contradictionthat leaves leakage current at unmanageable levels because either subthreshold or tunneling currents have to be left at highvalues.

DRAM soft errors: The contents of random DRAM memory locations are changed by alpha radiations in the environment.This is a reliability issue. But most DRAM arrays include some form of error correction coding to handle this.

DRAM, 1 transistor: A DRAM where each cell consists of a single transistor. The transistor is not the storage device, butrather an access device. Storage takes place on a storage capacitor. The capacitor exists at the source of the access transistor.Parasitic capacitance is not high enough to carry enough charge for storage, thus an additional fabricated capacitor has to beadded. DRAM arrays can sometimes be embedded in traditional CMOS, but the properties of such arrays are inferior.Commercial DRAMs require specialized processes to linearize and increase the size of the storage capacitor withoutaffecting density. One transistor DRAM reads are destructive, and frequent refreshing is needed due to leakage. Thus DRAMis not onlt significantly slow when compared to SRAM but is also much denser. Commercial DRAM forms the majority ofmain memory for processors.

DRAM, 3 transistor: A DRAM where each cell consists of three NMOS transistors. Storage takes place dynamically at thegate of one of the transistors. Read and write bit-lines are distinct. Three transistor DRAMs have nondestructive reads. Theyalso do not require an additional storage capacitor. They are thus fairly fast and suitable for embedded memories, requiringno nontraditional fabrication steps. However their density is clearly inferior to one transistor DRAMs.

DRAM, 4 transistor: The largest of DRAMs. Each cell consists of four transistors. It is formed when an SRAM cell isstripped of its PMOS transistors. Storage takes place dynamically on one node. The cell contains a superfluous, needless, anduseless feedback path. Thus it is seldom used, being replaced in all cases by the smaller and superior three transistor DRAM.

Drift: A physical phenomenon in which free charge carriers move under the effect of an electric field. If the motion isthrough a crystal structure, the velocity is usually constant.

Drift current: The current resulting from the drift of charge carriers in a crystal structure.

Drift velocity: A relatively small but directional velocity that results from the drift of carriers in a crystal structure. Becausecharge carriers repeatedly collide with imperfections in the crystal, their velocity continuously oscillates between null andsome maximum value. Drift velocity is the average.

Glossary 603

Driver: The transistor or transistors in a ratioed gate which accept logic inputs as gate controls. Drivers change theirconfiguration depending on the input and are responsible for achieving the logic “0”s of the truth table by pulling downagainst the load.

Dual inline pin: A type of IC package. It is the simplest of packages. Pins are on the periphery of the IC, in two parallelrows along the two longer sides. Pins make a sharp, roughly 90° turn downward. DIP pins can be mounted very easily. Thepins fit through holes in the substrate of the PCB, and soldering can be done manually due to the large separation of pins.Because pins make a very sharp turn, they have to be relatively thick, at least at their base. This severely limits the maximumnumber of pins that can be fit on a DIP package.

Dummy cell (DRAM): A single cell per bit-line in DRAM containing nothing, or containing a capacitor always prechargedto the same value. Sense amplifiers are differential by their very nature. Sense amplifiers are also necessary for DRAMsbecause DRAMs can drive only a small voltage differential on bit-lines. Because DRAMs are single-ended by necessity, thedummy cells are used in conjunction. Whenever a cell is activated in a bit-line, the dummy cell is activated on the oppositebit-line to provide a differential input to the sense amplifier.

Dynamic CMOS: A logic family where the number of transistors and delay are comparable to ratioed logic families, but theVTC and static power are similar to CMOS. Dynamic CMOS will have at least one output state where the output node ishigh impedance, thus they are prone to severe signal integrity issues.

Dynamic hazard: A logical hazard that occurs as a combinational output makes a transition from “0” to “1” or “1” to “0”.Dynamic hazards indicate the presence of at least three paths for the same signal that converge in a single AND or OR gate.They are associated with structures of the form XX’ + X or X(X + X’). Thus all dynamic hazards have an underlying statichazard. The dynamic hazard can be resolved by resolving the underlying static hazard.

Dynamic latch: A latch where storage takes place on a high-impedance capacitive node, usually the input of an inverter.Dynamic latches are much smaller than static latches but suffer from signal integrity issues, especially leakage if they are notupdated frequently.

Dynamic power: Power dissipated in resistors while capacitors are charging or discharging. In long channel MOSFETs aswell as FinFETs, it is the dominant power dissipation mechanism.

Dynamic register: A register formed from dynamic latches. It is much more compact than a static register, but suffers fromsevere signal integrity issues.

EEPROM: Electrically erasable programmable ROM. An NVM where the storage device is a floating gate tunneling oxidetransistor (FLOTOX). The FLOTOX device has a particularly thin oxide on one side, traditionally the drain. Programming isperformed by hot carrier injection. Erasure is performed by exposing the drain to a high reverse voltage, causing Fowler–Nordheim tunneling into the substrate. EEPROM has bad programming and erasure times. However, it had good writecycles and could be erased in situ, which was a great improvement over EPROM. It has dismal density because it requiresthe use of two transistors per cell, one transistor being the storage FLOTOX the other being an access transistor.

Effective density of states: A single number that represents how high the density of states would have to be at the edge of aband to produce a charge concentration equal to that in the entire band.

Einstein’s relationship: Diffusivity and mobility are both primarily functions of dopant concentration. Einstein’s rela-tionship recognizes the tightly knit definition of the two and relates mobility and diffusivity.

Electrical effort: A unitless number that represents how much harder it is for a logic gate to drive itself unloaded relative toan inverter. Electrical effort is greater than or equal to 1, with only inverters having an electrical effort of 1.

Electromigration: A long term degenerative process where high current density causes the corrosion of metal wires overtime, increasing their resistance or causing them to overheat. In ASICs, electromigration is particularly dangerous in vias,where improper etching can lead to narrower openings and higher resistance.

Electron: In general, it is a negatively charged subatomic particle that exists outside the nucleus. It has a very small massand an absolute charge of 1.6 � 10−19 C. In the context of electrical current flow, electron usually refers to a free electronfunctioning as a charge carrier. In solid state, this would be an electron that exists in the conduction band and thus can moveunder the effect of an electric field.

604 Glossary

Electron affinity: The difference between the vacuum level and the edge of the conduction band. It represents the amount ofenergy necessary to free the least energetic free electron from the material. Electron affinity depends only on the crystalmaterial, and is independent of doping.

Electron affinity rule: The electron affinity at either side of an interface should preserve the electron affinity values for thetwo materials. The vacuum level must be continuous. A corollary of the rule is that discontinuities in the CB edge and VBedge at the interface are normal and expected.

Electron current: Current due to the motion of electrons in the conduction band. This could be diffusion or drift current orboth.

Elmore time-constant: A method to calculate an equivalent time-constant in a circuit with multiple capacitors and resistors.It is calculated by multiplying each capacitance by the resistance seen in intersection with the path to the output node. TheElmore time-constant method works only for circuits with no loops. It is very useful for modeling delay in CMOS gateswhere internal node capacitance is significant. It is also useful in modeling delay in interconnects with significant resistance.

Emitter: The more highly doped of the peripheral zones of a BJT. It is n-type in npn and p-type in pnp. The heavy dopingmeans that significantly more carriers are injected from the emitter into the base than vice versa.

Emitter efficiency: The ratio of majority carriers to total carriers in the emitter current. If the emitter doping is heavyenough, this ratio should approach 1.

Empty flag: A FIFO flag that indicates the FIFO is empty. It signals the receiver to stop reading because no unread dataexists in the memory. The FIFO is judged empty when an update to the read pointer causes it to equal the write pointer. Theempty flag is calculated from a combination of two pointers from two different clock domains, requiring the use ofsynchronizers.

Enhancement load logic: A ratioed logic family where the driver is an NMOS and the load is a diode-connected NMOS.The family has the advantage of consisting entirely of normal NMOS transistors. However, it has terrible steady-stateperformance. Logic low output is ratioed, logic high output loses a threshold drop from the supply. Static power dissipationis high. The transition region of the VTC is wide and the noise margins are small.

Entity (VHDL): The smallest building block in VHDL. It declares the existence of a certain circuit with certain ports. Itoffers no information on the internal construction of the circuit, nor does it suggest the number of instances of such circuitused. One way to abstract the entity is to consider it as a description of the black box associated with the circuit.

Enumeration (VHDL): A user-defined data type in VHDL where a signal can take values from a finite set of textual labelsdefined by the user. The labels have no correspondence to actual hardware realization, which is usually left to synthesizeroptimization. Enumerations are most often used in state machines where they allow state signals to be manipulated usingstate names instead of binary strings.

EPROM: Erasable programmable ROM. An NVM of historical importance. Devices were double gate, but the oxide wasfairly thick. Avalanche injection was used for programming transistors. Erasure required exposure to UV radiation. Erasurewas particularly problematic. It could not be erased in situ, and required special packaging with a transparent window forexposure. It had good programming speed and density, but very bad write cycles and erasure times.

Erasure (NVMs): The act of returning the state of a cell in a nonvolatile memory to its default by returning the state of thecell transistor to default. This is usually achieved by pumping charges out of the floating gate into the substrate. This isachieved by UV exposure or Fowler–Nordheim tunneling.

Error: An error is the deviation of an output in a unit under test from the expected output due to a fault.

ESD protection: Electrostatic discharge protection. An important part of input pin pad interface circuitry. An input pin canaccumulate a lot of static discharge, especially when handled by human operators. If this static charge seeps to the firstMOSFET gate in the die core, it would easily break down the thin oxide, leading to catastrophic failure of the chip. ESDprotection is provided in the form of two diodes. In normal operation, these diodes are comfortably reverse biased. If enoughstatic charge accumulates, however, the diodes break down reversibly, allowing the extra charge to leak to the substratebefore the MOSFET oxide breaks down.

Glossary 605

Etching, dry: Using plasmas to eat away a material according to a certain pattern. This is almost exclusively used to patternsome metals like aluminum. Dry etching is directional, achieving incredibly good and dense patterns. It also leaves behindno residue. On the other hand it leaves significant amounts of static charge, requiring tough antenna rules. Very fewmaterials can be dry etched, even some metals like copper cannot be properly dry etched at a suitable temperature.

Etching, wet: Using wet solvents to eat away a material according to a certain pattern. The etchant is usually an acid.Materials patterned by wet etching are usually either silicon dioxide or silicon. Wet etching tends to be nondirectional, thuscreating significant lateral etching. It can also be dirty, requiring wafers to be cleaned afterward.

Euler path: As it relates to stick diagrams, it is a path that visits every transistor in both the PUN and PDN while visitingevery node at most twice. If a Euler path is found to cover the entire PDN and PUN, then the stick diagram (and layout) canbe drawn using a single diffusion strip per network. If multiple paths are necessary, then as many strips as there are paths arenecessary.

Evaluate phase: In a dynamic CMOS gate, the clock phase where the output node evaluates the logic. The output nodecapacitance either loses its precharge or keeps it depending on the logic. If the precharge is kept, then the node is in highimpedance.

Event (VHDL): An actual change in a signal value. In a process this will not happen until the end of the process if asensitivity list is used or until the next wait statement is observed otherwise.

Exit (VHDL): A VHDL loop manipulation construct. It causes the loop break and exit regardless of the loop condition.While not particularly unsynthesizable, it can yield unpredictable hardware.

Exposure: The process of exposing the surface of a wafer to light through a photomask. The light is usually very lowwavelength ultraviolet. It must take place in a photographically pure environment to prevent the photoresist from beingcontaminated.

External loading: Capacitive loading imposed on the output of a gate from external sources. In CMOS, this is usually theinput capacitance (gate capacitance) of the following stage.

Failure rate: The rate at which a system fails. For a successful system, the failure rate should be measured in failures peryear or decade. For most electronic systems, a failure cannot be recovered from and represents the system outliving its usefullife. The failure rate of a system is highly variable through its lifetime, being very high during introduction, droppingsubstantially in useful life, and then rising again in late life.

Fall time: The time it takes for a signal to drop from one to zero. In other words, the dropping slope of the wave.

Fan-out (BJT): The maximum number of stages that can be connected to the output of a bipolar logic gate. The limit isimposed by base current, which draws output current from the gate, reducing the high logic output.

Fan-out (CMOS): The ratio of the size of the next stage in a logic chain to the size of the current stage. It is also the ratio ofthe input capacitances of the gates because capacitance is directly proportional to size. In fact, the ratio of capacitances is themore systematic definition of fan-out for CMOS.

Fast–Fast corner: A corner case where a finished chip has NMOS and PMOS that are both faster than the nominal valuessuggested by the design flow. This is usually due to better than expected mobility. Fast–Fast corners produce faster thanexpected chips, which can be binned as “higher quality” and sold as higher priced high speed grade pieces. But untested fastcorners can also lead to unplanned hold-time violations, which lead to catastrophic failure of the chip.

Fault: A fault is a model of the deviation of the behavior of a circuit due to a defect. The model can be at different levels ofabstraction. Faults can be at the system, logic, or transistor (circuit) level. A fault is not always indicative of the nature of theunderlying defect, it is just indicative of how the defect manifests at a certain level of abstraction. A fault is significant if itleads to an error.

Fault coverage: The percentage of possible faults discovered when a certain number of tests are applied. In a circuit with kinputs and m states, all faults are discovered by applying 2(k + m)tests. Applying fewer than the full set of tests couldpotentially result in less of the possible faults being covered. The percentage covered is called fault coverage.

606 Glossary

Fermi level: The average chemical energy of electrons in a material. It is also defined as the energy level at which theprobability of finding an electron is 0.5. Alternatively, it can be defined as the energy level at which the probability of findingan electron is equal to the probability of finding a hole. The Fermi level does not have to be a true and valid energy state, it isjust a value. For semiconductors, Fermi level is not a valid state, but lies in the forbidden gap.

Fermi–Dirac function: Probability distribution of finding an electron at a certain energy level. It is a probability conditionalon the existence of a suitable energy level, thus it does not indicate an absolute probability value.

Field oxide, FOX: The thick, insulating oxide grown over non-active areas of the wafer. This is obsolete in shallow anddeep trench technologies, but in LOCOS it signifies areas where a transistor does not exist and is instrumental in preventinglatch-up.

FIFO: A nonrandom access memory. Data can only be accessed on a first-in-first-out basis. The core of a FIFO is a simpleshift register or RAM. But FIFOs have additional flags and pointers. The read pointer indicates the next read location, thewrite pointer indicates the next write location. There are also two flags: the full flag indicates the memory is full and can nolonger accept more inputs. The empty flag indicates the memory is empty and can no longer be read until it is written toagain. The FIFO usually has two ports, each port is designated as either read or write.

FinFET: A MOSFET structure built on a thin protruding fin instead in the bulk of the wafer. The gate forms an inverted Ushape over the fin, thus enclosing almost the entirety of the channel. This allows the gate to maintain significantly morecontrol on the channel than the drain. FinFETs thus allow the oxide to be made thicker, reducing tunneling current. FinFETsare so good at battling leakage that dynamic power becomes the dominant power dissipation mechanism.

Fixed-point number: A number representation where the position of the binary point is fixed. Thus all numbers must havethe same number of integer and fraction bits. Fixed-point arithmetic hardware is very efficient. Most ASIC registers storefixed-point numbers.

Fixed-point simulation: A simulation where all numbers are represented in fixed-point and where all operations arefixed-point. A fixed-point simulation allows system level designs to be translated into a form more suitable for hardware. Italso allows a systematic study of the effects of quantization noise, allowing the designer to choose register sizes. A properfixed-point simulation should be bit matched to the expected output of the hardware.

FLASH: A category of NVMs which combine density with ease of programming and erasure. There is a single device percell. The device is a double gate transistor with very thin oxides. Programming is performed by hot carrier injection orFowler–Nordheim tunneling. Erasure is performed only by Fowler–Nordheim tunneling. Because no access transistor ispresent, erasure cannot be performed on a per cell basis, and entire blocks of memory must be erased at once. FLASHmemories are versatile and compact, and form the bulk of mass storage in consumer electronics. However, they arecomplicated and require a lot of monitoring circuits to manage the drift of threshold voltages with use.

Flat band diagram: The band diagram of a device when all energy levels are flat. This is not the equilibrium band diagramand the Fermi level will exhibit discontinuities. The flat band diagram is of little theoretical significance, but it represents thestate where all built-in fields in the device are neutralized. It is systematically characterized by a flat vacuum level.

Flat band potential: The total amount of built-in potential at thermal equilibrium. In a MOS capacitor, it is also theopposite of the gate to body potential that needs to be applied to bring the device to flat band state.

Flattened design: A design where all parts of the netlist are considered to be on the same flat level. Thus, there are nopartitions. Flattened designs allow the place and route tool to try more options than a floor planned design. However, it alsoincreases the load on the tool, increasing the risk of failure to find closure. Thus flattening is a high-risk high potential rewardproposition.

Flip chip technology: The mounting technology used with BGA ICs. Solder balls are mounted on exposed metal pads inthe chip. The chip is then flipped over and aligned to the PCB footprint of the chip. Heating is used to melt the solder balls,causing them to bond to copper tracks on the PCB. An insulating polymer is injected to cover and protect the bottom of thechip.

Glossary 607

Floating point number: A number representation where the position of the binary point is flexible. The number isrepresented as a base and a mantissa. Floating point numbers allow a very large range of numbers to be represented.However, efficient use of floating point requires large width registers. Thus, they are rarely used in ASICs, but are commonin general purpose processors.

Floating point simulation: Simulation performed using floating point numbers and operations. High level programminglanguages can be used to perform the simulation, making it very easy to write, debug, and modify. Floating point simulationsonly capture the functionality and algorithmic-level information. There is no information that aids the hardware design,beyond a description of the target system at a functional level.

Floorplanning: Assigning parts of the chip area to partitions. Just as partitioning is optional, floorplanning is optional.Floorplanning is challenging because we must maintain a certain area and aspect ratio for the die. Partitions must also beplanned properly so that the ones that communicate more frequently are placed next to each other.

For (VHDL): A VHDL looping construct. It can only be used within processes. It has syntax very similar to programminglanguages. While loops are generally synthesizable, the resulting hardware can often be unpredictable.

For-generate (VHDL): A structure that allows for multiple component instantiations to be declared using succinct code.The structure is not strictly a loop, and will be translated into parallel hardware.

Forward-biased PN junction: A PN junction where an external voltage is applied with a positive polarity on the P side.The depletion region is narrowed. The built-in field is weakened. The barrier to majority carriers on both sides decreases.Majority carriers on either side diffuse in exponentially large numbers, leading to the flow of a large current.

Fowler–Nordheim Tunneling: Tunneling that occurs across a triangular band. This occurs when an insulator is severelytilted; this causes a section of the insulator band to appear as a triangle. This causes its effective thickness to be diminished,raising the probability of tunneling. The extreme tilting is associated with the application of a large electric field. F–Ntunneling is an important source of leakage, especially source to drain leakage. But it is more significant as aprogramming/erasure mechanism in nonvolatile memories.

FPGA: Field-programmable gate array. An implementation platform that stands in the middle between ASICs and generalpurpose processors. FPGAs combine the flexibility and ease of design of processors with the performance of ASICs. Insteadof standard cells, an array of configurable logic cells is programmed based on a programmer file. Interconnects are alsothrough programmable routing channels. The design flow for FPGA is analogous to ASIC design flow. The initial HDLdesign should be nearly identical for both FPGA and ASIC if good design practices are followed.

Full adder: A building block for adders which accepts three inputs and produces two outputs: a sum and a carry. In largeradder, two of the input bits come from the operand while the third is a carry-in from a previous bit position. Full adders aresometimes called 3:2 compressors. They are significantly more common than half adders, forming the bulk of N-bit addersand array multipliers. Full adders are also much more complicated than half adders, so every opportunity that they can bereplaced by the latter should be used. Full adders are actually two fairly independent CMOS gates: a sum gate and a carrygate.

Full flag: A FIFO flag that indicates the FIFO is full. It signals the transmitter to stop writing because any further writingwould overwrite data that the receiver has not read. The FIFO is judged full when an update to the write pointer causes it toequal the read pointer. The full flag is calculated from a combination of two pointers from two different clock domains,requiring the use of synchronizers.

Function (VHDL): A subprogram in VHDL. Functions can have multiple arguments but can only return a single value.They can only use variable declarations and assignments. Functions are synthesizable if all their statements are synthe-sizable. Functions are most often used to perform calculations and transformations that reduce to constant values at synthesistime.

Gate: One of the four terminals of a MOSFET. It is the metal/polysilicon plate of the MOS capacitor. It is the controlterminal of the transistor. Since the gate is a capacitor terminal, steady-state gate current is zero. However, significantleakage does flow through the gate in modern technologies.

Gate area: The total area of a logic gate. Ideally, this should be the layout area of the gate. In some comparative studies, thetotal MOSFET-gate area can be used instead, but this is only a small fraction of the actual layout area.

608 Glossary

Gate capacitance: The capacitance seen at the gate of a MOSFET. It is the MOS capacitance that exists across the oxide. Itexists between the gate and the channel if the transistor is on or the gate and the body if the transistor is cutoff.

GDS II: Graphical Database System II. A standard file format used to communicate layout information to vendors to allowmask extraction. GDS II is a plain text format. The bulk of the file describes the vertices of polygons in every layer.

Generate (adders): A state for a full adder where the carry-out is true regardless of the value of carry-in. Whether the FA isin generate state can be deduced exclusively from the operands. So all generates for all bit positions can be calculated inparallel at the start of operation. Together with propagate, generate forms a method of conceptualizing the full adder thatallows some of the fastest adders to be designed.

Generic (VHDL): A constant that can be declared in the entity rather than the architecture. Although it is treated by the restof the entity and architecture as a constant, it remains an unknown constant until the entity is instantiated. Generics arepowerful tools and their use is encouraged. They allow highly scalable and modifiable code to be written. They alsocentralize constants, making code much easier to debug and modify.

Generic map (VHDL): Part of a component instantiation where a generic is assigned a constant value. If a generic map isnot used, the default value of the generic is used instead. Generics can be mapped to higher level generics or constants.

Global wire: A wire which connects widely spaced subsystems on a die. Because die size increases with technologyscaling, global wire delay scales very badly, usually increasing significantly as technology shrinks. This is mainly due to theterrible scaling of resistance. Global wires are usually routed in higher metal layers. These layers are made thicker and widerto alleviate the bad scaling.

Glue logic: Random logic used to connect or interface large subsystems. Its presence indicates subsystem interfaces werenot properly designed, or system partitioning was not properly considered. The presence of glue logic is undesirable becauseany modifications in subsystems requires said random logic to be fundamentally redesigned.

Gold standard: The correct output expected from a circuit or unit under test. This is the standard against which obser-vations are compared to make a judgement about the result of testing. The gold standard is usually obtained from a higherlevel simulation, necessarily a bit-accurate simulation.

Good design practices: A set of practices that are recommended for use by the designer. These practices have a range ofconsequences although most of them are optional. Not following good design practices may not cause design errors.However, it can lead to unpredictable results. Good design practices aim to restrict coding so that it is more cognizant of thehardware into which it is translated.

Ground bounce: A phenomenon where the ground of a microchip is observed to bounce up significantly, typically for ashort time. Ground bounce is distinct from resistive drops. It occurs due to inductance, particularly at the pad, pin, and PCBlevel. High frequency changes in currents are sourced to the ground lead to significant Ldi/dt drops, which cause the groundto bounce up until the currents have resolved. The danger of this phenomenon is that currents do not have to be large for it tobe observed. Bounces are especially dangerous because they can trigger latch-up.

Group generate: For a continuous range of bit positions, it is a bit that signifies that a carry is generated anywhere in therange and manages to propagate to the output of the range. Group generates and propagates are instrumental in designingsome of the fastest adders possible.

Group propagate: For a continuous range of bit positions, it is a bit that signifies whether all positions in the range arepropagating. So it signifies whether an input carry to the range would be allowed to bypass the entire range. Grouppropagates and generates are instrumental in designing some of the fastest adders possible.

H tree: A kind of clock tree where Each branch is an H shape. H trees allow a regular fractal distribution of clocks thatinherits all the merits of all clock trees.

Half adder: A building block for adders which accepts two inputs and produces two outputs: a sum and a carry. In largeradders, the two input bits are usually from the operands. Half adders are of limited use in N-bit adders, but they can be usedto optimize array multipliers. The half adder is actually two somehow independent CMOS gates: a sum gate and a carry gate.Half adders are significantly less complicated than full adders, and thus any missed opportunity to replace the former withthe latter is very wasteful.

Glossary 609

HDL: Hardware description language. A set of languages used to describe circuits. They allow behavioral descriptions,structural descriptions, or a mixture thereof. HDLs are significantly different from programming languages, particularly inthe fact that they are concurrent languages. Rather than describing a sequence of operations, HDLs generally describeconnections of hardware components.

Heterojunction: A semiconductor junction where the two sides consist of different materials with the possibility ofdifferential doping. The equilibrium band diagram will most likely exhibit discontinuities in the conduction band edge andvalence band edge that reflects different electron affinities.

Hierarchical design: Bottom up design. A larger design is made using smaller building blocks. This larger design can thenbe a building block for an even larger design. Hierarchical design allows complex circuits to be managed and implemented.It also allows debugging and modification to be simplified by requiring only a single location to be modified instead of allinstances of the target component.

High-impedance node: A capacitive node which does not have any low-impedance paths to either supply or ground.High-impedance nodes can store values, but any loss of charge is irreparable. Most high-impedance nodes arehigh-impedance only for certain periods of time, with low-impedance paths existing at other times.

Hold-time: The time after the active edge of the clock that the input of a register must be held stable. For ideal clocks,hold-time is null. However, because clocks overlap, this allows some transmission gates to remain conductive longer thanthey should. Hold-time is used to ensure that the data stored in the master latch is not corrupted due to clock overlap.

Hold-time violation: A condition where the input of a register changes too soon after the active edge, soon enough that ahold-time would not have passed. In a pipeline, this normally occurs when a very fast combinational path causes a registerinput to update too soon. Hold-time violations cannot be addressed by increasing clock period, but can be readily addressedby adding combinational delay to the offending path. Most hold-time violations are detected and addressed by the design toolwithout the designer even being aware. However, if a hold-time violation conflicts with a setup-time violation, designerintervention is necessary. Hold-time violations that occur in a finished chip are significantly more dangerous than setup-timeviolations.

Hole: An empty state in the valence band. Under the effect of electric field, valence electrons can move through this emptystate. Because it is easier to track the motion of the empty state than the motion of all the valence electrons, we define thestate as a charge carrier. Because the empty state moves in the same direction as the electric field, we consider it to have apositive charge with a magnitude equal to that of an electron.

Hole current: Current formed due to the motion of electrons in the valence band whether due to drift or diffusion.

Homojunction: A semiconductor junction where both sides are of the same material, the only difference being in the typeand/or concentration of dopants. All energy levels are continuous (though not necessarily flat) in thermal equilibrium.

Hot carrier effect: When carriers flow in a channel, they reach their maximum kinetic energy at the drain. In velocitysaturated transistors, this kinetic energy is at its maximum possible value. Thus electrons in velocity saturated transistors areextremely energetic near the drain. Velocity saturated transistors also tend to have thinner oxides, this makes the fringe fieldlines from the drain extend significantly into the oxide. Some electrons are energetic enough to cross the oxide insulatorbarrier. And the field lines are favorable. This causes electrons to flow into the oxide. In normal transistors this causeselectrons to be trapped in impurity levels in the oxide, thus increasing the threshold voltage of the device with time. Innonvolatile memories, the hot carrier effect can be used to program double gate transistors.

Hybrid clock network: A clock network that combines multiple clock distribution methods to combine their advantages.For example, a spine can be used to distribute the clock across a single dimension, then trees are used to drive the clock todifferent partitions with low relative delay. Each partition can then be covered by an alpha grid, improving the modifiabilityof the underlying design.

Idempotent fault: A type of coupling fault in memories. A transition in a cell causes the value in another cell to go to acertain value. Idempotent faults are directional, complicated, and difficult to detect and diagnose.

IEEE library: The most important VHDL library, used in almost all designs. The IEEE library defines the criticallyimportant std_logic data type. It also defines a set of functions for manipulating signals of the std_logic type. Particularlyarithmetic, comparison, and logical operations.

610 Glossary

If-else (VHDL): A conditional statement construct that can only be used inside a process. Its syntax is very reminiscent ofprogramming languages. It is used to create latches and registers, but can also be used to create multiplexers. Strictlyspeaking, if-else statements create priority encoders.

Implicit latch: An accidentally created latch. This is due to a deficient VHDL conditional statement. A common cause thatlead to the deficiency is to miss the fact that std_logic can take more values than just zero and one. Implicit latching is verydangerous because it can complicate placement and routing needlessly. Implicit latches are caught and highlighted by allsynthesis tools although they do not cause synthesis failure. Implicit latches should be addressed and removed.

Impure function (VHDL): A pure function is a function whose return value is determined exclusively by its arguments.Impure functions on the other hand can have other external factors affecting their returns. This is particularly the case whenthe function uses a shared variable or opens a file.

Infant mortality: The earliest phase in the lifetime of a system. The failure rate is initially very high due to uncovered faultsbeing detected and due to the young age of the process. The failure rate of the population drops precipitously as the productages. When the failure rate saturates, the infant mortality phase ends and useful life begins. Design goals are to bring the startof useful life earlier. Trying to control failures during infant mortality is not very useful.

Ingot: A silicon cylinder which can be sliced into wafers. The ingot is usually doped and is essentially a single crystal.

Input high voltage: The higher of the two input voltages at which the VTC of a gate has a slope of −1. This represents theedge of the stable logic “1” input range. Thus it is instrumental in defining the high noise margin. It is the higher limit of thetransition (high gain) region.

Input low voltage: The lower of the two input voltages at which the VTC of a gate has a slope of −1. This represents theedge of the stable logic “0” input range. Thus it is instrumental in defining the low noise margin. It is the lower limit of thetransition or high-gain region.

Instance (VHDL): A specific physical declaration of the existence of a specific component. The instance uniquely labelsthe specific use of the component as well as describing how its ports are connected in the port map.

Insulator: Alternatively known as dielectric. A material with a very large bandgap and for which there are no suitabledopants. Insulators have extremely low charge carrier concentration and very low conductivity. They also offer very largeenergy barriers to charge carriers flowing in from other types of materials.

Integrated circuit: A term sometimes applied to a die, and sometimes applied to the die when mounted and packaged.

Interwire capacitance: The capacitance that exists between two wires rather than a wire and the substrate. This can bebetween wires in the same layer or between wires in different layers although the former is more common. Interwirecapacitance does not result in delay, but leads to coupling and interference, which can be even more dangerous. Interchipcapacitance is worse for deeply scaled technologies due to wires being more closely packed, and their thnicknesses beingkept relatively high.

Intrinsic delay: The delay of a gate with zero external loading. It is d