a power-constrained mpu roadmap for i nternational t echnology r oadmap for s emiconductors

A Power-Constrained MPU Roadmap for International Technology Roadmap for Semiconductors

Kwangok Jeong and Andrew B. KahngUCSD VLSI CAD Laboratory

[email protected]

CSE and ECE DepartmentUniversity of California, San Diego

mailto:[email protected]

UCSD VLSI CAD Laboratory - ISOCC, Nov. 23, 2009 (2/11)

Needs for MPU Roadmap• What is the limit of future SoC designs?

• MPU uses highest frequency / power / integration level of a technology MPU is a reference of leading edge SoC designs

• For a good MPU roadmap,• How would you approach the task of roadmapping MPU?• On what technology parameters should the MPU roadmap depend?• What constraints cause fundamental shifts in the MPU roadmap?

• A consistent and holistic modeling approach for MPU roadmap to reflect recent technology changes and to tradeoff MPU design constraints

• Historical MPU design constraints• Moore’s Law: #TrN = 2 (#TrN-1)• Constant die area: 310mm2 ((2X #Tr) (0.5X Tr area) = 1)• Power: 130W ~ 150W• Performance: improved with multicore architecture


Technology Scaling Changes for ITRS 2009• New scaling trends for M1 half pitch and gate length

• Cell area follows M1 half pitch• Electrical parameter follows gate length

• Smaller area is expected, but what about power?

Physical Lgate

M1 ½ Pitch

1 year delayed

2 year delayed, but scaling becomes more aggressive0.7x / 3year 0.7x / 2year (~2013), 0.7x / 3year (2014~)

Decreases dimension Smaller areaDecreases Pdyn and Pleak

Increases densityIncreases Pdyn and Pleak

Electrical Parameters (Ioff, Cunit, etc.)Increases gate capacitanceDecreases Ioff

Increases Pdyn but decreases Pleak


Parameterized MPU Model

A-Factor(Alogic , ASRAM)

Transistor Density(Dlogic , DSRAM)

Power Density(Ddynamic , Dstatic)

MPU Power(P)

Capacitance Density(Dcap,logic , Dcap,SRAM , Dcap,int)

Unit-Cell Area(Ulogic , USRAM)

M1 Half-Pitch(F)

#Tr. per logic cell (Ntr,nand2)#Tr. per SRAM bitcell (Ntr,bitcell)#Logic gates per core (Ngates)#Bitcells per core (Nbits)#Cores per die (Ncore)

#Components

Unit-width leakage (Ioff)

Gate length (Lg)Gate width (Wg)Gate capacitance (Cg)

Technology (PIDS)

Switching ratio ()Low-Vth cell ratio ()

Low Power Tech.

Interconnect capacitance (Cint)Interconnect density (Dl,max)

Technology (Interconnect)

Logic layout overhead (Ologic)SRAM layout overhead (OSRAM)

Design Overhead

Voltage (V)Frequency (f)

Operating Condition

Unit logic cell width (Wlogic )Unit logic cell height (Hlogic)Unit SRAM bitcell width (WSRAM)Unit SRAM bitcell height (HSRAM)

Unit Cell Layout

Metal2 routing pitch (pM2)Poly-to-poly pitch (ppoly)

Design Rules

Metal1 (M1) Pitch

M1 half-pitch (F)

= M1 pitch / 2


Updated A-Factors: M1 HP (F) based Model• Logic:

• A-factor = 175

NAND2 Area= 3 PPoly 8 PM2 (3 1.5 PM1) (8 1.25 PM1)= 45 (PM1)2

= 180 F2 175 F2




MPU Power(P)



M1 Half-Pitch(F)

NWell

Contact

Active

M1

Poly

Contacted-poly pitch(PPoly 1.5PM1)

M2 pitch (PM2 1.25PM1)

Contacted-poly pitch (PPoly 1.5PM1)

M1 pitch (PM1)

• SRAM: • A-factor = 60

SRAM Bitcell Area= 2 PPoly 5 PM1 = 3 PM1 5 PM1= 15

(PM1)2

= 15 (2 F)2 = 60 F2


(U) Area of unit cells• Logic:• SRAM:

(S) Area of MPU• Logic:• SRAM:

(D) Density of MPU (#Tr. / Area)• Logic:• SRAM:

OverheadUnit area

#cores#gates per core

Transistor Density Model




MPU Power(P)



M1 Half-Pitch(F)2FAU logiclogic

2S FAU RAMSRAM

gatecorelogiclogiclogic NNUOS

bitscoreSRAMSRAMSRAM NNUOS

logiclogic,trlogic,tr S/ND

SRAMbitcell,trSRAM,tr S/ND

#bits per core


Power Density Model• Capacitance density

• Dynamic power density• Active capacitance

density• Dynamic power density

• Static power density




MPU Power(P)



M1 Half-Pitch(F)

*PIDS: Process Integration, Devices and Structure** INT: Interconnect

intmaxlggtrintcaptrcapcap CDWCDDDD ,,, 3/1

caplogiccap DD ,

11

312

, fVDD HPlogiccapdynamic

LSTPoffHPoffHPlogictrlogicstatic IIVDD ,,,, 15.0

LSTPoffSRAM

LSTPoffHPoffSRAM

SRAM

HPlogictrlogicstatic

IO

IIO

O

VDD

,,,

,,

111

5.0

Cg: gate cap. per unit width from PIDS*

Cint: unit length interconnect capacitance from INT**

Wg: average width of a transistor (=5F)Dl,max: maximum interconnect density (/cm2) from INT**, assuming every third track is occupied

: switching ratio, assumed as 15% in 2007: ratio of high performance (HP) transistors, assumed as 10%: ratio of SRAM dynamic power to logic dynamic power


Capacitance Density(Dcap,logic , Dcap,SRAM , Dcap,int) of logic part uses HP transistors

Bitcell array (1/OSRAM) uses LSTP transistors of peripheral part uses HP transistors(1- ) of peripheral part uses LSTP transistors


New MPU Integration Scaling and Chip Size• Fast M1 half-pitch

Increases density• Number of cores: 2x / 2year

(~2013), 2x / 3year (2014~)• Number of transistors per core:

2x / 2year (~2013), 2x / 3year (2014~)

• Reduced A-factors • Logic A-factor: ~320 175• SRAM A-factor: ~100 60

Reduced chip size• 310mm2 260mm2

• Logic area = #cores #Logic Tr. AF2

= ~100mm2

• SRAM area = #SRAM bits 9 6 AF2 = ~83mm2

• Integration overhead= 30% of total chip size= ~77mm2

Bill

ion

Tran

sist

ors

* Intel Core-i7: 263mm2

* AMD Opteron (Shanghai): 258mm2


Intrinsic Frequency Scaling• MPU frequency scaling follows

transistor intrinsic delay (CV/I) scaling: • 13% per year• Dynamic power increases due to

large active capacitance increases

• Dynamic power reduction techniques must be developed• Switching activity ratio scaling factor: N = k N-1

k = 1 k = 0.95


Power-Constrained Frequency Scaling• Intrinsic frequency scaling + activity scaling

Still exceed 150W in 2015• To meet market needs (130~150W for a platform),

frequency improvement has to be limited: • 13% per year 8% per year, total power < 150W

8% frequency scaling

Power < 150W


Conclusion• We have proposed a consistent, holistic modeling

approach for MPU area/power/frequency roadmapping. From the model,• For future high performance MPU, aggressive dynamic

power reduction techniques are strongly required• Frequency improvements need to be restricted: 8% per year

• Ongoing work• We track tradeoff every year and make sure we don’t miss

the frequency/#core/power curve tradeoff• We are considering doing a 2009 blind survey on frequency

from key vendors

BACKUP


Outline• International Technology Roadmap for Semiconductors

• Roadmap for Microprocessor

• Recent Technology Roadmap Changes

• Parameterized MPU Roadmap Models• Transistor Density Model

• Capacitance Model

• Power Model

• Power-Constrained Frequency Model

• Conclusion


History of ITRS

1991Micro Tech 2000

Workshop Report1992 1994 1997

National Technology Roadmap for Semiconductor(NTRS) - Semiconductor Industry Association (SIA)

Europe Japan Korea Taiwan USA

SIA

International Technology Roadmap for Semiconductors(First Version - 1998 Update)

1999

2000Update

2001

2002Update

2003

2004Update

2005

2006Update

2007

2008Update

2009Full Revision(Odd years)

Update(Even years)

2009


ITRS, System Driver, and MPU

System Drivers

Design

Test & Test Equipment

Process Integration, Devices & Structure

RF and AMS

Front End Processes

Lithography

Interconnect

Factory Integration

Assembly & Packaging

Environment, Safety & Health

Yield Enhancement

Metrology

Modeling & Simulation

EmergingResearch Devices

Emerging Research Materials

ITRSSystem Drivers

Process Integration, Devices & Structure

InterconnectMicroprocessor (MPU) requires- Leading edge process and device- Highest frequency / integration / power

We develop a power-constrained MPU roadmap to tradeoff power and performance


Capacitance Density Model• Capacitance density due to transistors

• Capacitance of a transistor

• Cg: gate cap. per unit width from PIDS*

• Wg: average width of a transistor (=5F)

• Capacitance density of transistors

• Capacitance density due to interconnect

• Dl,max: maximum interconnect density (/cm2) from INT**, assuming every third track is occupied

• Dl,eff : effective interconnect density,1/3 (Dl,max), considering routing congestion and power/ground network

• Cint: unit length interconnect capacitance from INT**




MPU Power(P)



M1 Half-Pitch(F)

*PIDS: Process Integration, Devices and Structure** INT: Interconnect

ggtr CWC

trtrtrcap CDD ,

intefflintcap CDD ,,


Power Model – Dynamic Power Density• Active capacitance density

• Not all capacitances are working : switching ratio, assumed as 15% in 2007

• Dynamic power density for logic area

: ratio of high performance (HP) transistors, assumed as 10%

• Non-timing critical parts can have smaller activity (1/3)

• Dynamic power density for SRAM area

• SRAM can have different (maybe slower) frequency, different operation modes, e.g., disabled, different VDD, etc. SRAM dynamic power estimation is hard!

: ratio of SRAM dynamic power to logic dynamic power




MPU Power(P)



M1 Half-Pitch(F) intcaptrcaplogiccap DDD ,,,

1

312

,, fVDD HPlogiccaplogicdynamic

logicdynamicSRAMdynamic DD ,,


Power Model – Static Power Density• Static power density for logic area

: ratio of high performance (HP) transistors, assumed as 10%

• (1- ): ratio of low standby power (LSTP) transistors• Ioff,HP and Ioff,LSTP are from PIDS

• Static power density for SRAM area

• Bitcell array (1/OSRAM) uses LSTP transistors of peripheral part uses HP transistors

• (1- ) of peripheral part uses LSTP transistors




MPU Power(P)



M1 Half-Pitch(F)

LSTPoffHPoffHPlogictrlogicstatic IIVDD ,,,, 15.0

LSTPoffSRAM

LSTPoffHPoffSRAM

SRAM

HPlogictrlogicstatic

IO

IIO

O

VDD

,,,

,,

111

5.0

a power-constrained mpu roadmap for i nternational t echnology r oadmap for s emiconductors

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