affordable asic design

7/28/2019 Affordable ASIC Design

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C DesignDr. John Tanner, Anant Adke, David H. ipinTanner Research, Inc.

444North AltadenaDrivePasadena, CA 91 107

AbstractTo be competitive, companies mustdesi@more applicationspecific integrated circuits (ASICs) into their products. Thenumber of ASICs designed increases each year, while thenumber of parts for each design decreases. The only waythis trend can continue is if the cost of design hardware,software, and prototypes drops. This tutorial addressesrecent advances in each of these three areas that allowaffordable ASIC design for the irst time.Commercial CAD tools are now available that supporthands-on electronic design on inexpensive FCs as well asmore expensive Macintoshes and Unix workstations.Designers can create vendor independent logic diagrams,simulate them, and implement them via automatictranslation to a variety of technologies including fieldprogrammable gate arrays (FPGAs), commercial gate arraysand standard cells, and custom masks suitable forinexpensive MOSIS prototypes. Mask preparation toolsinclude completely automatic mask generation for logicdesign, as well as fully customized design for VLSIapplications. New cross-section viewing facilities aid in theunderstanding of IC fabrication processes and in the designof special structures. FPGAs and MOSIS prototypes areinexpensive and bring the fu n back into designing with newIC technology.This tutorial will discuss the following topics:

Economics of ASIC use and fabricationAffordable design platformsAffordable design toolsTraditional gate array and standard cell technologiesField programmable gate arrays (Actel. Xilinx)Affordable prototypes through multi-project wafersAffordable volume production

With the drop in price of personal computers andworkstations and the emergence of new powerful yet low-cost CAD software, it is now possible LO provide hands-ondesign capability at lower costs than ever befoxe. Affordablelow-volume prototyping of FPGAs and MOSIS customchips allows designers to carry their designs throughimplementationand testing before volume production.C . .

There are many reasons for =designusing off-the-shelf TTL parts to aplflication specific

integrated circuits. For one thing, it is very easy LO copy adesign implemented. using off-the-shelf parts. As boarddensities go up, there is always a push towards reducingparts count. Putting the design into a single IC greatlyreduces the parts count compared to a off-the-shelfimplementation. Also, it is seldom possible to find an off-the-shelf part that exactly implements the required function.There are other advantages also. lower parts and inventorycosts, lower manufacturing costs, lower power consumptionand i ncreased reliability being some of them.The downside of going to ASICs is that the designturnaround time increases significantly. The NRE costsassociated with the design increase significantly (00. ASICsbecome cost-effective at volume production of at least10,OOO. For full-custom designs, the volumes have to be ashigh as 100,000 units. There are several reasons for thehigh NRE costs.The tools required to support ASIC design are the first majorcost item. Although workslation prices continue to drop,the software and hardware investment can easily run up LOhundreds of thousands of dollars. A significant effort ha s LObe expended to ensure design integrity prior to production,since recycling costs can kill a project. This requires a lotof simulation expenses. The other major cost of ASICproduction is the mask charges. With todays complicatedprocesses, it is common to have ten to twelve mask steps.With the per mask costs being $5000 an d up , the maskchargesalone can add up to tens of thousands of dollars.Does all this mean that ASIC design is restricted to bigcompanies which can afford an investment of millions ofdollars? Fortunately, it is not so. With the emergence ofpowerful new software running on inexpensive yet powerfulpersonal computers, ASlC designers can implement theirinnovative designs inexpensively. The fabrication costs arereduced too, hanks to the many new technologies that allowquick and inexpensive prototyping and volume production.

ble D & r n PI &form.The major capital costs associated with undertaking ASICdesign in house are the costs of new computers and CADsoftware. Although Unix workstations have recentlydropped in price dramatically, acquiring al l the piecesnecessary to implement ASIC design represents a significantinvestment to the tune of hundreds of thousands of dollars.It is also m e that with the introduction of more powerful32-bit microprocessors. the ubiquitous personal computersare approaching the native power of workstations. It h asbeem widely reported that more engineering groups havebought design tools that run on IBM PC compatiblecomputers than tools based on any other platform. On thesoftware side, the introduction of powerful new tools that


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Table 1

Many clone companies1 h4Byte RA M2 floppy disks60MByte hard diskVGA graphics card and monitorMouseDOS oftware

386 computer,20 MHZ $2200

Total

Costspe r CAE seat.softwareOrcADTannerResearchSchematic EditorLogic SimulationActel Mapping library

MOSIS Mapping libraryLayout EditorMOSIS Layout LibraryIS-SPICEintusoft

4951295249249995295

295$6.073

allow designers to implement low cost ASICs hascompleted the full spectrum of ASIC design. Indeed,personal computers provide the real bargains, not only inlowest purchase price but with low hardware and softwaremaintenance costs and widest availability of affordablecommercial software.An ASIC designer can be outfitted withd IBM compatible386-based PC for less than $4400 p a seat. Table 1idenlifes the software and hardwarer e q d or typical ASlCdesign . Softwarecosts will vary with the emphasis of thecourse.System support costs of Pcs are minimal. Unlike Unixworkstations that require a major time commitment from aUnix expert, DOS machines are simple enough that they canbe un with almost no software maintenance support.Hardware maintenance of PC-class machines is alsogenerally low. When the rare hardware failure does occur, itis easy for a novice to open the machines and swap cards andcomponents with similar working machines to isolateproblems. Budgets should include 10%to 15% of purchasecosts per year to cover hardware maintenance and repair.After the first year budgets may allow for systemenhancements such as RAM upgrades, local area networks,modems, and data backup systems.

TookThe major integrated circuit design tasks are schematiccapture, gate-level simulation. fault grading, cell masklayout, analog simulation, design rule checking, and chiplayout. We will show that each of these steps can beimplemented on a personal computer with affordable yetpowerful software. Figure 1is a block diagram of the toolsand thek interrelationships.

Schematicwand netlist generatioA typical design begins with the creation of a schematicusing elements from a vendor independent logic library.Library elements range from low level gates, flip-flops,latches, and multiplexers up to multiple-bit counters andadders. The schematic editor creates a netlist that specifies

the library elements used in a design and theirinterconnection. The netlist translator, in conjunction witha vendor mapping library, substitutes a vendor-specificimplementation for each generic element in the netlist andproduces a new netlist in a particular vendors netlist format.This capability allows the designer to change technologiesby simply rerunning the netlist translator using a differentmapping library. No changes to the schematic arenecessary.The netlist wanslator allows for unit delay or full timingsimulations. Before choosing an implementationtechnology, a designer may simulate with a constant delayfor each logic element in order to debug the basic logicfunctionality. After choosing a vendor technology, thenetlist translator is executed again. The translator accessestiming information in the selected vendor mapping library.Each of the vendors cells has been precharacterized fortiming delays in the form of a constant plus a capacitive-load dependent term. The capacitances of each cells inputsare also contained in the mapping libraries. The netlisttranslator analyzes the circuit, adds up the i o h l capacitancefor each node, substitutes the appropriate capacitances intoeach delay formula, computes Lhe delays, and passes them tothe simulator. Wiring capacitances can be included in thecalculation, either as a fanout dependent empirical prelayoutestimate, or from a capacitance back annotation fileprovided from the place-and-route software.Gate-level simulationThe majority of the design time is spent iterating betweenthe simulation and the schematic. Fortunately, the gate-level simulator has beem heavily optimized for speed. Thegate-level simulator allows for binary signals 0 and 1,unknown X, nd high-impedance Z ignals and producestext output or waveforms. I t includes a static timinganalysis command that allows the designer to determinemaximum or minimum delays between nodes. Thesimulatoralso includes a powerful fault simulator.Fault testing on the production line culls out chips thathave fabrication defects and marks them for discard. Thistesting is very different from the functional testing that adesigner must do to verify that his design is correct.


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S c h e m L i b T MVendorIndependentLibrary SchematicCapture

IntwaceMask Level

-ne of:ActelxilinxVendor HarrisMapping NationalLibrary NcROKITI

SCMOSCMOS3L A

GateSimTMGate-level

I I

One of:SCMOSLibTMLay0u CMOS3LibTMLibrary AnaCMOSLibmother libraries

/ .Standard Ce lpPlace and RouteL-EditTM

Layout Editorwith DRC

\ Extractor 1I

ES2H PMCE-e MOSISOrbitus2Mask VLSIFormat U T M C

IS-Spiceor PSPICEAnalog Simulation

Figure 1: lock diagram of PC-based ASIC design CAD tools.


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Functional testing may involve large numbers of testpatterns to exercise the chips in many Vferent situationsthat the chip is expected to deal with. q h e goal of faulttesting is to minimize the number of tedpattemsand thusminimize the time each chip spendson an expensive testeryet still catch all fabrication faults by propagating theireffects to the outputs. The fault simulator takes in a netlistand a production test pattern and returns the percentage ofpossible fabrication defects (modeledas stuck-at faults) thatthe es t pattern would uncover. In today's climate of qualitycompetition, test coverage of 98% or more is consideredhighly desirable.When the designer is satisfied with the simulated behavior ofthe circuit, the netlist is forwarded for implementation. Inthe case of FPGAs, the netlist is processed by the vendor'ssoftware to internally configure a specific FPGA part. For avolume production part, the netlist is passed to thesemiconductor vendor where their place-and-route softwarewill create the production mask data for the gate array orstandard cell chip. For MOSIS prototypes. the netlist ispassed o the layout software on the designer's own machineto create the MOSIS-compatible standard cell layout. Ineach of these cases, the timing information corresponding tothe detailed placement and routing can bepassed back to thedesigner for post-layout simulation. Before committing tofinal implementation costs, the designer can verify that thepost-layout timing is within specifications.

. .ut 1 .ibranesMOSIS-compatible layout libraries are available for digitaland analog standard cells. These libraries contain fixedheight cells suitable for automatic composition by the place-and-route software. The libraries also contain sets of padsfor the MOSIS technologies ranging from 3pm to 1 . 2 ~ .The analog library contains cells described in Analog VLSIand Neural Systems by Carver Mead. Large scale analogcircuits are generally not suitable for automatic layoutcreation, so the analog library also contains several largefull-custom analog circuits that can serve as examples andcan be scavenged for useful cell layouts.

provides a very affordable implementation of Spice. PSpiceis another very popular commercial analog simulator.Several other commercial versions of Spice are available.The extractor can also produce a switch-level netlist file inNTK format. NTK files can be simulated at the switch-levelusing programs such as COSMOS from CMU. The NTKfiles can also be used for a layout vs. schematic (LVS)comparison to insure that the mask implements thedesignem intentasdefined by the schematic.-tion ViewsStandard cell designs only scratch the surface of the designpossibilities available with silicon. High-performancedigital designs can benefit from custom RAM, ROM, PLA,and ALU blocks. Analog design almost always requireshand crafted structures. Traditional analog circuits includeamplifiers, comparators, analog-to-digital conveners. digital-to-analog converters. and switched capacitor filters. Possiblenovel structures include imagers (both MOS and CCD),combination bipolar-MOS transistors, Hall-effect sensors,temperature sensors, neural networks, and floating gatestructures.An integrated circuit is inherently a three-dimensionaldevice. Experienced designers can quickly mentally translatethe flat screen representation into its corresponding threedimensional structure. In discussions between engineers,hand drawn cross section views are often used tocommunicate the relevant content of a design that may notbe readily apparent from the usual flat top view.Quick access to cross section views provides an effectiveway of aiding understanding of integrated structures. Wehave implementedan automatic cross section view generatorwithin L-Edit, the Tanner Tools layout editor. L-Editallows the designer to interactively create and edit geometricmask data on a computer screen by using a mouse. Withthe new cross section feature. the designer draws a sectioningline on the layout with a mouse. L-Edit immediately opensa new window adjacent to the layout and constructs in thewindow a cross section view corresponding to the sectioningline in the layout area. This viewing facility allows thedesigner to check his layout against his mental model of it.Cross section views of integrated circuits aid novice andavout. verification. and analQe s mulation

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implant, and CCD implant. Clever engineers can createmulti-gate uansistors, JETS. isolated bipolar transistors,CCD transfer srructures. and a variety of floating gatestructures. Cross section views are important even to theveteran chip designer when creating and communicatingthese more complex structures.Cross section views are often useful for understanding thereasons for geometrical design rules. For example, mostCMOS processes have a minimum distance between via andthe edge of polysilicon. Vias may be entirely surrounded bypoly or completely away from poly, but may not be near anedge. Although this rule may Seem arbitrary to first-timedesigners, a cross section view shows clearly the unevenmetal terrain over poly edges. It becomes easy to visualizethe fabrication problem that would arise from trying to placea via over the uneven metal. Advanced designers benefitfrom understanding the motivation for d a g n rulesby beingable to selectively violate design rules ufi8er conditions thatwont cause fabrication problems.Our implementation of cross section views is intended to aidthe circuit designer in conceptually Understandingthe!.verticalstructure of integrated circuits. For this purpose, therenderings do not have to be a completely accuraterepresentation of the physical structure of integrated circuits.Actual chips have a variety of properties, such as smoothheight transitions. that are not modeled here. The simplecross section feature described is nor intended to be accurateenough to aid the process engineer but simply to showclearly the vertical relationship of the various fabricationlayers as a function of the masks specified in the layout.The cross section views are built up from the layout bysimulating a set of fabrication steps and building thediagram from the substrate up, one layer at a time. Oursimplified process steps amount to the recipe used to createthe integrated circuit view and correspond only roughly tothe process steps used by the fabricator to create the chip.The process specification is maintained on-line within L-Edit and may be edited interactively by the user.Figure2 shows a screen captured from the PC version of thelayout editor. In operation, the designer interactively drawsand edits the mask geometry using a mouse. In this case,the upper half of the screen displays a finished invertercircuit. The designer then invokes the cross sectioncommand by pulling down the special menu. Next thedesigner chooses the cross section to be displayed bydrawing a sectioning line across the layout. This line can beseen below with arrowheads at each end pointing toward thecross section view. L-Edit then opens a special crosssection window and constructs the corresponding side viewof the integrated circuit.L-Edit cross section views can also be constructed one stepat a time, under control of the user. For illustrating thefabrication steps, the display can be temporarily halted aftereach step in the process specification table. This single-stepdisplay mode is useful for learning the steps involved infabrication. It is also possible to use a much more detailedprocess specification table. Single stepping through afabrication cross section that includes all the photoresist andother intermediate processing steps would better

communicate the full complexity of todays fabricationprocesses. For circuit designers who only want to viewfinal cross sections, the simpler process specification issufficient and easier to maintain.D d P n Methodu log i e s

There are several technologies available to the ASICdesigner to implement his designs.standard cells are a collection of fixed height cells whichimplement commonly used SSI and MSI logic functions.Designing with standard cells is very much like designingwith off-the-shelf TTZ logic parts. The restriction of fixedpitch exists so that during the automatic placement andlayout phase, all the cells can be abutted to each other. Thisreduces the complexity of the algorithms required forplacement and muting. The cells themselves are hand-craftedby layout engineers. Note that during fabrication, the chipis built from ground up, i.e.. all the mask steps have to befollowed. This reduces the cost-effectiveness of standardcells. It is true that their space utilization and speed is

higher than gate arrays.Gate arrays reduce the number of processing steps duringfabrication. They consist of a prefabricated collection ofuncommitted gates, which can be mask programmed usingone or more levels of metallization. The gate array vendoris able to stock the gate arrays, and customize them forindividual customers using a very few processing steps. ascompared to the ten or twelve mask steps required tofabricate a chip ground up. This reduces the cost for thecustomer. It may not bepossible to achieve as high speedsand space utilization as standard cells, though.

The two leading vendors of FPGAs today are Actel andXilinx. Actel devices are configured by a special hardwaredevice that permanently burns the connections internal toan Actel chip. Once burned, the Actel chip maintains itsconfiguration and no longer requires any special supportcircuiuy.The configuration of Xilinx chips is stored in volatile flip-flops within the chip. Each time a Xilinx chip is poweredon, its configuration needs to be loaded into the deviceagain. During prototyping, the configuration data can bedownloaded from a PC. For stand alone operation, a Xilinxchip can load its configuration data on power up from aROM. Xilinx prototypes have the advantage of beingreusable but have a slight system complexity of allowingfor power-up configuration. Prototyping with Actel partsrequires access to a special burner box that costs $5,000along with the specialized Actel software to operate it. Notethat the Actel software requires atleast 80386-basedmachines. The investment in the Actel hardware andsoftware can be avoided by using an Actel programmingservice such as the one provided by Tanner Research. The

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Xilinx software and cable costs about $4OOO.Both Actel and Xilinx FPGAs employ programmable logicbuildmg blocks and interconnect to implement a specificcircuit. The vendor independent methodology shields th edesigner from these awkward and individual internalarchitectures and allows the designer to concentrate on thedesign problem using more fam iliar gate s and flip-flops.The netlist translator in conjunction with the vendors

software maps each design onto the programm able structureinside the FPGAs. As the size of a design approaches thelimits of the capacity of an FPGA, the vendors softwaremay be unable to create a valid configuration . At this point,a designer may make his design smaller, select a largerFPGA .part , or attempt to perform hand optimization.Anecdotal evidence suggests that the Actel software canachieve much higher utilization of an array before giving up,

LEdit F i l e Ed i t V i w Cell Arrange Se tup Spmcial

P-

Figure 2: L-Edit screen display showing automatically generated cross section view .

Table 2: Comparison ofActel and Xilinx FPGAs and MOSIS prototypes.

Actel Actel using Xilinx MOSISburning servicestart-up Cost $5,000 $0 $4000 so

Gate capacity 2000 2000 2000 1000Cost per chip $100 $200 $100 $500Implementation time 1 hour 2 days 1 hour 7 weeksSpecial structures No No No Yes* Note that Xilinx has a wide variety of parts w ith different gale capacities and prices. Their slated gate capacities arctheoretical Values that gene rally need to be divided by 2 or 3 to get actual gate capacities.

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but Actel provides no access to the internal elements of theirFPGAs for hand optimization. The Xilinx software cannotachieve automatic and complete configuration for nearly ashigh a utilization as Actel's, but the Xilinx software comeswith an editor for hand tweaking the design within theXilinx architecture.In order to reduce start-up costs for using FFGAs. TannerResearch offers an Actel programming service. Customerscan design and simulate their circuits on their owncomputer. When they are ready for an implementation. theytransfer the netlist electronically to our computer, weprogram the part using our Actel software and hardware, andship the resulting part overnight. The price for this serviceis $200 and $250 for the 1200 and 2000 gate partrespectively, including the cost of the part and shippingcosts.

Affordable Productionve P r o t o w

MOSIS s a prototyping service. It offers small quantitiesof full-custom and semi-custom chips for as little as $500using industry standard volume production processes.Designs are combined on a single wafer run. Therefore,instead of paying for an entire wafer lot costing between$50.000 and $80,000, MOSIS users only pay for thepercentage of silicon that they use, which can be as low as$500. For digital design, approximately lo00 gates will fi tinto a MOSIS TinyChip" using the Tanner Tools andlibraries.The benefits gained by working with a volume productionprocess may not beworth the additional cost and seven weekfabrication delay for projects that are smctly digital and canfit into an FFGA. For analog designs or special structures,access to a full-custom process is necessary. For prototypequantities MOSIS provides a tremendous cost advantage overa custom fabrication run purchased directly from asemiconductor vendor. Table 2 compares Actel and XilinxFPGAs with MOSIS prototypes.

le VFor production volumes, neither MOSIS gar& nor FPGAsprovide cost effective solutions. As volfies increase, thepiece price becomes more important jhan NRE costs.Engineers must be aware of ASIC prices in order to make aninformed decision on the cost effectiveness of including anASIC in a system design. Almost always, the price forvolume purchase of ASICs is a negotiated settlementbetween the customer and the ASIC vendor. OrbitSemiconductor, Inc., working with Tanner Research, hasprovided budgetary ASIC costs for the purpose ofengineering decisions prior to a negotiated semiconductorpurchase. Orbit is a MOSIS vendor, so you have the optionof obtaining inexpensive prototypes from their fabricationline.Another vendor who covers the full spectrum of prototypes,low volume Droduction run or hieh volumes is US2. US 2

uses a novel technology wherein an E-beam is used to writeall layers onto the wafer. They promise fully tested partswithin four weeks.

SummarvAffordable commercial CAD tools are now available for arange of electronic design classes. These tools supportFPGA and MOSIS prototypes. In less than two years, theTanner Research software has been adopted by more than 90colleges and universities. The majority of these sites usePCs. A smaller number use Macintoshes. We expect thenew Unix version of the tools to gain acceptance at schoolsthat can afford these more expensive machines.

ContactsLayout, Gate level Simulation,Libraries, Logic Mapping softwareTanner Research, Inc.Schematic capture softwareM A DTango (Accel)ViewlogicAnalog simulation softwareintusoftMicroSimFPGA hardwareActelXilinx

MOSISOrbitus2

Custom IC prototypesCustom IC volume production

(818) 795-1696(503) 690-988 1(619) 554-1000(508) 480-088 1(213) 833-0710(7 14) 770-3022(408) 739-1010(408) 559-7778(213) 822-1511(408) 744-1800(800) 969-7448

affordable asic design

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