lecture_2 #1 2 asic design methodology 1) definition 2) design representation(top-down, b-s-p) 3)...
TRANSCRIPT
Lecture_2 #1
2 ASIC Design Methodology
1) Definition
2) Design Representation(Top-down, B-S-P)
3) Design Objectives
4) ASIC Types
5) ASIC Design Process
6) Cost Analysis
Contents
Lecture_2 #2
1) Definition of ASIC
ASIC is application-specific.
(vs. General-Purpose, Commodity or Standard IC i.e., memory, microproces
sor)
ASIC can become ASSP(Application-Specific Standard Product) if vo
lume becomes large.(ex:MODEM, disk controller)
ASIC integrates many block in one chip.
(Today’s board is tomorrow’s ASIC.)
Lecture_2 #3
2) Design Representation using Gajski’s Y-chart
Lecture_2 #4
3) Design Objectiveslow
high
longhigh
performance
Per-chipcost(chip area)
NRE Cost
PTAT(ProductTurn-around Time)
FPGA
Gate array
Full-custom
BICC
Lecture_2 #5
4) ASIC Types
PLD PAL(device name), PLA(circuit style) ;
all AND-OR plane logic(two-level logic)
FPGA
Gate Array(with or without embedded block, ex;memor
y)
Standard Cell(w. or w/o macro)
Compiled block ; datapath, RAM, ROM, multiplier
Full - Custom
Semi-custom IC
(ASIC in narrow sense)
Lecture_2 #6
Important elements in ASIC Design Important elements in ASIC Design
ASICdesign
ASICdesign
System specificationSystem specification
in-houseCAD tools
in-houseCAD tools
CommercialCAD tools
CommercialCAD tools
ASIC foundryASIC foundry
IPIP
librarylibrary
Lecture_2 #7
Programmable logic device(PLD) die. Programmable logic device(PLD) die.
The macrocells typically
consist of programmable
array logic followed by a
flip-flop or latch. The m
acrocells are connected u
sing a large programmabl
e interconnect block.
Lecture_2 #8
Field-programmable gate array(FPGA) die. Field-programmable gate array(FPGA) die.
All FPGAs contain a reg
ular structure programma
ble interconnect.
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Two-step manufacturing Two-step manufacturing
Full-customfabrication
Semi-customfabrication
Standard phase custom phase
Lecture_2 #10
Standard & Custom Masks Standard & Custom Masks
Two-step manufacture :
First(deep)processing steps Base wafers
Customization :contacts & metal layers ASIC
Custommasks
Custommasks
Standardmasks
Standardmasks
Lecture_2 #11
Master array = core + I/O pads Core : - macro-architecture
number & distribution of basic core cells embedded(specialized) structures
- micro-architecture isolation method : gate or oxide isolation predefined channels or channelless layout available devices : transistors, capacitors, resistors, … NMOS/PMOS transistor count ratio number of contacts to each transistor gate, source or drain spacing between transistors, or transistor pitch identical or variable size transistors relative size of the NMOS and PMOS transistors layout of the basic core cell
I/O pads - number, functional capabilities, size, ...
Architecture Specifications Architecture Specifications
Lecture_2 #12
PLDs, PALs, EPLDs :< 2K gates
field programmable AND/OR arrays with latches
use (E)EPROM or (anti)fuse devices
field programmable gate arrays(FPGA) :< 5K gates(1972), 100K gates(1998)
electrically programmable SRAM, antifuse or EPROM devices
logic mapped into predefined blocks
programmable interconnections
gate arrays, sea-of-gates(SOG) :200K gates
personalized with metals & contacts
standard cell
compiled cells datapath, ROM, RAM
macro-based & full-custom :all mask layers personalized
dense & high performance
Comparison of Various ASIC Methodologies Comparison of Various ASIC Methodologies
Rapidly changing designslow volumelow complexity
High volumecomplexstable designs
Lecture_2 #13
Fill the gap between PALs and classical(mask programmable) gate arrays architecture :
array of configurable logic blocks(gates, multiplexers, flip-flops) predefined routing channels filled with interconnection wires wires are programmable
programming technology : EPROM, anti-fuse, or SRAM. SRAM : volatile but reconfigurable configuration Xilinx EPROM : non-volatile and reprogrammable, Altera anti-fuse circuits : permanent programming Actel
size : up to 10K gate, (now 200K gates) speed is comparable to PALS.
Field Programmable Gate Arrays Field Programmable Gate Arrays
K
Lecture_2 #14
First gate arrays : one programmable metal layer
fixed contact locations
extensive use of polysilicon for routing
2- or 3- transistor cell -> 2- or 3-input NAND (NOR) gates
later improvements : use several basic cells to implement more
complex macros
programmable contacts
second programmable metal layer + vias
First Generations of Gate Arrays First Generations of Gate Arrays
Predefinedchannel
P
N
P
N
Lecture_2 #15
CHANNELLESS LAYOUT suppression of predefeined channels array entirely filled up with transistors connections are routed over unused transistors
GATE ISOLATION vs. OXIDE ISOLATION suppression of the gaps in the diffusion continuous strips of diffusion with equally spaced
transistors basic cell = 1N & 1P electrical isolation made by connecting a gate to
VSS(NMOS) or VDD(PMOS)
OTHER VARIANTS & IMPROVEMENTS : embedded arrays RAM-compatible basic cell additional metal layers
Second Generation : Sea-of-Gates Second Generation : Sea-of-Gates
Gate isolation
Oxide isolation
VDD
P
N
VSS
VDD
P
N
VSS
Lecture_2 #16
ADVANTAGES OF GATE ISOLATION :
flexibility in macro width(one transistor
increment)
density : transistor gate length smaller than
diffusion-diffusion distance
full merging of source & drain
PROBLEMS WITH GATE ISOLATION :
N-and P-gate need to be physically separated
on very large & noisy circuits, glitches on
power supply lines may weaken the isolation
for short times
Gate Isolation vs Oxide Isolation Gate Isolation vs Oxide Isolation
Lecture_2 #17
Channelled versus Channelless Array Channelled versus Channelless Array
Routing problem is simplerOK with only one metal
Flexibility in channel definition(position & width)over-the-cell routinghigher packing densityRAM-compatiblesupports variable-height cells & macrocellsnow universally used
Lecture_2 #18
Simpler
reusability of classical P&R tools
tunable channel width(in fixed increments)
lower density(in terms of gates)
gates are smaller
smaller transistor size
Routing Channels Routing Channels
fixed channel width
increased master cell area
large transistor size
both methods can be used together
needs a special macro design
Alternate channels :
Covering channels :
Lecture_2 #19
Signal routing : internal macro connections : metal 1
external horizontal wires(channels) : metal 1
external vertical wires : metal 2
metal 3&4, if any, follow direction of metal 1&2, respectively
Metal Usage Metal Usage
Lecture_2 #20
power distribution : primary distribution : horizontal metal 1 lines
secondary distribution : vertical metal 2 lines
Metal Usage Metal Usage
Lecture_2 #21
Embedded Structures Embedded Structures
A part of the core is dedicated to a special function
most often : static RAM but also ROM, A/D or D/A converters, PLL, …
also : embedded test structuresadvantages : optimized function, performance,
high densitydrawback s : less versatile array, need to
maintain a larger master family(price !)
Core is generic and supports various customizations
reduced master family -> lower pricehigher flexibility, e.g. RAM size and location
need adapted CAD tools
Lecture_2 #22
BiCMOS Master Architecture(1) BiCMOS Master Architecture(1)
Higher gate count(CMOS is denser)TTL or ECL I/Osexamples :
Hitachi 84NTT 89(reduced voltage on-chip)
now abandoned
BiCMOS periphery blocks used for clock buffers, level conversion, …CMOS core : 60% - 95% areaexample :
LSI Direct Drive Array(88)
Lecture_2 #23
BiCMOS Master Architecture(2) BiCMOS Master Architecture(2)
Variant of the previousmixed digital/analog applicationsbipolar part can contain passive elementscan be seen as an embedded arrayexample : LSI Logic
Higher flexibility in the use of both devicesfull digital or mixed applicationsthe most used architectureexamples :
Motorola, AMCC, Hitachi, TI, ToshibaNEC, Fujitsu
Lecture_2 #24
Standard Cell Layout(W=25m in =0.25m Standard Cell Layout(W=25m in =0.25m
Lecture_2 #25
CBIC routing in 2-metal layers CBIC routing in 2-metal layers
Lecture_2 #26
Datapath composed of datapath cells Datapath composed of datapath cells
Bit 31
Bit 0Bit 1
Bit 30
adder
control and power signals (metal 2)
mux
Bit 2
Data buses(metal 3)
inv VDD(metal 1)
VDD (metal 2)
control signal (metal 2)
Data Buses (metal 3)
VSS (metal 1)
VSS (metal 2)
P diff.
N diff.1 bit-slice
2-1 mux inverter
Tr. gate
poly
metal 1
metal 2
metal 3
Datapath cell = Bit Slice Functional Element
Lecture_2 #27
5) ASIC design process
Lecture_2 #28
6) Cost Analysis
Spreadsheet for fixed cost of FPGA MGA and CBIC Spreadsheet for fixed cost of FPGA MGA and CBIC
Lecture_2 #29
Spreadsheet for Variable cost of FPGA MGA and CBIC Spreadsheet for Variable cost of FPGA MGA and CBIC
Lecture_2 #30
Product Profit Model Product Profit Model