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Lecture 19 CMOS Sequential Circuits - 2

Prof. José Luís Güntzel guntzel@inf.ufsc.br

Integrated Circuits & Systems INE 5442

Federal University of Santa Catarina Center for Technology

Computer Science & Electronics Engineering

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.2

 VTC with hysteresis  Different thresholds for positive

and negative  Hysteresis voltage = VM+ − VM−

 Restores signal slopes  Fast transition time at the output

Non-Bistable Sequential Circuits – Schmitt Trigger

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.3

Noise Suppression Using Schmitt Trigger

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.4

r ≈ kp/kn

CMOS Schmitt Trigger

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.5

M2, M4: ON

r ≈ kp/kn

Initial condition

0 0

CMOS Schmitt Trigger (LH)

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.6

M2, M4: ON

r ≈ kp/kn

0 →VM+ 0

CMOS Schmitt Trigger (LH)

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.7

M1, M3: ON

r ≈ kp/kn

VM+ 0 → VDD

Pull-down speeds up Vout transistion to VDD

CMOS Schmitt Trigger (LH)

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.8

M1, M3: ON

r ≈ kp/kn

Initial condition

VDD VDD

CMOS Schmitt Trigger (HL)

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.9

M1, M3: ON

r ≈ kp/kn

VDD →VM- VDD

CMOS Schmitt Trigger (HL)

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.10

M2, M4: ON

r ≈ kp/kn

VM- VDD → 0

Pull-up speeds up Vout transistion to 0

CMOS Schmitt Trigger (HL)

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.11

Moves switching threshold of the first inverter

r ≈ kp/kn

Application: Noise suppressor

CMOS Schmitt Trigger

Source: Rabaey; Chandrakasan; Nikolic, 2003

k = μ . Cox . W/L

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.12

(W/L)M1 = 1µm/0.25 µm (W/L)M2 = 3µm/0.25 µm

(W/L)M3 = 0.5µm/0.25 µm (W/L)M4 = 1.5µm/0.25 µm

Schmitt Trigger Simulated VTC

Voltage-transfer characteristics with hysteresis.

2.5

V M 2

V M 1

2.0

1.5

1.0

0.5

0.0 0.0 0.5 1.0 1.5 2.0 2.5

Vin(v)

Vx(v

)

VM-

VM+

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.13

(W/L)M1 = 1µm/0.25 µm (W/L)M2 = 3µm/0.25 µm

(W/L)M3 = 0.5µm/0.25 µm (W/L)M4 = 1.5µm/0.25 µm (W/L)M4 = k*0.5µm/0.25 µm

Schmitt Trigger Simulated VTC

Voltage-transfer characteristics with hysteresis.

2.5

V M 2

V M 1

2.0

1.5

1.0

0.5

0.0 0.0 0.5 1.0 1.5 2.0 2.5

Vin(v)

Vx(v

)

VM-

VM+

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.14

Voltage-transfer characteristics with hysteresis.

The effect of varying the ratio of the PMOS device M4

(W/L)M1 = 1µm/0.25 µm (W/L)M2 = 3µm/0.25 µm

(W/L)M3 = 0.5µm/0.25 µm (W/L)M4 = 1.5µm/0.25 µm (W/L)M4 = k*0.5µm/0.25 µm

Schmitt Trigger Simulated VTC

2.5

V M 2

V M 1

2.0

1.5

1.0

0.5

0.0 0.0 0.5 1.0 1.5 2.0 2.5

Vin(v)

Vx(v

)

2.5

k = 2 k = 3

k = 4

k = 1

2.0

1.5

1.0

0.5

0.0 0.0 0.5 1.0 1.5 2.0 2.5

Vin(v)

Vx(v

)

VM-

VM+

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.15

Multivibrator Circuits

flip-flop (latch, register)"

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.16

Application: ATD (Address Transition Detector) in SRAMs

Transition-Triggered Monostable

Source: Rabaey; Chandrakasan; Nikolic, 2003

in Delay td

out td

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.17

simulated response of 5-stage oscillator with minimum-size transistors

Fixed frequency

How to vary frequency?

Astable Multivibrators (Oscillators)

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.18

Applications: PLL, DVS

Voltage Controller Oscillator (VCO)

Source: Rabaey; Chandrakasan; Nikolic, 2003

CMOS Sequential Circuits

Lecture 19 – 2012/2 Prof. José Luís Güntzel

INE/CTC/UFSC Integrated Circuits and Systems Slide 19.19

References

1.  RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3.