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1 TFE4180 Semiconductor Manufacturing Technology Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra TFE4180 Semiconductor Manufacturing Technology Norwegian University of Science and Technology ( NTNU )

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Page 1: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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TFE4180 Semiconductor Manufacturing Technology

Etching ( Part 3 )Chapter 16: Semiconductor Manufacturing Technology by M. Quirk & J. Serda

Saroj Kumar PatraTFE4180 Semiconductor Manufacturing Technology

Norwegian University of Science and Technology ( NTNU )

Page 2: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Objectives

• Give an application example for dielectric, siliconand metal dry etch

• Discuss wet etch and its applications• Explain how photoresist is removed• Discuss etch inspection

Page 3: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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TFE4180 Semiconductor Manufacturing Technology

Table of Contents• Dry Etch Applications

– Dielectric Dry Etch– Silicon Dry Etch– Metal Dry Etch

• Wet Etch– Types of Wet Etch

• Polysilicon Etch Technology Evolution• Photoresist Removal

– Plasma Ashing• Etch Inspection

Page 4: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Requirements for Successful Dry Etch1. High selectivity to avoid etching materials that are not to be

etched (primarily photoresist and underlying materials)2. Fast etch rate to achieve an acceptable throughput of wafers3. Good sidewall profile control4. Good etch uniformity across the wafer5. Low device damage6. Wide process latitude for manufacturing

Page 5: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Dry Etch Critical Parameters

Equipment Parameters:• Equipment design• Source power• Source frequency• Pressure• Temperature• Gas-flow rate• Vacuum conditions• Process recipe

Other Contributing Factors:• Cleanroom protocol• Operating procedures• Maintenance procedures• Preventive maintenance schedule

Process Parameters:• Plasma-surface interaction:

- Surface material- Material stack of different layers- Surface temperature- Surface charge- Surface topography

• Chemical and physical requirements• Time

• Quality Measures:• Etch rate• Selectivity• Uniformity• Feature profile• Critical dimensions• Residue

Plasma-etchinga wafer

Page 6: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Dielectric Dry Etch of Oxide

• The most complicated etch process• Etch to form contact holes and vias

– Selectivity and high-aspect ratio important• Plasma etching process based on fluorocarbon

chemistry– CF4, CHF3, C3F8, C4F8, NF3, SiF3– May add Ar and/or He (buffer gas)

Page 7: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Oxide Etch Reactor

CF4

C3F8

C4F8

CHF3

NF3

SiF4

Ar

Wafer

Electrostatic chuck

Plasma

Selection of fluorocarbon and hydrocarbon chemicals

HF CF2

F

CHF

CF4

Page 8: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Dielectric Dry Etch of Oxide

• Underlying material selectivity– Add O2 <20% => better selectivity between Si and

oxide– Add H2 <40% => reduces etch rate for Si~0– Hard ”etch stop”– Polymer formation

Page 9: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Etch Stop Hard Mask Layer

n-well p-well

LI Oxide

p+ Silicon Substrate

p- Epitaxial Layer

2 Doped oxide CVD

Nitride etch

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Oxide CMP 3 4 Oxide etch1 Nitride CVD

Example: Silicon nitride, Si3N4, serves as etch-stop during LI oxide etchNote: The numbers show the order of the five operations

Page 10: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Dielectric Dry Etch of Oxide

• Photoresist selectivity• Contact etching to varying

depths• Sidewall profileContact holes

S DG

Page 11: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Dielectric Dry Etch of Silicon Nitride

• Gas-chemistry‒ CF4 mixed with N2 and O2

• LPCVD‒ High density

• PECVD‒ Low density higher etch rate

Page 12: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Silicon Dry Etch

• Mainly used for- Polysilicon gate formation- Single-crystal silicon trench creation

• Gases containing chlorine/bromine are preferred for etching- High selectivity to oxide- Etches anisotropically

Page 13: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Silicon Dry Etch

• Polysilicon Gate Etch Process Steps1) Breakthrough step2) Main-etch step3) Overetch step (avoid microtrenching)

Polysilicon gate formation

• Requirements- High selectivity to the gate oxide- High degree of anisotropy

Page 14: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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• Forms trenches for device isolation or vertical capacitors• Requires precise dimensional control• Carbon is added to protect the walls while etching• Fluorine, adequate selectivity to the photoresist• Chlorine/Bromine, high selectivity to the oxide mask (deep

trenches)

Silicon Dry EtchSingle-Crystal Silicon Etch

Page 15: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Metal Dry Etch

Major Requirements for Metal Etching1) High etch rates (>1000 nm/min)2) High selectivity to the masking layer (>4:1), interlayer dielectric (>20:1)

and to underlying layers3) High uniformity with excellent CD control and no microloading (<8% at

any location on the wafer)4) No device damage from plasma-induced electrical charging5) Low residue contamination (e.g., copper residue, developer attack and

surface defects)6) Fast resist strip, often in a dedicated cluster tool chamber, with no

residual contamination7) No corrosion

– Avoid moisture and atmospheric contamination

Page 16: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Typical Steps for Etching Metal Stacks1) Breakthrough step to remove native oxide2) ARC layer etch (may be combined with above step)3) Main etch step of aluminum4) Over etch step to remove residue. It may be a continuation of the main

etch step5) Barrier layer etch6) Residue removal process to prevent corrosion7) Resist removal

TiN Al + Cu (1%)Ti

p+ Silicon substrate

p- Epitaxial layer

n-well p-well

LI Oxide

ILD-1

Metal etchPhotoresist mask

Page 17: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Tungsten Etchback

Metal-2 stack

(d) Metal-2 deposition

Tungstenplug

(a) Via etch through ILD-2 (SiO2)

Metal-1 stackILD-2

ILD-1

Via SiO2

(c) Tungsten etchback

SiO2Tungstenplug

(b) Tungsten CVD via fill

Tungsten

Page 18: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Wet Etch

• Advantages:– High selectivity– No plasma induced electrical charging– Simple equipment

• Disadvantages:– Isotropic– Safety risk– High disposal costs– Photoresist lift-off– Bubble formation

Page 19: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Wet Etch ParametersParameter Explanation Difficulty to Control

ConcentrationSolution concentration(e.g., ratio of NH4F:HFfor etch an oxide).

Most difficult parameter tocontrol because the bath

concentration is continuallychanging.

TimeTime of waferimmersion in the wetchemical bath.

Relatively easy to control.

Temperature Temperature of wetchemical bath. Relatively easy to control.

Agitation Agitation of the solutionbath.

Moderate difficulty toproperly control.

Page 20: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Wet Oxide Etch• Buffered oxide etch:

– Selective removal of oxide by buffered solution of HF• Etch rate depends on formation and doping• Etches equally lateral and vertically on amorphous SiO2

Table 16.81 Approximate Oxide Etch Rates in BHF Solution at 25Ca

Type of Oxide Density (g/cm3) Etch Rate (nm/s)Dry grown 2.24 – 2.27 1Wet grown 2.18 – 2.21 1.5

CVD deposited < 2.00 1.5b – 5c

Sputtered < 2.00 10 – 20a) 10 parts of 454 g NH4F in 680 ml H2O and one part 48% HFb) Annealed at approximately 1000C for 10 minutesc) Not annealed

1 B. El-Kareh, ibid, p. 277.

Page 21: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Wet Chemical Strips

• Used to remove surface layers– Si3N4 etched with H3PO4 at 160°C

• Difficult to control bath• Oxynitride film is removed with HF

– Excess Ti after silicide formation

Page 22: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Polysilicon Etch Technology Evolution

Page 23: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Photoresist removal

• Wet removal– Photoresist stripping – Not cost effective

• Plasma Ashing– Dominant technique– Dry removal of resist with oxygen– Reacts oxygen atoms with the resist material in a plasma

environment

Page 24: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Atomic Oxygen Reaction with Resist in Asher

SubstrateResist

Asher reaction chamber

2) O2 dissociates into atomic oxygen 3) Plasma

energy turns oxygen into + ions

4) Neutral O and O+ react with C and H atoms in resist

Neutral oxygen radicals 5) By-product

desorption

6) By-product removal

Exhaust

Gas delivery

Downstream Plasma

1) O2 molecules enter chamber

+

++

++

++

+

Page 25: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Residue Removal

• Removal of post-etch residue– Sidewall polymers– Via veils– Elevated temperature

• Can harden residues

• Dry ashing not sufficient to remove residues

Page 26: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Post Etch Via Veil Residue

Via veils

Polymer residue

Page 27: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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Etch Inspection

• Traditionally manual microscope inspection• Automatic inspection systems • Critical Dimension Bias• Overetching, underetching, undercutting• Metal Corrosion• Defects can not be reworked

• Surface particle contamination can be cleaned

Page 28: Etching ( Part 3 ) - NTNUfolk.ntnu.no/jonathrg/fag/TFE4180/slides/Ch16 Etching (Part 3).pdf · Etching ( Part 3 ) Chapter 16: Semiconductor Manufacturing Technology by M. Quirk &

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TFE4180 Semiconductor Manufacturing Technology