international journal of pure and applied mathematics...

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Simulation and analysis of Transistor Clamped Nine

Level Inverters for Harmonics Reduction S. Usha

1, C. Subramani

2 and N. Saranya

3

Department of Electrical and Electronics Engineering, SRM

University, Chennai, TamilNadu

[email protected] , [email protected] and

[email protected]

Abstract This paper presents a three phase cascaded multilevel inverter

employing a six bridge power cells for obtaining a three phase, nine level

output. A five level transistor clamped H bridge configuration is used. To

achieve a balanced power distribution for the power cells, a multicarrier

phase shifted pulse width modulation technique is used. In order to

balance the capacitor voltage, phase shift pulse width modulation is used.

The obtained output voltage harmonics were analyzed with LC filter and

without filter.

Keywords and phrases: cascaded multilevel inverter, Capacitor

voltage balancing, output voltage harmonics filter, and Transistor

clamped multilevel inverter.

1 Introduction

With an increase in demand for high voltage, high power converters which are capable

of producing high quality waveforms, led to multilevel inverter development. These

converters utilize, low voltage devices and reduces switching frequencies. Research at

multilevel is still going on to further improve its capabilities to minimize components

and manufacturing cost. These power switches are cascaded in series for their

configuration at multilevel structures as they have voltage limits. This cascading in

series helps to facilitate high power conversion. Multilevel inverter output is superior in

quality which results in reducing the filter requirement and size of system. By reducing

the switching frequency, switching losses can be reduced which helps in maintaining

high power quality.

It was accounted in different applications, such as motor drives [1-3], power devices

[4-5] and distribution [6-8]. The three frequently used multilevel inverter are Diode –

Clamped inverter [9], Cascaded MLI [10] and capacitor clamped or flying capacitor

[11]. There are some topologies that were introduced and observed to be working

successfully in various industrial applications [12-13]. Selective harmonics elimination

is the modulation strategy applied to multilevel inverters [14] Carrier-based pulse width

modulation (PWM), Space Vector Modulation (SVM) and fundamental frequency or

staircase modulation. In general there are three topologies- the cascade multilevel

inverter which has the ability of achieving optimal fault tolerance because of its

modularity property. This property makes it the most reliable one. It enables the

International Journal of Pure and Applied MathematicsVolume 114 No. 7 2017, 547-557ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu

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inverter to continue operating at lower power levels after the failure of cell. Its unique

property of modularity allows the cascaded MLI to be stacked easily for high power

and high voltage applications. The cascaded MLI is typically built up by cascading

several identical single phase H bridge cells. This configuration is termed as H bridge

cane. The H bridge cane is termed symmetrical when all the DC bus voltages are equal

in series power cell. In an asymmetrical Cane, DC voltages are varied to produce more

levels of output [2]. Hence the design of inverter becomes more sophisticated as each

power cell has to be sized according to different power level including isolated DC

sources. This sophisticated construction makes symmetrical CHB modularity have an

upper hand over asymmetrical CHB, when aspect like maintenance is taken into

consideration. Also an increase in voltage level is possible without changing DC

voltage with same number of power cells, as proposed in this paper. Recently, a

transistor clamped converter topology, which provides a similar approach to increase

output level by taking different voltage levels for the series stacked capacitors has

drawn attention towards itself. This paper proposes a new configuration using a five

level output instead of three level with conventional H Bridge. A NPC in each power

cell has been presented by using a similar arrangement [3]. However with an increase

in excessive number of power switches and diode requirements has led to an increase in

number of isolated dc sources and bulky transformer. In this paper, the proposed

inverter is evaluated for medium voltage drive application based on standard voltage of

2.3 KV to 13.8 KV and power ranging from 400KW to 40 MW. In addition to better

output quality and more output levels, the occurrence of motor insulation failure which

occurred due to steep voltage waveforms (dv/dt) across the motor terminals is reduced.

Comparatively In a conventional CHV with similar cell configuration focus was given

more to constant speed drive application such as fan, blowers, pumps and compressors

as these comprise nearly 97% of currently installed medium voltage drives in various

industries, production plants, process industries and oil and gas sectors.

Inverters which convert DC power to AC power at desired power frequency constitute

the most important class of power electronic circuits. Application of inverters in

industries include AC drives, UPS, HVDC transmission lines etc. DC power inputs that

inverters can use power supply network rotating alternator, fuel cell, PV array.

Inverters that consist of silicon controlled rectifier need heavy components for

commutation action of the SCR’s. With the advancement of technology in field of

power semiconductor device, modern power electronic device such as BJT, MOSFET

and IGBT replaced SCR usage, as they did not required complex commutation circuitry

to turn of the device. In this work chapter II describe the topologies of transistor

clamped multilevel inverter. Chapter III explain about the topology of proposed

multilevel inverter. Chapter IV describe PWM scheme for the proposed inverter.

Chapter V delineate simulation circuits and results of 9 level transistor clamped H

Bridge cascaded multilevel inverter. Finally it is concluded in Chapter VI.

2 Topologies Of Multilevel Inverter

Multilevel inverter was proposed in 1981 by Nabae.A. Since then Multilevel inverters have drawn much interest in the electrical power industry in recent years. The motivation for multilevel inversion springs from the fact that the existing power devices are highly stressed or not of adequate voltage rating to operate from high voltage DC bus to realize high power inverters. Features of Multilevel inverters are well suited for drive system and power system applications such as High Voltage DC (HVDC) transmission, reactive power compensation devices, power conditioning and active power filtering so on .They were proposed as an expansion of the conventional inverters to resist increased DC link voltage produced by series connection of the semi-

International Journal of Pure and Applied Mathematics Special Issue

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conductor devices and efficient clamping voltage across each switching device in phase leg. Therefore, as a substitute for high power and medium voltage conditions, a multilevel power structure has been imported. This multilevel inverter achieves high power ratings and also allows the usage of renewable energy sources. In order to achieve high power applications, renewable energy sources like photovoltaic, wind and fuel cells can be interfaced with this multilevel inverter system. Generally the six-switch VSI is called a two-level VSI due to fact that the inverter phase voltages anV ,

bnV and cnV are instantaneously either 2

dcVor

2

dcV . In other words, the phase voltages

can take one of two voltage levels. Multilevel topologies provides an alternative option to these voltages to take out of N levels. The commonly used MLI topologies are Diode clamped MLI, Cascaded H-Bridge MLI and Flying Capacitor MLI. the advantages of multilevel inverters are Lower voltage stress on each switching device, reduced

harmonics output voltage, Stress in dt

dv is reduced, lesser distortion in input current

and Operate at lower switching frequency. The main applications can be divided into two areas. Large motor drives: These cover a wide range of high power loads like pumps in petrochemical industry, fans in cement industry, traction in transportation industry, Blowers etc. Power Systems applications: The essential applications are STATCOM, UPFC, power conditioners, grid connected system etc. Apart from these applications some other reported applications are rectifier, DC/DC Converter, fuel cell utilization, arc furnace etc.

A. Transistor clamped multilevel inverter

The transistor clamped inverter is advantageous as it requires same number of power

transistors as the level generated. Because of this property, the numbers of

semiconductor devices are reduced to half with respect to previous topologies. A 51

level converter requires 51 transistors instead of 100 transistors. This inverter is in

accordance with the linear equation mT

(1)

Where T stands for number of transistors required and m is the level generated in the

topology. The control of gate is very simple and easy due to switching ON of only one

power transistor at a time. There is also a direct relation between the output voltage and

transistor that is to be turned on. Despite of the excellent characteristics of this

topology, the transistors used are still too large and hence implementation of a practical

converter with more than 50 levels is not feasible. One of the solution to this problem is

to increase the number of steps by using H converters which can be obtained by

connecting two of the already discussed topologies in series. Also the H topology has

many redundant combination of switches position to produce the same output level. For

example, in a 51 level inverter that uses H configuration, the number of transistors

required for transistor clamped topology is 52, but only 25 power supplies are required

instead of using 50 for a single leg. Therefore the problem that was occurring with

increase in number of levels and reducing the size and complexity has been partly

rectified.

3 Topology of the proposed inverter

Figure 1 shows the cell employing an additional bidirectional switch which is

connected between the first leg of the H Bridge and capacitor midpoint. This additional

bidirectional switch enables five output voltage levels (+Vdc –Vdc, 0, +1/2Vdc, -

1/2Vdc) based on switching topologies combinations given in the table. The required

value for a 2.3-KV medium-voltage drive where each power switch is a 1.7KV IGBT.


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A two cell configuration is used in this case to produce a high quality output up to 17

voltage levels.

Figure 1: General Topology for a 5 level inverter

The maximum levels of NC cell based proposed inverter phase voltages and line are

given by the following equations:

14 NCnp

(2)

18 NCnl

(3)

4 Proposed pwm scheme

In order to describe a voltage source modulation, illustration of a modulating signal

with a triangular waveform is most important. Generally there are three alternative with

PWM strategies with different phase relationships .in the proposed method the

modulation index is given by

crr

re

VVM

2

1

(4)

Where reV is reference voltage amplitude and crrV is the amplitude of carrier signal.

Multi carrier phase-shifted PWM (CPS-PWM) which is used to produce the PWM

signals. All the triangular carrier waves carry the same amplitude, frequency and phase

shifts between adjacent carriers. Based on the number of cells, n can be obtained from

ccN

1-n2 crr , N = 1, 2 … ccN (5)

One carrier signal and two voltage references are used for signal generation. The

reference voltage of 1reV , 2reV and reV defined by

tMVre sin1

(6)

rere VV 1 (7)


550

5

2

1

12

rere VV

(8)

Though both the references are identical yet there is an offset which displaces them.

This offset is equal to the carriers’ amplitude which is ½ when reference voltage is

between2

10 reV .The pulses are generated by comparing the reference and carrier

wave. In the proposed method both switches operate at the fundamental frequency

while the others operate close to the carrier frequency with reduced switching losses.

The Generation of PWM signal with multicarrier is demonstrated in figure 2.

Figure 2: Generation PWM signal with multicarrier (14)

5 Simulation Results

Simulation of Cascaded H-Bridge is demonstrated in figure 3. In order to verify the

proposed inverter illustrated schemes, simulations were performed by using

MATLAB/SIMULINK. Figure 4 shows the Simulink model of Simulation diagram of

9 level transistor clamped H Bridge (TCHB) cascaded multilevel inverter and Pulse

generating circuit are demonstrated in figure 5 .Proposed inverter holds four main

divisions, they are namely-pulse generation unit, DC-AC conversion unit, Filter unit

and star connected load Figure 6 shows the phase voltage of Transistor clamped MLI

with 250 v magnitude.

Figure 3: Cascaded H-Bridge of Phase A, Phase B and Phase C


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Figure 4: Simulation of 9-Level Transistor clamped inverter without filter

Figure 5: Pulse generating circuit for transistor clamped Multilevel inverter

Figure 6: Output voltage waveforms for Phases A,B and C of 9-Level Transistor

clamped MLI Without filter

Figure 7 demonstrate the total harmonics distortion in the inverted output voltage

without filter is 16.76 % were compared with the harmonic obtained without using

filter. The THD value of the proposed inverters phase voltage was obtained as 26.3%

and capacitor voltage is demonstrated in figure 8.


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Figure 7: THD Analysis of Transistor Clamped MLI without Filter, THD is 16.76%

Figure 8: Capacitor Voltages

Figure 9: Simulation of 9-Level Transistor clamped inverter with filter

The nine level stepped voltage wave form is transformed to pure sinewave by the

proper design of LC filter. Figure 9 shows the simulation of Transistor clamped MLI

with LC filter. Also filter design is leaded in Figure 10 and 11.


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Figure 10 : L-C filter (L=10mH ,C=10µF)

Figure 11: Star Connected Resistive Load (R1=R2=R3=10Ω)

Figure 12: Output voltage waveforms for Phases A,B and C of 9- Level Transistor

clamped MLI With filter

Figure 13: THD Analysis of Transistor Clamped MLI with Filter, THD is 2.63%

The output voltage wave from with filter is illustrated in figure 12.Figure 13 shows the

harmonics obtained in the inverted output voltage using filter is less that value is 2.63%

were compared with the harmonic obtained without filter is 16.76%.


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Parameters Transistor

Clamped MLI

without Filter

Transistor

Clamped

MLI with

Filter

DC Bus Voltage, Vdc

300V

300V

Output voltage

285V

289V

Fundamental

frequency

50Hz

50Hz

Carrier Frequency

1KHz

1KHz

THD Value

16.67%

2.63%

Table1: Comparison transistor clamped MLI inverter with and without filter

The Table 1 represents the comparison of transistor clamped MLI with filter and

without filter. For the same input data, output voltage is high and harmonics is less in

transistor clamped MLI with filter compared to without filter also these result

compared with the conventional cascaded H-bridge inverter .The proposed method

produced reduced harmonics with less number of switches also capacitor voltage is

balanced compared to conventional method.

6 Conclusion

This paper presents a cascaded three phase multilevel inverter which can be used to

easily balance the midpoint capacitor voltage of each cell. This inverter topology

consists of nine level transistor clamped H Bridge with multi carrier phase disposition.

To achieve balanced power distribution of power cells a multi carrier phase shifted

pulse width modulation technology is implemented. Using this configuration, a third

offset harmonic injection was developed. The harmonics obtained in the inverted

output voltage using filter were compared with the harmonic obtained without using

filter. The THD value of the proposed inverters phase voltage was obtained as 26.3%.

Simulation of the above inverter topology was carried out using Simulink and the

performance wave forms obtained were verified.

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