Microelectronics Reliability xxx (2015) xxx–xxx

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Microelectronics Reliability

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Investigation on stress induced hump phenomenon in IGZO thin film transistors undernegative bias stress and illumination

Dae Hyun Kim, Jong Tae Park ⁎Department of Electronics Engineering, Incheon National University, #119 Academi-Ro Yoonsu-Gu, Incheon, 406–772, Republic of Korea

⁎ Corresponding author.E-mail address: jtpark@incheon.ac.kr (J.T. Park).

http://dx.doi.org/10.1016/j.microrel.2015.06.0240026-2714/© 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: Kim DH, Park JT, Instress and illumination, Microelectronics Rel

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Article history:Received 19 May 2015Received in revised form 19 June 2015Accepted 19 June 2015Available online xxxx

Keywords:InGaZnO thin film transistorDevice degradationHump

The cause of the stress induced hump occurrence in IGZO thin film transistor has been investigated throughexperiment and device simulation. The hole accumulation and trapping into the edge region under negativebias stress and illumination have been found to be the cause of the hump occurrence. The effects of the quantityof the hole trapped charges and the edge region length on the hump occurrence have been discussed. From thedevice simulation, the optimized device design parameters, such as the IGZO film thickness and the edge length,have been discussed to reduce the hump occurrence under negative bias stress and illumination.

© 2015 Elsevier Ltd. All rights reserved.

1. Introduction

Since the drive current degradation in IGZO thin film transistors dur-ing operation could be the cause for thefluctuation in pixel brightness indisplay devices, the optimized device structure and process to reducedevice instability have become the critical issues in display applications.The common device instabilities induced by bias stress include,threshold voltage shifts, drain current degradation, and subthresholdslope variations [1,2]. Particularly, the stress induced hump occurrenceunder positive and negative bias stress carriers (PBS and NBS) was con-sidered as one of themost serious issues of the device instability in IGZOthin film transistors [3–5]. Aswell-known, the negative shifts of transfercurves under NBS are due to the hole trapping and/or the generation ofthe donor-like states at the interface of IGZO film and the gate dielectriclayer [6,7]. It has been also reported that the stress induced humpappeared under negative bias and illumination stress (NBIS) [4,8]. Thehump phenomenon appeared when the parasitic transistor turns onfaster than the main transistor. In literature [4,9], the mechanisms ofthe hump occurrence have been explained by two different views,such as the increased hole trapping concentration at the edge regiondue to high electric field at the corner and the creation of the donor-like state together with trapped positive charges at the front channelsurface. The concrete mechanism for hump occurrence under NBIS isstill under debate. Nevertheless, a study on the optimized devicestructure and process to reduce the hump occurrence has not beenperformed so far.

vestigation on stress inducediability (2015), http://dx.doi.o

In this work, we investigated systematically the mechanism of thehump occurrence through experiment and the device simulation. Inaddition, the device design parameters of IGZO thin film transistor toreduce the hump occurrence have been discussed though the 3-D devicesimulation.

2. Device fabrication and measurement

Staggered amorphous IGZO thin film transistors with bottomMogate which were fabricated on a glass substrate have been used inthis work. The thickness of the gate dielectric layer SiNx and theamorphous IGZO (1:1:1 mol of Ga2O3:In2O3:ZnO) film were200 nm and TIGZO = 50 nm, respectively. After defining the activeIGZO channel region using photolithography and wet etching, SiOx

layer was used for the etch stop layer and passivation layer. Thesource and drain electrodes were made of a 150 nm thick Mo andall devices were finally annealed in an oven at 350 °C for 1 h. Thechannel length and width of tested transistors were 10 μm and54 μm, respectively. More detailed process was explained in ourprevious work [10]. A white halogen lamp ranging from 500 to700 nm wavelength was used as a light source. The intensity oflight source calibrated by photometry was 0.2 mW/cm2. The devicedegradation was evaluated using an Agilent B1500A semiconductorparameter analyzer.

In order to explain the measurement results of the hump occur-rence under NBIS, the device simulation has been carried out usingthe 3-dimensional SIVACO ATLAS software [11]. The setup ismatched with fabricated devices by simulating with devicedimension (i.e., a 10 μm channel length, a 200 nm gate dielectriclayer, a 54 μm channel width, a 50 nm IGZO thickness). To address

hump phenomenon in IGZO thin film transistors under negative biasrg/10.1016/j.microrel.2015.06.024

Fig. 1. Transfer characteristics as a function of stress time.

Fig. 2. Transfer characteristics after NBIS (VGS = −20 V for 2 h) and de-trapping stress(VGS = 20 V).

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the effect of the interface state on the device degradation, thephysical model of the donor-like Gaussian function has beenincluded in the simulation.

Fig. 3. Cross section view of IGZO transistor along channel width and

Please cite this article as: Kim DH, Park JT, Investigation on stress inducedstress and illumination, Microelectronics Reliability (2015), http://dx.doi.o

3. Results and discussion

Fig. 1 shows the transfer characteristics before and after NBIS for 2 h.The parallel negative shift of the transfer curves at the beginning ofstress means that the photo-generated holes were trapped at theinterface of IGZO film and the gate dielectric layer. Subsequently, aslope of the transfer curve does not change. As the stress time increases,the more negative shifts of the transfer curve and the degradation ofsubthreshold slope were observed. This means that the donor-likeinterface states have been generated together with the hole trappingat the interface of IGZO film and the gate dielectric layer. One can clearlysee the hump occurrence together with the degraded subthresholdslope when the stress time is greater than 3600 s. The turn-on voltagefor the hump appearance increases in the negative direction as thestress time progresses.

In order to identify the cause of the hump occurrence under NBIS,the experiments of de-trapping and recovery were performed. Fig. 2shows the transfer characteristics after NBIS and de-trapping stress for2 h and 900 s, respectively. To de-trap the hole trapped charge at theinterface of IGZO film and the gate dielectric layer, a positive bias stressof 20 V was applied. The hump was completely recovered after 300 sand the transfer curves were shifted further in the positive directionas the stress time progress to 900 s. However, the transfer curve wasnot shifted further in the positive direction although the de-tappingstress progressesmore. Thismeans that the hole trapped charges duringNBIS were de-trapped but the interface state charges were not de-trapped under PBS. As previous report [4,12], the interface state chargesare the donor-like states which are originated from the ionized oxygenvacancy, such as Vo+ and Vo++. Since the donor-like states are placedat deep energy level and thus stable at room temperature, they areunlikely to recover under PBS without external excitation [4,12].

Fig. 3 shows a cross sectional view of IGZO transistors along thechannel width and a schematic view of two edge regions with thehole trapped charges, which have been implemented in ATLAS 3-Dsimulator. Δx and Δy indicate the length and the height of accumulatedhole charge region. Those positive charges accumulated at the edgeregions were known to give rise to the parasitic edge channels [4].

In order to verify the cause of the accumulation of positive charge atthe edge regions, Fig. 4 shows a plot of contour of the electric field dis-tribution with a gate bias of -20 V for edge lengths Ledge = 0.5 μm.From the simulation results, one can clearly see that the electric filed

schematic view of two edge regions with hole trapped charges.

hump phenomenon in IGZO thin film transistors under negative biasrg/10.1016/j.microrel.2015.06.024

Fig. 4. A plot of contour of the field along TIGZO and the edge region for Ledge = 0.5 μm.

Fig. 5. Transfer characteristics without and with three kinds of trapped charges.

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is larger at the edge region than at the channel region along channelwidth [11]. The more concentrated electric field leads to the morehole accumulation into the edge region. Therefore, the cause of thehump occurrence can be attributed to the electric filed crowding effectsat the edge region.

In order to further investigate the cause of the hump occurrence,we compared through the device simulation the transfer character-istics without and with three kinds of charges, i.e., the positivecharges (Qh) at gate dielectric layer, the donor-like subgap densityof states (NGD) at the interface, and the hole trapped charges (Qhe)at the edge region. Fig. 5 shows the transfer characteristics withoutand with three kinds of charges. From the simulation results, thetransfer curve shifts to the negative direction but the hump doesnot appear when both Qh and NGD have been implemented. Eventhough we increase to Qh + NGD = 1 × 1013/cm2 + 5 × 1017/cm3,the hump does not appear. Therefore, it can be concluded that thehump occurrence is not caused by both Qh and NGD. However, thehump occurrence is clearly observed with the implementation ofQhe = 31012/cm2 at two edge regions. From Fig. 5, one canclearly see the hump occurrence with implementation ofQh + NGD + Qhe = 1 × 1013/cm2 + 5 × 1017/cm3 + 3 × 1012/cm2.This is proof that the Qhe in the edge region is the main factorcausing the hump occurrence. In the simulation, Δx and Δy wereassumed as 0.1 μm and 10 nm, respectively.

Considering the measurement and simulation, the device degrada-tion and hump appearance mechanism under NBIS can be explainedas follows. The photo-generated holes move toward the interface of

Fig. 6. Transfer characteristics with forward and reverse measurement modes after NBIS.

Please cite this article as: Kim DH, Park JT, Investigation on stress inducedstress and illumination, Microelectronics Reliability (2015), http://dx.doi.o

IGZO film and gate dielectric layer during NBIS. Some holes (Qh) aretrapped at the gate dielectric layer and other holes are captured bydonor-like states at the interface (NGD). The rest of the holes (Qhe) areaccumulated at the edge region due to the enhanced electric flux.However, the electrons are migrated to the back channel and trappedat the back channel interface. From the different behaviors of thetransfer curve in forward and reverse measurement modes after NBISas shown in Fig. 6, we can confirm the trapped electron charges at theback channel interface. The hump occurrence was observed in forwardsweeping but it disappeared in reverse sweeping. During the forwardsweeping, the holes trapped at the gate dielectric layer and the holestrapped at the interface may be de-trapped partly. However, the holestrapped at the edge region are not de-trapped and thus the humpdoes not disappear. During the reverse sweeping, the electrons trappedat the back channel move toward the front channel and capture theionized oxygen vacancy Vo+ and Vo++. These cations would havebeen neutralized by capturing electrons, which may explain thehysteresis in Fig. 6.

To investigate the effects of Qhe on the humpoccurrence, the transfercharacteristics according to the quantity of Qhe have been plotted inFig. 7. With constant of Ledge = 0.2 μm and TIGZO = 50 nm, the humpdoes not appear when Qhe is equal to 1 × 1012/cm2, however, it beobserved when Qhe increases to 3 × 1012/cm2. The gate voltage for thehump occurrence increases in the negative direction as Qhe increases.This means that the hump does not appear at the early state of NBISbut it appears as the stress time progresses.

The transfer characteristics with Ledge have been plotted in Fig. 8.With a constant of Qhe = 2 × 1012/cm2 and TIGZO = 50 nm, the humpappears at a certain Ledge. The hump was observed when Ledge is larger

Fig. 7. Transfer characteristics with Qhe at the edge region.

hump phenomenon in IGZO thin film transistors under negative biasrg/10.1016/j.microrel.2015.06.024

Fig. 8. Transfer characteristics with Ledge.

Fig. 9.Maximum electric filed along TIGZO and Ledge.

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than 0.2 μm. The gate voltage for the hump occurrence increases in thenegative direction as Ledge increases. Since the electric field depends onan angle between IGZO film and the edge length, the device designguide line to reduce the hump occurrence has been explored by com-paring the maximum electric fields as a function of TIGZO and Ledge.From Fig. 9, it can be clearly seen that the maximum electric field de-creases as TIGZO decreases and Ledge increases. This means that themax-imum electric field is more concentrated at the edge region than at thechannel region as an angle between IGZO film and the edge region de-creases. Therefore, it can be concluded that the edge length should beminimized to reduce the hump occurrence when the thickness ofIGZO film is constant.

Lastly, it was confirmed that the hump occurrence is not dependenton Δy but it increases as Δx increases. This result indicates that thechannel of the edge transistor is formed at the interface of IGZO thinfilm and the gate dielectric layer. Through the simulation,we confirmedthat the hump occurrence was independent of the channel width. If thehump occurrence is caused by the existence of a back channel, the sizeof hump is expected to depend on the channel width [13,14].

4. Conclusion

From the analysis of the measurement and the device simulation ofIGZO thin film transistor, we can conclude that the cause of the humpoccurrence under NBIS is due to the hole accumulation and trappinginto the edge region. When the thickness of IGZO film is constant, theedge region length should be minimized to reduce the humpoccurrence.

Please cite this article as: Kim DH, Park JT, Investigation on stress inducedstress and illumination, Microelectronics Reliability (2015), http://dx.doi.o

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