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Metal fatigue in copper pillar Flip Chip BGA: A rened acceleration model for the aluminium pad cracking failure mechanism R. Alberti, R. Enrici Vaion , A. Mervic, S. Testa STMicroelectronics, Via C. Olivetti n°2, Agrate Brianza, MB 20864, Italy abstract article info Article history: Received 22 May 2015 Received in revised form 19 June 2015 Accepted 23 June 2015 Available online xxxx Keywords: Flip Chip copper pillar Thermal fatigue CofnManson Stress free range The increasing complexity of automotive-oriented Application Specic Integrated Circuits (ASICs) pushed the industry to innovative packaging solutions that are sometimes challenged by the severe automotive quality targets. This study is related to the characterization of an advanced Flip Chip Ball Grid Array (FC-BGA) package with copper pillar interconnections, specically to its reliability performance versus the Temperature Cycling (aligned to AEC-Q100 Grade 1 perimeter). The thermo-mechanical stress due to the different Coefcients of Thermal Expansion (CTEs) of the materials in the system is the root cause of a failure event never discovered before: cracked pads at the aluminium layer level, just below the Cu pillar, showing the symptoms of metal fatigue. Starting from the consolidated CofnManson law, a rened acceleration model for this new failure mechanism is here proposed. It assumes the existence of a stress-free temperature range, which is dened as the portion of the entire thermal load that does not produce fatigue on the pillar stack. The stress-free temperature range hypothesis and the estimate of its extent were validated through a good tting of the data coming from the experimental trials performed on the aforementioned copper pillar FC-BGA package. The model obtained was employed to allow a more accurate failure rate prediction for the studied Flip Chip pack- age for automotive applications. © 2015 Elsevier Ltd. All rights reserved. 1. Introduction The increasing complexity of Application Specic Integrated Circuits (ASICs) designed for the automotive market, demands for a leap for- ward in packaging solutions, in order to shift from more traditional and well-established technologies, such as gold wire and Low Prole Quad Flat Package (LQFP), to more powerful and innovative ones, like Copper Pillar Flip Chips Ball Grid Array (CuP FC-BGA). The latter allows indeed for a more dense distribution of pads on the die and permits, as a consequence, to pin out a larger number of signals. Since copper pillar Flip Chips also offer a better thermal dissipation, they could become in the foreseeable future the elective choice in automotive for power- demanding infotainment ASICs featuring an elevate number of signal lines. This transition is not totally free of technological challenges: auto- motive customers established strict quality and reliability standards to be met by Integrated Circuit (IC) producers. The aforementioned inno- vative, at least in automotive, back-end solutions showed to be reliable in the past, although for less critical applications i.e., consumer ones. Different and unknown criticalities could arise when those technologies target to meet the aggressive automotive standards. The study described in this paper has been carried out after the dis- covery of an unknown failure mechanism concerning the CuP FC-BGA package of an automotive ASIC test vehicle submitted to aggressive automotive reliability trials [1]. Typically CuP FC-BGA technologies may suffer of intrinsic weakness during the Temperature Cycling (TC) unless optimized process parame- ters and materials are adopted. Usually cracks that develop in the low-k layer were found to be the most relevant failure cause. In our case how- ever, after stressing the test vehicle by means of TC, cracks formed in the pad outermost aluminium layer in a way that is far dissimilar from the one already described in literature [25]. The plastic deformation effect of TC stress was conrmed by our FC- BGA through experimental data collection based on Shadow Moiré technique (warpage characterization in temperature). Furthermore the reliability features of the CuP FC-BGA assembly, with various bills of materials and geometries, against TC were also investigated through the correlation of experimental results with Finite Element Analysis (FEA) simulations. Because such failure mechanism was completely unknown, an ana- lytic acceleration model for this phenomenon was investigated based on the concept of stress free temperature presented hereby. Microelectronics Reliability xxx (2015) xxxxxx Corresponding author. E-mail address: [email protected] (R. Enrici Vaion). MR-11748; No of Pages 5 http://dx.doi.org/10.1016/j.microrel.2015.06.150 0026-2714/© 2015 Elsevier Ltd. All rights reserved. Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr Please cite this article as: R. Alberti, et al., Metal fatigue in copper pillar Flip Chip BGA: A rened acceleration model for the aluminium pad cracking failure mechanism, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.150

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Page 1: Metal fatigue in copper pillar Flip Chip BGA: A refined ...homepages.laas.fr/nolhier/ESREF2015/SESSION_E1/OE1_5.pdf · This study is related to the characterization of an advanced

Microelectronics Reliability xxx (2015) xxx–xxx

MR-11748; No of Pages 5

Contents lists available at ScienceDirect

Microelectronics Reliability

j ourna l homepage: www.e lsev ie r .com/ locate /mr

Metal fatigue in copper pillar Flip Chip BGA: A refined acceleration model for thealuminium pad cracking failure mechanism

R. Alberti, R. Enrici Vaion ⁎, A. Mervic, S. TestaSTMicroelectronics, Via C. Olivetti n°2, Agrate Brianza, MB 20864, Italy

⁎ Corresponding author.E-mail address: [email protected] (R. Enrici

http://dx.doi.org/10.1016/j.microrel.2015.06.1500026-2714/© 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: R. Alberti, et al., Mcracking failure mechanism, Microelectronic

a b s t r a c t

a r t i c l e i n f o

Article history:Received 22 May 2015Received in revised form 19 June 2015Accepted 23 June 2015Available online xxxx

Keywords:Flip Chip copper pillarThermal fatigueCoffin–MansonStress free range

The increasing complexity of automotive-oriented Application Specific Integrated Circuits (ASICs) pushed theindustry to innovative packaging solutions that are sometimes challenged by the severe automotive qualitytargets. This study is related to the characterization of an advanced Flip Chip Ball Grid Array (FC-BGA) packagewith copper pillar interconnections, specifically to its reliability performance versus the Temperature Cycling(aligned to AEC-Q100 Grade 1 perimeter).The thermo-mechanical stress – due to the different Coefficients of Thermal Expansion (CTEs) of the materials inthe system – is the root cause of a failure event never discovered before: cracked pads at the aluminium layerlevel, just below the Cu pillar, showing the symptoms of metal fatigue.Starting from the consolidated Coffin–Manson law, a refined acceleration model for this new failure mechanismis here proposed. It assumes the existence of a stress-free temperature range, which is defined as the portion ofthe entire thermal load that does not produce fatigue on the pillar stack. The stress-free temperature rangehypothesis and the estimate of its extent were validated through a good fitting of the data coming from theexperimental trials performed on the aforementioned copper pillar FC-BGA package.Themodel obtainedwas employed to allow amore accurate failure rate prediction for the studied Flip Chip pack-age for automotive applications.

© 2015 Elsevier Ltd. All rights reserved.

1. Introduction

The increasing complexity of Application Specific Integrated Circuits(ASICs) designed for the automotive market, demands for a leap for-ward in packaging solutions, in order to shift from more traditionaland well-established technologies, such as gold wire and Low ProfileQuad Flat Package (LQFP), to more powerful and innovative ones, likeCopper Pillar Flip Chips Ball Grid Array (CuP FC-BGA). The latter allowsindeed for amore dense distribution of pads on the die and permits, as aconsequence, to pin out a larger number of signals. Since copper pillarFlip Chips also offer a better thermal dissipation, they could become inthe foreseeable future the elective choice in automotive for power-demanding infotainment ASICs featuring an elevate number of signallines.

This transition is not totally free of technological challenges: auto-motive customers established strict quality and reliability standards tobe met by Integrated Circuit (IC) producers. The aforementioned inno-vative, at least in automotive, back-end solutions showed to be reliablein the past, although for less critical applications — i.e., consumer ones.

Vaion).

etal fatigue in copper pillars Reliability (2015), http://dx

Different and unknown criticalities could arisewhen those technologiestarget to meet the aggressive automotive standards.

The study described in this paper has been carried out after the dis-covery of an unknown failure mechanism concerning the CuP FC-BGApackage of an automotive ASIC test vehicle submitted to aggressiveautomotive reliability trials [1].

Typically CuP FC-BGA technologies may suffer of intrinsic weaknessduring the Temperature Cycling (TC) unless optimized process parame-ters andmaterials are adopted. Usually cracks that develop in the low-klayer were found to be themost relevant failure cause. In our case how-ever, after stressing the test vehicle bymeans of TC, cracks formed in thepad outermost aluminium layer in a way that is far dissimilar from theone already described in literature [2–5].

The plastic deformation effect of TC stress was confirmed by our FC-BGA through experimental data collection based on Shadow Moirétechnique (warpage characterization in temperature).

Furthermore the reliability features of the CuP FC-BGA assembly,with various bills of materials and geometries, against TC were alsoinvestigated through the correlation of experimental results with FiniteElement Analysis (FEA) simulations.

Because such failure mechanism was completely unknown, an ana-lytic acceleration model for this phenomenon was investigated basedon the concept of stress free temperature presented hereby.

Flip Chip BGA: A refined acceleration model for the aluminium pad.doi.org/10.1016/j.microrel.2015.06.150

Page 2: Metal fatigue in copper pillar Flip Chip BGA: A refined ...homepages.laas.fr/nolhier/ESREF2015/SESSION_E1/OE1_5.pdf · This study is related to the characterization of an advanced

Fig. 2. Warpage measured at different temperatures. Temperature goes from 25 °C to150 °C in steps of 25 °C.

2 R. Alberti et al. / Microelectronics Reliability xxx (2015) xxx–xxx

2. Failure description

2.1. Sample description

The test vehicle used for this study is a fine pitch CuP FC-BGA assem-bled by Thermal Compression process flow using Non Conductive Paste(TC-NCP) and with metal lid on top. The Back-End test chip structureis an ultra low-k one with total area around 50 mm2. The Input/Output(I/O) signals on bumpoutmatrix are also placed all along chip peripheryand arranged in multiple rows. Pillars are made of Cu, while solderbumps are composed by SnAg. A thick Al layer covers the outer surfacein contact with the CuP of every metal die pad.

Fig. 1 illustrates a CuP cross-section for the test vehicle under study.

2.2. Warpage measurements

Warpage control is a critical factor in FC BGA packages: a mismatchbetween the Coefficients of Thermal Expansion (CTEs) of the silicondie and the substrate induces a significant strain on CuP and solderinterconnects during TC, which may lead to failure.

During assy manufacturing steps, the FC-BGA package experiencesdifferent thermo-mechanical deformations. After attaching the lid(one of the last steps of the assembly process), the warpage is reducedbecause the metal cap tends to pull back the substrate from bendingdownwards. Hence the flatness of the final package depends on manyparameters, like materials and geometries, and is mainly driven bytemperature.

The experimental warpage data collected on our test chip were ob-tained by Shadow Moiré measurements performed in steps of 25 °C,starting from 25 °C up to 150 °C. One interesting result, useful for ourdiscussion, is shortly presented in Fig. 2. The warpage along FC-BGAdiagonal is clearly more relevant at room and, we can infer, cold tem-perature than at hot. Moreover, warpage intensity is gradually decreas-ing with rising temperature from 25 °C to around 100 °C and thenremains constant until 150 °C. This can be explained as a relaxationcondition in the temperature range between 100 °C and 150 °C wherethe expansions and contractions of the different materials reach anequilibrium, inducing a state of minimum strain in the FC-BGA package.

2.3. Failure detection techniques

An important point is related to the detection techniques used todiscover a cracked CuP interconnection.

High coverage Final Test (FT) by means of Automatic Test Equip-ment (ATE) is carried out at every reliability readout step on 100%sample size but it is not enough for an exhaustive assessment. Afailed device can be detected through FT/ATE only if the pillar/Al

Fig. 1. CuP FC cross-section adopted for FEA modeling; “SR” stays for Solder resist (this isjust a schematization not in scale).

Please cite this article as: R. Alberti, et al., Metal fatigue in copper pillarcracking failure mechanism, Microelectronics Reliability (2015), http://dx

interconnection is open or if it shows very high resistance. It happenedthat some test vehicle units, in the earlier phase of the TC exercise,passed the electrical ATE check even if a crack was actually presentand highlighted by Focused Ion Beam (FIB) cross section (a small con-ductive path was present that made detection by ATE not effective).

For this reason, in addition to ATE, physical analysis was employedeffectively to detect the presence of crack. Although a FIB cross sectionreveals any crack symptom, it is resource and time consuming and,not less relevant, destructive.

SAM (Scanning Acoustic Microscopy) is another viable investigationmethod to detect the crack with the considerable advantage to be lessdemanding in terms of resources. However in our case also SAM is a de-structive technique, as the metal lid must be removed before scanning.A completely cracked Al pad is showed by a SAM scan as a “whitebump”, like it happens in case of a low-k layer crack; on the contrarygood bumps are dark spots. Note that cracks that are tiny or not extend-ing for a relevant portion of the metal layer are not detectable this way.An example of a SAM picture is reported in Fig. 3.

2.4. Failure mechanism description

A new type of failuremechanismwas observedwhile performing TC[6] on the described automotive product test vehicle assembled with aCuP FC-BGA package. 1000 TC proved to be a critical exercise for thiskind of devices: the range adopted for automotive AEC-Q100 Grade 1

Fig. 3. SAM scan of the bump matrix. The cracked pads show as “white bumps” (greenoval), contrast them with black dots representing intact pads (the die area is around50 mm2.)

Flip Chip BGA: A refined acceleration model for the aluminium pad.doi.org/10.1016/j.microrel.2015.06.150

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Fig. 5. Second step: crack initiation.

3R. Alberti et al. / Microelectronics Reliability xxx (2015) xxx–xxx

qualification is from −50 °C to 150 °C (Rev G was the latest one at thetime of the study). As a consequence of a thermal fatigue crack in the al-uminium pads located on the die corners, several rejects were foundafter TC.

In fact, during TC, samples are submitted to a thermo-mechanicalstress inside a chamber whose internal temperature changes cyclically.

The temperature variation causes a mechanical stress on the DeviceUnder Test (DUT) due to the different CTEs of thematerials in the struc-ture. The structure passes cyclically from a relaxed to a stressed condi-tion as temperature changes; this process eventually results in fatiguefailure of the most stressed component in the system.

A weak performance in TC was identified in the past for CuP FC-BGAstructures in general, however it always exhibited cracks in the low-klayers [2–5]. The aluminium pads in die corners are known to be morecritical from stressing viewpoint but never failed due to metal crack.This failure mechanism was never faced in similar FC-BGA configura-tions; hence the necessity to assess the risk associated and its impacton the field operative lifetime.

It was experimentally observed that this mechanism could bedescribed as a three-step process. The first one is the crack incubation:at the beginning of the TC trial the Al die pad do not present any signof cracking for a certain number of TCs, see Fig. 4.

Taking the range−50 °C/150 °C as our reference, this phase lasts forapproximately a few hundred cycles.

It can be assumed that during this period the metal structure ismodified — grains inside the metal layer have to align to allow for thecrack to develop.

The second phase is the crack onset and development: when thealuminium grains in the point of highest stress are properly placed,the crack starts and develops under the applied stress, as shown inFig. 5.

This phase goes up until more than one thousand cycles. The reduc-tion of the section onwhich the stress is applied – only the intact part ofthe die pad sustains the stress, not the cracked one – leads eventually tothe sudden failure with the formation of a crack for the whole padsurface, as in Fig. 6.

Note that the growth is not linear with the number of cycles; in factthe crack comes to cover abruptly the full die pad surface as soon as itreaches a critical extension.

The given description is well supported by Finite Element Analysis(FEA) simulations that show how the interface between the Al padand the Cu pillar is the most stressed element in this specific pull-instack, especially at the Cu pillar boundaries. The simulations, also revealthat the stress level is not the same between different Cu pillars in thebump matrix: for symmetry reasons pillars in the die corners are themost stressed (together with the respective Al pads), while those insidethe die are actually the least stressed.

Fig. 4. First step: crack incubation. The sectioned die is visible in the lower part of thepicture.

Please cite this article as: R. Alberti, et al., Metal fatigue in copper pillarcracking failure mechanism, Microelectronics Reliability (2015), http://dx

This distinction is experimentally confirmed: after thermal cycling,pillars in the corners result more severely damaged than the ones onthe edges, while the inner ones are not cracked at all.

3. Reliability characterization

It is common practice when assessing reliability characteristics of adevice to perform different accelerated stress trials each one designedto address a specific failure mode.

In particular the Coffin–Manson relation (C–M) is a widely acceptedlaw that well models the acceleration of failure mechanisms relatedwith thermal fatigue [7]. The Coffin–Manson's points of strength areits simplicity combined with a good capacity of prediction; on theother hand it could be too coarse when a high level of precision isrequired. It simply states that

Nf ¼ k � ΔT−qtrial: ð1Þ

Nf is the number of thermal cycles to fail, ΔTtrial is the thermal rangeadopted for the TC accelerated trial, k is an empirical constant of propor-tionality and q is the fatigue ductility exponent, an empirical parameterthat depends on materials and geometries. The link between C–M andAF is stated in the following formula

AF ¼ ΔT trial

ΔT field

� �q

ð2Þ

Fig. 6. Third step: crack development for the whole section length.

Flip Chip BGA: A refined acceleration model for the aluminium pad.doi.org/10.1016/j.microrel.2015.06.150

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Table 1Weibull parameters.

Trial Shape parameter (β) Scale parameter (c) [TC]

−15/125 °C 4.4285 3820−50/150 °C 4.8794 1104−65/150 °C 4.8470 768

4 R. Alberti et al. / Microelectronics Reliability xxx (2015) xxx–xxx

where AF is the Acceleration Factor and ΔTfield is the expected thermalbudget experienced on field.

Literature usually offers an indication about the most suitable qrange for the materials in the DUT [7,8]. If references do not suggesta range for the system under study, a good value can be found onthe base of past experience. Unfortunately in this case – a newfailure mechanism in an innovative package – neither historicaldata were available nor literature reported any indication about areasonable value to adopt, apart from merely generic or roughindications.

Therefore a convenient q value needed to be experimentally deter-mined: TC exercises in three different thermal ranges were launched,employing samples from the same assembly lot to limit lot-to-lotvariability. The selected thermal ranges were

1. Standard range from −50 °C to 150 °C2. Severe range from −65 °C to 150 °C3. Mild range from −15 °C to 125 °C.

Results are illustrated in Fig. 7, where three linearizedWeibull unre-liability curves F(t)fitting the experimental rejects data are showed. Theshape parameter is the same for all the fitting curves (obtained by fittingat least three experimental readouts).

A tentative value for q can be computed starting from the estimatedscale parameters (or characteristic lives) of the Weibull curves. In fact,under the hypothesis of linear acceleration, the scale parameter followsthe acceleration relation

c1 ¼ AF � c2: ð3Þ

It compares two trials: c1 is the scale parameter of the Weibulldescribing the trial with a lower level of stress and c2 is the parameterof the most stressing exercise.

Combining Eqs. (2) with (3) it can be obtained:

q ¼ln

c1c2

lnΔT2

ΔT1

: ð4Þ

It is possible to extract a value for c from every TC trial (see Table 1):In order to estimate the parameter the original form of the C–M

reported in formula (1) can be used, calling y = ln Nf and x =ln ΔTtrial the previous formula can be linearized as follow [9]

y ¼ lnk−q � x: ð5Þ

Fig. 7. Linearized Weibull log–log plot of the unreliability function F(t), where t ismeasured.

Please cite this article as: R. Alberti, et al., Metal fatigue in copper pillarcracking failure mechanism, Microelectronics Reliability (2015), http://dx

This is the equation of a linewith slope equal to− q and intercept atln k. Then it is possible to plot the natural logarithmof c on the y axis andthe natural logarithm of the trial temperature range extension on the xaxis, proceed with a linear regression and define the value of q asabsolute value of the slope coming from the linear fitting, see Fig. 8.

With this method the q extracted is qlinear reg = 3.66 with a coeffi-cient of determination R2 = 0.9965.

Looking the graph in Fig. 8 and taking these experimental points incouples, three q values can be calculated: qlow = 3.48 ; qhigh = 5.02 ;qext = 3.74.

Results do not match the expectations; in fact qhigh and qlow shouldbe equivalent or at least very close in a so small temperature range.

It would be reasonable to find a unique value for the whole temper-ature range under study. To reach a more refined estimation of q theextended C–M relation is adopted [7]

Nf ¼ k � ΔT trial−ΔTSFð Þq ð6Þ

where a newparameter is introduced:ΔTSF is the stress-free temperaturerange, the range in which the system does not undergo any permanentmodification, as it reacts elastically. The AF becomes

AF ¼ c1c2

¼ ΔT2−ΔTSF

ΔT1−ΔTSF

� �q

: ð7Þ

Two characteristics ofΔTSFmust be defined: its value and its positionrelative to the temperature boundaries of the trial (Fig. 9).

ΔTSF must be significantly smaller than the whole trial temperaturerange, it would not make any physical sense to find that almost all thethermal range of a trial is elastic. For what concerns the second point,it is reasonable to assume that the stress-free range stays in the hightemperature side because: (a) the structure is assembled at high tem-perature, hence it is in a relaxed state in this range; (b) FEA simulationstake 150 °C as the relaxed state temperature and they are able to welldescribe the system's behavior; (c) Shadow Moiré analysis showedthat substrate/die warpage is minimum at high temperature (around100 ÷ 150 °C). On these grounds the ΔTSF will be placed in the highestpart of the TC range.

Fig. 8. Scatter plot of data as per Eq. (5) and following explanation with their linear fitting.

Flip Chip BGA: A refined acceleration model for the aluminium pad.doi.org/10.1016/j.microrel.2015.06.150

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Fig. 9. Entire TC load temperature interval with the distinction between effective andstress-free ranges. Fig. 11. Fatigue ductility exponent q values for common material classes [7].

5R. Alberti et al. / Microelectronics Reliability xxx (2015) xxx–xxx

Stress free range from amathematical point of view is a concept thatallows finding a unique value for q, constant in all the explored temper-ature range. In the calculation, what is really meaningful of ΔTSF is itslower bound that has been used as a free variable. Note that the upperbound is, for our hypothesis, out of the explored experimental temper-ature range.

The effective thermal ranges for TC become

ΔTmild effective ¼ TMAX mild−TMIN mildif TMIN SFN125 °C ð8Þ

ΔTmild effective ¼ TMIN SF−TMIN mildif TMIN SFb125 °C ð9Þ

ΔTstandard effective ¼ TMIN SF−TMIN standard ð10Þ

ΔTsevere effective ¼ TMIN SF−TMIN severe: ð11Þ

Note that the last two ranges have only one form for the effectiverange, because the range to be explored is upper limited at 150 °C andTMIN SF will always be assumed equal to or lower than 150 °C in thiscomputation. The restated equations for qlow and qhigh are

qlow TMIN SFð Þ ¼ln

cmild

cstandard

lnΔTstandard effective TMIN SFð ÞΔTmild effective TMIN SFð Þ

ð12Þ

qhigh TMIN SFð Þ ¼ln

cstandardcsevere

lnΔTsevere effective TMIN SFð ÞΔTstandard effective TMIN SFð Þ

: ð13Þ

Fig. 10. Graph obtained by imposing a stress free temperature in hot TC range in order tomake equal the q values of the two different ranges.

Please cite this article as: R. Alberti, et al., Metal fatigue in copper pillarcracking failure mechanism, Microelectronics Reliability (2015), http://dx

The approach is to find the TMIN SF that gives

qlow TMIN SF� � ¼ qhigh TMIN SF

� �: ð14Þ

Note that ifqlowðTMIN SFÞ ¼ qhighðTMIN SFÞalsoqextðTMIN SFÞequals theother two values.

Employing the experimental data in Table 1 the target equation rootis TMIN SF ¼ 133 °C. The graphical representation of this computation isreported in Fig. 10.

This is a reasonable value, the stress-free range covers about the10%–15% of the total standard thermal range.

Finally the re-computed value is q = 4.23.Comparing the computed value with the ones coming from the

JEDEC standard [8], see Fig. 11, it can be noticed that q is in the rangesuggested for hard metal alloys and intermetallic layers. The crack de-velops in aluminium, which is indeed a hard metal.

4. Conclusions

A characterization regarding the reliability performances of a FlipChip BGA package with copper pillar interconnections versus the TCstress test has been here presented.

A new failure mechanismwas found, which involves the cracking ofthe aluminium pad due to metal fatigue.

A refinedmodel of the Coffin–Manson law for this kind of failurewasinvestigated and explained. Themodel is based on the concept of stress-free temperature range, defined as the portion of the entire TC load thatdoes not contribute to metal fatigue effects inside the package. Underthis hypothesis it was obtained a q value, constant in all the exploredtemperature range, suitable for an accurate field failure rate prediction.

The stress-free temperature range introduction and the methodadopted for its computation were validated by the good fitting of datacoming from experimental trials performed on FC-BGA test vehiclestudied.

References

[1] Automotive Electronic Council's Stress Test Qualification for integrated circuits, AECQ100, Rev. H, 2014.

[2] X.R. Zhang, W.H. Zhu, B.P. Liew, M. Gaurav, Copper pillar bump structure optimiza-tion for Flip Chip packaging with Cu/low-K stack, 11th. Int. Conf. on Thermal. Me-chanical and Multiphysics Simulation and Experiments in Micro-Electronics andMicro-Systems, EuroSimE 2010, pp. 1–7.

[3] S.W. Lee, B.W. Jang, J.K. Kim, Y.H. Jung, Y.B. Kim, H.G. Song, S.Y. Kang, Y.M. Kang, S.M.Lee, K.C. Park, C.S. Ju, G.R. Kim, A study on the chip-package-interaction for advanceddevices with ultra low-k dielectric, Proc. 2012 IEEE 62nd Elec. Comp. and Tech. Conf2012, pp. 1613–1617.

[4] Z. Baig, T.S. Shetty, A.R.N. Sakib, F. Mirza, D. Agonafer, Impact of replacing Sn–Agbumpswith Cu pillars on the BEoL Cu/low-k fracture under reflow— a computationalstudy, 14th IEEE ITHERM Conference 2014, pp. 473–477.

[5] K.Y. Au, F.X. Che, J.L. Aw, J.-K. Lin, B. Boehme, F. Kuechenmeister, Thermo-compression bonding assembly process and reliability studies of Cu pillar bump onCu/low-K chip, 16th IEEE Electronics Packaging Technology Conference (EPTC)2014, pp. 574–578.

[6] JEDEC Standard No. 22-A104D, Temperature Cycling, 2009.[7] JEDEC Publication No. 122G, Failure Mechanisms and Models for Semiconductor De-

vices, 2011 53–54.[8] J. McPherson, Accelerated Testing, Electronic Materials Handbook. Packaging, vol. 1,

ASM International Publishing, 1989 887.[9] P.A. Tobias, D.C. Trindade, Applied Reliability, Van Nostrand Reinhold Company, New

York, 1986.

Flip Chip BGA: A refined acceleration model for the aluminium pad.doi.org/10.1016/j.microrel.2015.06.150