2 prjct seminar

8/7/2019 2 PRJCT SEMINAR

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IMAGE EDGE DETECTION

BASED ON FPGA

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(Autonomous)SREE SAINATH NAGAR,A.RANGAMPET,

TIRUPATHI-517102

Batch No: 1106Under the esteemed guidance of:

MrMr.. RR..NAGENDRANAGENDRA..,, MM..techtech,,

AssistantAssistant ProfessorProfessor

Presented By:A.SARITHA 07121A0402

A.MIDHUN 07121A0457S.PAVAN KUMAR 07121A0474

M.UDAY 07121A0455G.SIDDARTHA 07121A0430


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CONTENTS

Objective

Existing and proposed system

Introduction to edge detection

Sobel operator and need for FPGA

Project overview

Module-1,Module-2 and Module-3

Algorithm

Results

Applications

References


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Objective

`This project presents a kind of parallel processingconstruction ofedge detection algorithm.

`Theedge of the grey image can belocated

efficiently.` Image analysis is to distinguish and count

objects, and recognize the shape of objects froman image.

`A solution to implement complex algorithms atfaster frame rates is to build custom hardware.


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Existing system

EXISTING SYSTEM

In theexisting conventional segmentation

techniques, intensity values used for

thresholding are not detected properly and

result in segmentation errors.

This processing can be performed on an FPGA

rather than a microprocessor or DSP.


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PROPOSED SYSTEM

PROPOSED SYSTEM:

Sobel Edge detection is implemented inFPGA due to its programming flexibility.


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Edges and edge detection

EDGES:

Edges are those places

in an image thatcorrespond to object

boundaries.

Edges are pixels whereimagebrightness

changes abruptly.Brightness vs. Spatial

Coordinates


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EDGE DETECTION?

An edge is an abrupt change in brightness as we

move from one pixel to its neighbor in an image.

Edge information for a particular pixel is obtained

by exploring thebrightness of pixels in the

neighborhood of that pixel.

If all the pixels in neighborhood are of same

brightness levels means no edge, if there ischange in brightness there is more chance of an

edge.


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Comparing EdgeOperators

-1 0 1

-1 0 1

-1 0 1

1 1 1

0 0 0

-1 -1 1

Gradient:

Roberts (2 x 2):

Prewitts (3 x 3):

0 1

-1 0

1 0

0 -1

Good Localization

Noise SensitivePoor Detection

Poor Localization

Less Noise Sensitive

Good Detection


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Gradient Methods SobelOperator

The3X3 convolution mask smoothes the imageby some amount ,hence it is less susceptible to noise.

ConvolutionMask

Gx = Gy=

The differences are calculated at the center pixel of themask. The gradient is calculated by using he sobel operator for each pixel in

the picture.

If the absolute valueexceeds a threshold, the pixelbelongs to an edge.

-1 0 1

-2 0 2

-1 0 1

1 2 1

0 0 0

-1 -2 -1


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WHY SOBEL

Because of its weighted coefficient ,it is

immune to noise

The accuracy rates are high when compared toother gradient methods


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HardwareModule

Power Supply

3.3V

SRAM

FPGA

SPARTAN 3

XC3S200

UART

Clock

50MHZ


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Existing System

DSP processors

Disadvantages

Inflexible architecture

Fixed data width

Limited number of MAC units

Time-shared MAC unit

Serial processing limits datathroughput

Multiple DSPs required to meetbandwidth needs

Proposed System

FPGA

Advantages

o Parallel design methodology

o Reconfigurable

o Implementdesignsat gate level

o MAC capability

o LowpowerDissipation

o Small in size

Why FPGA?


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Need for FPGA

Low power Dissipation

Small in size

Accuracy Floating point

Supports parallelism

Easily reconfigurable

Can implement larger logic funcions.


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FPGA Spartan-3 XC3S200` 220K system gates, 4320 equiv.logic cells

` 480 totalCLB (configurablelogic block)

` 30K distributed RAMbits

` 216K block RAMbits

` 12 dedicated multipliers` 4 DCM (digital clock multiplier)

` 173 user I/O, 76 differentialI/O pairs

CONFIGURABLE LOGIC BLOCK

` Main logic resource for implementingsynchronous and combinatorial circuits

` Comprised of four slices` Two logic function generators, two storage

elements, wide-function multiplexers, carrylogic, and arithmetic gates

` left-hand pair also supports: storing datausing Distributed RAM and shifting data with16-bit registers.


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Control system For FPGA

` FPGAs are programmable digitallogic chips.We canprogram them to do almost any digital function.

`We can compile the "logic function" on yourcomputer, using a software provided by the FPGA

vendor that creates a binary file that can bedownloaded into the FPGA.

`We can connect a cable from the computer to theFPGA, and thebinary file can be downloaded to the

FPGA.`That's it! our FPGA behaves according to our "logic

function".


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Project Overview

`Module 1: Conversion of the input image

into text file format using Matlab.

`Module2: Developing customlogic &

Softcore processor design.

`Module3: Configuration into FPGA using

EDK.


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Module 1

Inputimage

Mat labGUI

1-Dpixels

Textfiles

2-Dpixels


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How to read an image

a =imread('cameraman.tif');

imshow(a);

pixval on;

a =imread('flowers.tif');

imshow(a);

pixval on;


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Convert Image into One dimensional

a = imread('cameraman.tif');

[r c]=size(a);

Len=r*c;

b=reshape(a,[1 Len]);


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GUI is a user interface built with graphical objects

MATLAB implements GUIs as figure windows

MATLAB generates an M-file that contains code tohandle the initialization and launching ofthe GUI

This M-file provides a framework for the

implementation ofthe callbacks

Graphical User Interface


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Module2-Development tool


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Embedded DevelopmentTool FlowOverview

Data2MEM

Bitstream

Compiler/Linker

(Simulator)

C Code

Debugger

Standard Embedded SW

Development Flow

CPU code in

on-chip

memory

?

CPU code in

off-chip

memory

Download to Board & FPGA

Object Code

Standard FPGA HW

Development Flow

Synthesizer

Place & Route

Simulator

VHDL/Verilog

?

Download to FPGA


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XPS Functions

` Project management MHS or MSS file

XMP file

` Software application

management

Software

Design

XPS

HW/SW

Simulation

HW/SW

Debug

HardwareDesign

Platform

management Tool flow settings

Software platformsettings

Debug and simulation


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LOGIC BEHIND THE CODE

K1 K2 K3

K4 K5 K6

K7 K8 K9

R1 R2 R3

R4 R5 R6

R7 R8 R9

The coefficients of the kernel are multiplied with the pixel

values of the image taking the center pixel as R5

The resultant values are addedFOR EXAMPLE:

Y=(R1*K1)+(R2*K2)+(R3*K3)++(R9*K9)

If the pixel output value is greater than the threshlod ,the pixel

is detected as the edge

KERNEL PICTURES


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ALGORITHM

Start

Read the pixel values and Kernel values

Perform the calculations(multiplicaton followed by addition)

Compare the output with threshhold If

output>threshold

edge pixel is considered

End if


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FLOWCHART

Start

Read the pixel andkernal values

Perform the calculation

1

ifIf

output>threshold

Edge pixeldetected

stop1

1


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Configuring the FPGA

Download thebit stream

Input file download. bit

This downloads thedownload. bitfile onto the target

board using the Xilinx impact tool XPS uses theetc/download.cmdfile for downloading the

bit stream.

EDK Intro 27


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DOWNLOADING THE BITSTREAM

For downloading thebit streamlaunch XMD

and type dowexecutable.elf.

This willbe successful only when .elf file isgenerated.


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Running and detecting theedge

After a selecting the textfile fromVB, type

run in the XMD.

The text file is nothing but the input imagewhich is converted using MATLAB .

The imageedges will then be detected once

the run command is entered.


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Launching XMD


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Input Image for Edge Detection


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Edge Detected Output


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Tools used

Software

` Xilinx ISE 8.1i

` Xilinx Platform Studio

`Matlab

` Visualbasic

Hardware

` FPGA Spartan3

Language used : VHDL & C


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Applications

Enhancement of noisy images satellite

images, x-rays, medical images like cat scans

Text detection

Mapping of roads

Video surveillance, etc.

September13, 2005 EE - 6358 Computer Vision 35


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CONCLUSION

Theedge of theImage can beeffectively

detected using Sobel operator apart from the

various Gradient operators.

The result of the complex image can be

obtained at higher rates by using FPGA instead

of DSP Processors.

The Sobel operator adding the orientation of

the convolution kernels can locate accurately

theedge, and not be sensitive to noise.


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REFRERENCES

[1] P. Athanas and A. Abbott.Real-time image processing on acustomcomputing platform.In IEEE Computer, Feb. 1995.

[2]2010 Ninth International Symposium on Distributed Computing and

Applications to Business, Engineering and Science.

[3] Chanda, B. and Dutta, D.Majumdar. (2001).DigitalImage Processing

and Analysis,Prentice-Hall ofIndia.[4] Gonzalez, RafaelC. andWoods, Richard E. (2002).DigitalImage

Processing, Pearson inc.

[5] D. T.Saegusa, T.Maruyama, Y.Yamaguchi, How fast is an FPGA in image

processing?, IEICE TechnicalReport,Vol.108. No.48, 2008, pp.8388

[6] Yangli ,Yangbing. Study of FPGA based Parallel Processing of SobelOperator AIModern Electronics Technique2005.J.


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THANK YOU

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