2011 meptec media kit

2011 Media Kit

Microelectronics Packaging & Test Engineering Council

www.meptec.org

A S P E C I A L O N E - D A Y T E C H N I C A L S Y M P O S I U M

Presented by

8th Annual

MEPTEC MEMS SymposiumMEMS and IC System Integration: From Sensing to Awareness

5.20.10S A N J O S E • C A L I F O R N I A

9.22.10A S U C A M P U S • T E M P E • A R I Z O N A

2010Medical ElectronicsSymposium / Day OneSuccessful Strategies for theMedical Electronics Sector

MEPTEC&SMTAPRESENTMicroelectronics Packaging & Test Engineering Council Surface Mount Technology Association

In Association With

A S P E C I A L T W O - D A Y T E C H N I C A L S Y M P O S I U M


Presented by

Semiconductor Packaging RoadmapsApplications Driving Requirements

11.10.10S A N T A C L A R A • C A L I F O R N I A

M A Y 2 0 , 2 0 1 0 • S A N J O S E , C A L I F O R N I A

A O N E - D A Y T E C H N I C A L S Y M P O S I U M & E X H I B I T S

MEPTECPRESENTSMicroElectronics Packaging and Test Engineering Council

8th Annual

MEPTEC MEMS SymposiumMEMS and IC System Integration: From Sensing to AwarenessPresenting Companies:

• Amkor Technology

• Analog Devices

• Fraunhofer Institute for Silicon Technology (ISIT)

• Fullpower Technologies

• IMEC

• Intel Corporation

• IntelliSense

• MEMS Industry Group

• Roger Grace Associates

• Sandia National Laboratories

• Silicon Clocks

• SVTC

• University of California at Berkeley

• WiSpry, Inc.

• Yole Développement

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2010Medical ElectronicsSymposiumSuccessful Strategies for the Medical Electronics Sector

Wednesday & Thursday September 22nd & 23rd


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MEMS -DRIVING INNOVATIONExisting Technologies Enable Future Innovations page 12

SPRING 2011 MEPTEC Report 3

INSIDE THIS ISSUE

4 MEPTEC Fall Events Tackled Packaging Challenges for ICs and MEMS Devices 6

Single Digit Growth for Total Semiconductor Sales in 2011 12

QFN Packaging Advances with Routable High Density Leadframe Technology 14

The Re-Birth of Silicon Interposers?

World Class Manufacturing Services for Power Management Semiconductorspage 14

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 15, Number 1 SP

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Presented by 2.25.10S A N J O S E • C A L I F O R N I A


HOME ABOUT MEPTEC CONTACT US ADVISORY BOARD INDUSTRY PARTNERS



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Quarterly Technical Symposiums

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MEPTEC HOME OFFICEP.O. Box 222, Medicine Park, OK 73557

Bette Cooper / President650-714-1570 Fax: Toll free [email protected]

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Contact Information

www.meptec.org

2011 Media Kit 2

About MEPTEC 4

MEPTEC Membership Demographics 5

2011 Advertising Opportunities

MEPTEC Report Newsletter 6

Distribution 7

Advertising Rates and Deadlines 8

AdvertisingSpecifications 9

Technitorials 10

1/6 Page Ad Artwork Production Services 11

2011 Marketing Opportunities

Web Banner Advertising 12

NEW! Email Banner Advertising 13

MEPTEC Event Sponsorship 14

MEPTEC Event Exhibiting Opportunities 15


Contents

www.meptec.org

2011 Media Kit 3

MEPTEC (Microelectronics Packaging and Test Engineering Council) is a trade association of semiconduc-tor suppliers and manufacturers, committed to enhancing the competitiveness of the back-end portion of the semiconductor business.

Since its inception over 30 years ago, MEPTEC has provided a forum for semiconductor packaging and test professionals to learn and exchange ideas that relate to assembly, test and handling. Through our member-ship of subcontractors, semiconductor manufacturers and vendors to the back-end, and an Advisory Board consisting of individuals from different segments of the back-end semiconductor industry, we continuously strive to improve and elevate the roles of assembly and test professionals in the industry.


About MEPTEC

www.meptec.org

2011 Media Kit 4




Presented by

8th Annual

MEPTEC MEMS SymposiumMEMS and IC System Integration: From Sensing to Awareness

5.20.10S A N J O S E • C A L I F O R N I A

9.22.10A S U C A M P U S • T E M P E • A R I Z O N A

2010Medical ElectronicsSymposium / Day OneSuccessful Strategies for theMedical Electronics Sector


In Association With



Presented by





INSIDE THIS ISSUE







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INSIDE THIS ISSUE







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Presented by 2.25.10S A N J O S E • C A L I F O R N I A

As of February 2011, MEPTEC membership represents 171 companies in 21 states and 13 foreign coun-tries. Geographically, 93% of MEPTEC member companies are located in North America (U.S. and Canada), 4%intheU.K.andEurope,and2%inthePacificRimregion.

In the U.S., 321 MEPTEC members represent 161 companies in 21 states.

West Coast membership accounts for 75%, Southwest 13%, and East Coast 12%, of MEPTEC member companies in the U.S.

13%Southwest

75%West Coast

12%East Coast

2%PacificRim

4%U.K. and Europe

93%North America


MEPTEC Membership Demographics

www.meptec.org

2011 Media Kit 5

1%South America

The MEPTEC Report is published four times per year as a service to MEPTEC members and supporters. The full color publication features articles on cutting edge technology, guest editorials, industry develop-ments, and other news applicable to major issues surrounding the world of semiconductor assembly and test.

A primary goal has been to make the MEPTEC Report a mar-keting tool for MEPTEC member companies. Priority coverage is given to member companies' products, services, and technol-ogy development. Advertising in the MEPTEC Report is very cost effective when compared to other trade journals, and reaches a very targeted audience of loyal readers. With the ad-dition of a digital edition the MEPTEC Report reaches an ever increasing audience.


MEPTEC Report Newsletter

Contact: [email protected] www.meptec.org

2011 Media Kit 6



INSIDE THIS ISSUE







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Print copies of the MEPTEC Report are distributed directly to all MEPTEC members. Additionally, thou-sands of bonus copies are distributed at major industry events throughout the year. New for 2011, the MEPTEC Report is available as a digital publication distributed at no charge through the MEPTEC website.

Bonus Event Distribution

All MEPTEC Symposiums and Luncheons

APEX Expo & Conference

Del Mar Electronics Exposition & Conference

ECTC / Electronic Components and Technology Conference

GSA Suppliers Expo & Conference

IMAPS Device Packaging Conference & Exhibition

IMAPS International Symposium on Microelectronics

IWLPC / International Wafer Level Packaging Conference

Known Good Die Packaging & Test Workshop

MEMS Industry Group Executive Congress

RTI Technology Venture Forum

SEMICON West

SMTA International Exposition and Conference

SMTAPanPacificMicroelectronicsSymposium&Exhibition


MEPTEC Report Distribution


2011 Media Kit 7

Rates are effective with advertising placed in the MEPTEC Report beginning Spring 2011 Issue.

Four Color Rates (per insertion) Standard Rate Discounted Member Rate

2 page Technitorial Spread $2750 $2500

Full page $1815 $1695

2/3 vertical $1395 $1245

1/2 vertical or horizontal $1180 $1070

1/3 vertical or square $1025 $920

1/4 vertical $885 $770

1/6 vertical $350 $250

Black and White Rates (per insertion) Standard Rate Discounted Member Rate

Full page $1180 $1070

2/3 vertical $925 $820

1/2 vertical or horizontal $745 $645

1/3 vertical or square $595 $495

1/4 vertical $450 $345

Additional DiscountsA 15% discount will be allowed on pre-paid advertising for four issues or more.

Bleed ChargesNo charge for bleed on full-page, 2/3, 1/2 and 1/3 page ads. Bleed not available on 1/4 and 1/6 page ads.

Special PositionsSpecial positions are available at a premium of 10% of the space rate and include inside front cover, inside back cover, and back cover.

Deadlines

Spring 2011 Issue Ad space close: 2/25 Materials Due: 3/4

Summer 2011 Issue Ad space close: 6/3 Materials Due: 6/10

Fall 2011 Issue Ad space close: 8/26 Materials Due: 9/2

Winter 2011 Issue Ad space close: 12/2 Materials Due: 12/9


MEPTEC Report Advertising Rates and Deadlines


2011 Media Kit 8

Ad Size Non-bleed Bleed Trim

Full page 7.20 x 9.50 in. (183 x 241 mm) 8.25 x 10.75 in. (210 x 273 mm) 8.00 x 10.50 in. (203 x 267 mm)

2/3 vertical 4.60 x 9.50 in. (117 x 241 mm) 5.25 x 10.75 in. (133 x 273 mm) 5.00 x 10.50 in. (127 x 267 mm)


1/2 horizontal 7.20 x 4.60 in. (183 x 117 mm) 8.25 x 5.35 in. (210 x 136 mm) 8.00 x 5.10 in. (203 x 130 mm)


1/3 square 4.65 x 4.60 in. (118 x 117 mm) N/A N/A

1/4 vertical 3.45 x 4.60 in. (88 x 117 mm) N/A N/A

1/6 vertical 2.25 x 4.60 in. (57 x 117 mm) N/A N/A


MEPTEC Report AdSpecifications NewPublicationTrimSize:8.0in.x10.5in.


2011 Media Kit 9

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To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environ-ment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC per-formance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a labora-tory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride in being able to do the seemingly impos-sible task of following Moore’s Law. We can now put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Over the past 35 years, geometries have gone from 8 micron (8000 nm) to 4x nm, roughly doubling the number of transistors per square inch every two years. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capability viewpoint ... can we build the based on a reasonable return on investment and long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the tech-

to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Over the past 35 years, geometries have gone from 8 micron (8000 nm) to 4x nm, roughly doubling the number of transistors per square inch every two years. Minimum feature size reduction has been the big-gest driver of Moore’s Law. For years, there have been predic-tions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to main-tain Moore’s Law from a technical capa-bility viewpoint ... can we build and run equipment that will allow us to follow Moore’s Law. I think we are beginning to reach a point where we must give serious consideration to the financial aspects of Moore’s Law. Can we justify the ongoing investments to stay on the Law based on a reasonable return on investment and long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technicaf designing and building the equipment and developing the pro-cesses. There is a lot of data that sug-gests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, to recoup their investment and make a profit. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will prob-ably not be because we can’t develop the technology, but more likely be because we can’t justify the develop-ment and equipment cost. ◆

nical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensive-ly” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufactur-ing the chips, but also the cost of design-ing and building the equipment and developing the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional expense to those in the assembly/test arena, such as: probe, wafer thin, wafer bump/RDL, saw and die attach. For our industry to remain healthy, a move to 450 mm must allow vendors to recoup their investment and make a profit. Setting 450 mm aside for a moment, these same fab vendors must continue development to allow new node jumps, which have been the main driver of the law. The investments that have been made to drive minimum feature size have been very expensive. Over the past 15 years, we have moved from 350 nm (.35µ) to <40 nm. This progress alone almost follows Moore’s Law. The cost of development and equipment must The outcome of this progress is that we see fabs that cost several billion dollars and mask sets that can cost many millions of dollars. Ther very expensive. Over the past 15 years, we have moved from 350 nm (.35µ) to <40 nm. This progress cost of development and equipment must The outcome of this progress is that we see fabs that cost several billion dollars and mask sets that can cost many millions of dollars. There are opinions the recent node jumps also have yet to be recouped. There is certainly a case that can be made that a move to 450 mm with all its intendant development cost will dilute the focus and funding on node jump development to the point that no net gain will be realized. We, as an industry, take a fierce pride in being able to do the seemingly impos-sible task of following Moore’s Law. We can now put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both

NICK LANGSTON you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thOver the past 35 years, geometries.

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To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environ-ment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would i itself. It doesn’t involve packaging and itself. It doesn’t involve packaging and itself. It doesn’t involve packaging and tself. It doesn’t involve packaging and it doesn’t involve speed or other IC per-formance factors. Senode jump develop-ment to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the tech-nical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpendof data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to ably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆


To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environ-ment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC per-formance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a labora-tory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride in being able to do the seemingly impos-sible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its inten-dant development cost will dilute the focus and funding on node jump devel-opment to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of designing and building the equipment and developing the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations

and IC folks. There will, however, be some additional 450 mm To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride in being able to do the seemingly impos-sible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its inten-dant development cost will dilute the focus and funding on node jump devel-opment to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is in the ointment is the word “inexpensive-ly” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufactur-ing the chips, but also the cost of a lot equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will prob-ably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆


SPRING 2011 MEPTEC REPORT 54 MEPTEC REPORT SPRING 2011


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Law from a technical capa-bility viewpoint ... can we build the based on a reason-able return on investment and long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the techni-cal wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of designing and building the equipment and developing of data that suggests that the industry still has not fully recouped the invest-ment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab opera-tions and IC folks. There will, however, be some additional expense to those in the assembly/test arena, such as: probe, wafer thin, wafer bump/RDL, saw and die attach. For our industry to remain healthy, a move to 450 mm must allow vendors to recoup their investment and make a profit. Setting 450 mm aside for a moment, these same fab vendors must continue development to allow new node jumps, which have been the main driver of the law. The investments that have been made to drive minimum feature size have been very expensive. Over the past 15 years, we have moved from 350 nm (.35µ) to <40 nm. This progress alone almost follows Moore’s Law. The cost of development and equipment must The outcome of this progress is that we see

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different under-standing. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance fac-tors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it cost factor. It is not of many years. We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Over the past 35 years, geometries have gone from 8 micron (8000 nm) to 4x nm, roughly doubling the number of transistors per square inch every two years. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s

NICK LANGSTON you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diam-eter step roughly doubled

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years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the techni-cal wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 back of my mind, I assumed you needcost of manufactur-ing the chips, but also the cost of designing and build-ing the equipment and devel-oping the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will probably not be because we can’t develop the tech-nology, but more likely be because we can’t justify the development and equipment cost. ◆


To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different under-standing. First, it applies only to the Iduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from, fab operations and IC folks. There will, however, be some additional expense to those in as: take put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for aroundrs. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capa-bility viewpoint ... can we build and run equipment that will allow us to follow Moore’s Law. I think we are beginning to reach a point where we must give serious consideration to the financial aspects of Moore’s Law. Can we justify the ongoing investments to stay on the Law based on a reason-able return on investment and long term health of our industry? For the last couple of

years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the techni-cal wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 back of my mind, I assumed you needcost of manufactur-ing the chips, but also the cost of designing and build-ing the equipment and devel-oping the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will probably not be because we can’t develop the tech-nology, but more likely be because we can’t justify the development and equipment cost. ◆


To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different under-standing. First, it applies only to the Iduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from, fab operations and IC folks. There will, however, be some additional expense to those in as: take put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Overduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capa-bility viewpoint ... can we build and run equipment that will allow us to follow Moore’s Law. I think we are beginning to reach a point where we must give serious consideration to the financial aspects of Moore’s Law. Can we justify the ongoing investments to stay on the Law based on a reason-able return on investment and long term health of our industry? For the last couple of

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To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environ-ment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC per-formance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a labora-tory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride

of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will prob-ably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆

in being able to do the seemingly impos-sible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its inten-dant development cost will dilute the focus and funding on node jump devel-opment to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the tech-nical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensive-ly” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufactur-ing the chips, but also the cost of design-ing and building the equipment and developing the processes. There is a lot


To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environ-ment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC per-formance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a labora-tory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride

of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will prob-ably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆

in being able to do the seemingly impos-sible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its inten-dant development cost will dilute the focus and funding on node jump devel-opment to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the tech-nical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensive-ly” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufactur-ing the chips, but also the cost of design-ing and building the equipment and developing the processes. There is a lot



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2.25 x 4.6



INSIDE THIS ISSUE







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Promote your products or services with this unique advertising opportunity. Each MEPTEC Report issue will contain a limited number of “technitorial” features which will highlight different aspects of technology relevant to assembly, packaging and test. The feature will include a right-hand placed full page, four-color advertisement, and a facing full page write-up. Priced at the low cost of $2,500.00, it is essentially two full pages of advertising for the price of 1-1/2 pages.

What is a Technitorial?A technitorial is a full page write-up provided by the advertising company that is a complementary techni-cal piece to the full page advertisement, describing the company’s products or services, non-commercial in nature. It will educate and inform the reader, yet will be subtly slanted towards the company’s technology by being placed next to the company’s full page advertisement. The article will not mention the advertising company’s name, but a by-line and contact information will be allowed.

Email Gina Edwards at [email protected] for availability and to place your order.


MEPTEC Report Technitorials – A "Technical Editorial"

www.meptec.org

2011 Media Kit 10

Promote your products or services with a low cost 1/6 page four-color ad space in the MEPTEC Report. Rate includes ad artwork, if needed, created using images provided by you (photo and/or company logo) and your text.

Network Ad Rates (per insertion) Standard Rate Discounted Member Rate

1/6 page Ad $350 $250

Additional DiscountsA 15% discount will be allowed on pre-paid advertising for four issues or more.

1/6 Page Ad Specifications1/6 Page Ad artwork can be produced at no additional charge from ma-terials supplied by advertisers. Advertiser should provide one four-col-or image (either photo or company logo) and one text file. Acceptable electronic formats are as follows: Photo image or logo files need to be provided as eps, tiff, or jpeg files. Images should be at least 300 dpi at the final desired print size for best reproduction quality. Ad text should be approximately 75 words (or less) and submitted as a Word document. Please include your company website URL for inclusion at bottom of ad. Deviation from these guidelines may require additional time or cost, and/or sacrifice reproduction quality.


MEPTEC Report 1/6 Page Ad Artwork Production


2011 Media Kit 11

Shown actual size – 2.25 x 4.6"

“Time Critical” Semiconductor Substrates

BGA, CSP, Flip Chip, High Frequency, High Speed, Rigid, Cavity and

Flex Packages- 25µm Lines and Spaces -

ACL is the onlyNorth American companyfocusing exclusively on thefabrication of “Quick Turn”semiconductor packages.

Phone: 408.327.0200 Email: [email protected]

www.aclusa.com

AdvancedComponentLabs, Inc.


MEPTEC Web Banner Advertising

www.meptec.org

2011 Media Kit 12

MEPTEC banner ads are a new, low cost way to gain exposure for your company while stretching your advertising dollars. MEPTEC Banner ads start as low as $95.00 per month for a single unit banner, up $380.00 per month for a quad banner, when purchased on a 12 month contract. All banners appear in the right-handcolumnoneverypageoftheMEPTECwebsiteandarepositionedonafirst-comefirst-servedbasis. Based on the total number of banner advertisers in any given month, banner ads will be rotated with each advertiser receiving equal number of page views.

BannerAdSpecificationsAcceptedinGIFformatonly,animationpermitted.15KmaximumfilesizeforSingleunitbanner,30KforDouble,45KforTriple,and60KmaximumfilesizeforQuadbanner.PleaseprovidetheURLaddressforthespecificpagethatyouwouldliketohaveyouradlinked.

Banner Prices MEPTEC Member Rate (cost per month) Non-Member Rate (cost per month)

Single Double Triple Quad Single Double Triple Quad1 Month $125 $250 $375 $500 $150 $300 $450 $6003 Months 115 230 345 460 140 280 420 5606 Months 105 210 315 420 130 260 390 52012 Months 95 190 285 380 120 240 360 480

Contact Gina Edwards at [email protected] to place your order.



Banner Ad Sizes

Single Banner: 120 pixels (w) x 90 pixels (h)

Double Banner: 120 pixels (w) x 180 pixels (h)

Triple Banner: 120 pixels (w) x 270 pixels (h)

QuadBanner:120pixels(w)x360pixels(h)


MEPTEC Email Banner Ads

www.meptec.org

2011 Media Kit 13

A limited number of MEPTEC Monthly Update Email Banner Ads are now available to MEPTEC Members only. These banner ads cost $45.00 per month for a single unit banner, or $450.00 for 12 months when purchased on a 12 month contract. All banners appear in the left-hand column and are positioned on a first-comefirst-servedbasis.Amaximumof10bannerswillappearoneachMonthlyUpdateemail.Cur-rent monthly distribution numbers approximately 4500 recipients.

BannerAdSpecificationsAcceptedinGIFformatonly,animationpermitted.15Kmaximumfilesizeforsingleunitbanner.PleaseprovidetheURLaddressforthespecificpagethatyouwouldliketohaveyouradlinked.

Banner Prices Available to MEPTEC Members Only Single Unit Banner 1 Month $45.00 per month 12 Months $37.50 per month

Contact Gina Edwards at [email protected] to place your order.


Update for January 2011

January Luncheon - Next Week!

MEPTEC Symposium - The Heat Is On

Banner Ad Size

120 pixels (w) x 90 pixels (h)

MEPTEC offers a variety of event sponsorship op-portunities for its technical symposiums. Event sponsorship provides a valuable opportunity to promote your company brand and product or ser-vice message to attendees while supporting your business development and positioning goals.

TypicalSponsorshipBenefitsinclude:

Platinum Sponsor: $3,250 - 3 available per event• Companyname&logolistedasPlatinumSponsor on all promotional materials, including email and web promotions• Full-pageblack&whiteadineventproceedings• 3freeadmissionstosymposium• 1tabletopexhibitdisplayatevent• FeaturedasPlatinumSponsorinsymposium proceedings• 1CDofsymposiumproceedings• Companylogo/descriptiondisplayedonvideo screen at beginning of event• Signagerecognitionatevent• Exposureinsemiconductorindustrytrade magazines (deadline restrictions)• DiscountonfutureMEPTECReport1/2page or larger, 4-color ad

Gold Sponsor: $2,100 – 3 available per event• Companyname&logolistedasSponsoronall promotional materials, including email and web promotions• Full-pageblack&whiteadineventproceedings• 2freeadmissionstosymposium• 1tabletopexhibitdisplayatevent• FeaturedasGoldSponsorinsymposium proceedings• 1CDofsymposiumproceedings• Companylogo/descriptiondisplayedonvideo screen at beginning of event• Signagerecognitionatevent• Exposureinsemiconductorindustrytrade magazines (deadline restrictions)• DiscountonfutureMEPTECReport1/2page or larger, 4-color ad

Silver Sponsor: $1,250 – 10 available per event• Companyname&logolistedasSponsoronall promotional materials, including email and web promotions• 1/2pageblack&whiteadineventproceedings• 1freeadmissiontosymposium• FeaturedasSponsorinsymposiumproceedings• 1CDofsymposiumProceedings• Companylogo/descriptiondisplayedonvideo screen at beginning of event• Signagerecognitionatevent• Exposureinsemiconductorindustrytrade magazines (deadline restrictions)

Note: Sponsorship pricing and benefits may vary from event to event. For specific sponsorship details and more informa-tion contact Gina Edwards at [email protected].


MEPTEC Event Sponsorship

www.meptec.org

2011 Media Kit 14


Presented by



M A Y 2 0 , 2 0 1 0 • S A N J O S E , C A L I F O R N I A

A O N E - D A Y T E C H N I C A L S Y M P O S I U M & E X H I B I T S

MEPTECPRESENTSMicroElectronics Packaging and Test Engineering Council

8th Annual

MEPTEC MEMS SymposiumMEMS and IC System Integration: From Sensing to AwarenessPresenting Companies:

• Amkor Technology

• Analog Devices

• Fraunhofer Institute for Silicon Technology (ISIT)

• Fullpower Technologies

• IMEC

• Intel Corporation

• IntelliSense

• MEMS Industry Group

• Roger Grace Associates

• Sandia National Laboratories

• Silicon Clocks

• SVTC

• University of California at Berkeley

• WiSpry, Inc.

• Yole Développement

Orig

inal

Imag

e Co

urte

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andi

a N

atio

nal L

abor

ator

ies

MEDIA SPONSORS

TAP TIMES®

ASSOCIATION SPONSORS

SILVER SPONSORGOLD SPONSORS

Output (1) @ 100% of File Size • Final Size 31.5” x 79.75”

WELCOME

2010Medical ElectronicsSymposiumSuccessful Strategies for the Medical Electronics Sector

Wednesday & Thursday September 22nd & 23rd


In Association With


Media Sponsors

Corporate Sponsors

ASU SponsorAssociation Sponsor

MEPTEC offers table top exhibit opportunities at its technical symposiums throughout the year. A limited numberoftable-topexhibitspacesareavailableonafirst-come,first-servedbasis.Eachdrapedtableis2-6 x 6-0. The cost includes a table and chairs, a complimentary table top sign, company description in the Symposium proceedings, and one complimentary admission to the symposium. You may use your table to display literature, parts, small pieces of equipment, table top display signs, etc. A table top sign will be provided, but you may also wish to display a banner or some other appropriate type of sign on the front or top of the table.

2011 MEPTEC Symposiums

March 21 The Heat is On: Performance and Cost improvements Through Thermal Management Design

Doubletree Hotel, San Jose, CA

May 19 9th Annual MEMS Symposium – MEMS Market Evolution

Wyndham Hotel, San Jose, CA

September 27 & 28 6th Annual MEPTEC Medical Electronics Symposium (co-sponsored bt SMTA)

Arizona State University, Tempe, AZ

November 8 MEPTEC Semiconductor Packaging Symposium

Biltmore Hotel, Santa Clara, CA

November 9 Know Good Die Packaging and Test Workshop (in association with SEMI)

Biltmore Hotel, Santa Clara, CA

For more information contact Gina Edwards at [email protected].


MEPTEC Event Exhibiting Opportunities

www.meptec.org

2011 Media Kit 15

2011 meptec media kit

Documents

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t w o d