avs9 pll designhv
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Lecture 9: Com onents of
Phase Locked Loo PLL
dvanced VLSI S stems
Instructor: Saraju P. Mohanty, Ph. D.
NOTE: The figures, text etc included in slides are borrowed from various books,
websites, authors pages, and other sources for academic purpose only. The
instructor does not claim any originality.
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Lecture Outline
Overall view of a Phase Locked Loop
omponen s o a
High Level System Design omponen - w se es gn an ower
Optimization
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Phase Locked Loop
The first phase locked loop was proposed by a French scientist deBellescize in 1932
Basic idea of working: reduction of phase difference between a locallygenerated signal and a reference signal by using feedback
A Phase Locked Loop (PLL) circuit synchronizes to an input waveform withina selected frequency range, returning an output voltage proportional tovariations in the in ut fre uenc
Used to generate stable output frequency signals from a fixed low-frequencysi nal
Two types: Analog and Digital
linear relationship between the input and the output
Digital PLLs are suitable for synchronization of digital signals, clock recovery fromencoded digital data streams and other digital applications
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Phase Locked Loop (contd..)
Three fundamental purposes of a PLL
Demodulator: matched filter operating as a coherent detector
Tracker of a carrier or synchronizing signal: narrow-band filter for
removing noise from the signal and regenerating a clean replica of thesignal
Frequency synthesizer: oscillator is locked to a multiple of an accurate
reference frequency
The components of a Phase Locked Loop are:
Charge Pump
Loop Filter
Voltage Controlled Oscillator
Frequency Divider
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Phase Locked Loop (contd..)
Reference
Signal
Output
SignalVoltage
DetectorCharge Pump Loop Filter Controlled
Oscillator
Frequency Divider
Phase detector and charge
pump together form the
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High Level System Design
Behavioral-modeling languages like Verilog-AMS and Verilog-A are veryimportant tools for a top-down design methodology for circuit designers
Provide validation of the overall system
Better performance at a higher speed
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Non-ideal characteristic behavior description
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Voltage Controlled Oscillator
Oscillators are used to create a eriodic lo ic or analo si nal with a stableand predictable frequency
Types of oscillators: LC oscillators - oscillates by charging and discharging a capacitor
through an inductor
Crystal oscillators
VCO is an electronic oscillator specifically designed to be controlled inoscillation fre uenc b a volta e in ut
Current starved VCO is used
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High Level System Design of a Voltage
INSTANCE parameters Amplitude of the output signal
Centre frequency of oscillation
Oscillator conversion gain
VCO = f - f / V where f= instantaneous fre uenc f = centre
frequency of oscillation, Vin= input voltage
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Current Starved Voltage Controlled Oscillato
urren arve compr ses o
Odd numbered chain of inverters
Two input stage transistors => limit current flow to the inverter
Frequency of oscillation (fo) depends on
Size of the transistor (W/L)
Current flowing through the inverter (Iinv) which is dependent on the input
vo tage dd
So, fo = Iinv / (N*CTOT*Vdd); where CTOT is the total capacitance of the
inverter transistors
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Transistor Level Diagram of a VCO
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VCO Equations
Frequency of
Oscillation
where
and
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Analog Design and Simulation Results
Fig: Simulation waveform of the analog VCO
Fig: Transistor level circuit diagram of the VCO
Fig: Voltage versus Frequency response
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Experimental Results: Power Analysis on
Average power and Leakage power are calculated
.
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Full factorial method
ange n ou pu s u e w c ange n npu
Two values for each input; one is considered as +1 and the other as 1
Taguchi L8 design matrix
Output responses are tabulated
Average values of output responses and then (effect) values are+ -
computed Pareto diagrams: factors affecting the output response is known
Prediction equations corresponding to that particular output response iswr en us ng:
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Design of Experiments: Results Outputs:
Frequency of operation
Average power
Inputs:
Gate oxide thickness
W/L ratios for current starved
Leakage powerNMOS, current starved PMOS,input NMOS, and input PMOS
Table: DOE, Experimental results
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Design of Experiments: Pareto Diagrams
Fi : Pareto dia ram for fre uenc Fi : Pareto dia ram for avera e ower
TToxox -- Gate oxide thicknessGate oxide thickness
11 -- W/L ratio forW/L ratio for the PMOS inverter
22 W/L ratio for the NMOS inverter
transistors.
33 rat o or t e current
starved transistors.
44 W/L ratio for the NMOS current
Fig: Pareto diagram for leakage power starved transistors.
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D i f E i t P di ti
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Design of Experiments: Prediction
Prediction e uations for the out uts considered:
F^ = 786.43 - 93.36Tox + 60.3 2 P^ = 35.05 + 5.7 4 + 3.3 3 ^ = + +. . ox . .
Optimization of frequency of operation:
, ox - 2
+1
4 and 3 must be -1, as average power has to be minimized
p m za on o ea age power:
Tox and 1 must be -1 and 2 must be +1
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Frequency Divider
In any flip-flop, when a continuous train of pulse waveforms at fixedfrequency is fed to it as an input signal, an output signal of approximatelyhalf the fre uenc of the in ut si nal can be obtained
Design and Working
JK flip-flop: realized using two 3-input and two 2-input NAND gates
Fig: Circuit diagram of a J-K flip-flop
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A l D i d Si l ti R lt
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Analog Design and Simulation Results
Fig: Transistor level circuit diagram of a Fig: Simulation results of the VCO and frequency divider for
an in ut volta e of 0.7V
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Comparative Simulation Results of Analog
w er og- mo e e
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Phase Frequency Detector
Compares the phase of the local oscillator to that of the reference signal
rec s e c arge pump o supp y c arge amoun s n propor on o ephase error detected
e ec s e p ase or requency erences an pro uces e resu an errorvoltage (output is proportional to the difference in phase or frequency)
XOR gate
Four-quadrant multiplier, also known as a mixer
ang- ang c arge pump p ase etector
Proportional phase detector
A PFD is realized using two D flip-flops and one 2-input NAND gate
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High Level System Design of a Phase
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High Level System Design of a Phase
INSTANCE parameters output voltage for high
output voltage for low
Vtrans = voltages above this voltage at input are considered high
Rise time, Fall time, and Delay time Reference signal is behind the input signal => Inc_out is low & Dec_out is
high and vice versa
gure: mu at on resu ts o t e er og- co e or ase requency etectorase requency etector
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Simulation Results of the Analog
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Simulation Results of the Analog
Fig: Circuit diagram of a D flip-flop
Fig: Circuit diagram of a PFD
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Simulation Results of the Analog
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Simulation Results of the Analog
Fig: Simulation results of the PFD
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Comparative Simulation Results of Analog
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Comparative Simulation Results of Analog
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Fig: Comparative view of the simulation results of the
Dec_out signal for a PFD for the analog and Verilog-A
s stem desi n a roaches
Fig: Comparative view of the simulation results of the
Inc_out signal for a PFD for the analog and Verilog-A
s stem desi n a roaches
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Stabilizes spurious fluctuation of currents and switching time, to minimize thes urs in the VCO in ut
Manipulates the amount of charge on the filter's capacitors depending upon
the signals from the UP and DOWN outputs of the PFD
Principle: two current sources and two switches controlled by the PFD outputs
UP is High & DOWN is Low => Vout increases => sources current on to thecapacitor
outcapacitor
UP is Low & DOWN is Low => V is constant and I is zero
Power analysis proves that the designed charge pump acts as a power source
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A l D i d Si l ti R lt
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Analog Design and Simulation Results
o e arge ump
Fig: Transistor level circuit diagram of the charge Fig: Simulation results of the charge pump at an input
.
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P A l i Ch P
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Power Analysis on a Charge Pump
Average power and gate leakage power are calculated Gate leakage is a major component of leakage
ca ng n ga e ox e c ness resu s n an a arm ng ncrease n ga eleakage current due to tunneling through the thin gate oxide.
Average power calculated for the whole device = 104.732 W
Table: Power analysis on a 45 nm charge pump
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Transistor Wise Power Analysis According
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Transistor Wise Power Analysis According
Regions of operation
Triode
Saturation
Table: Power Analysis for transistor M0 according to
each region of operation in a charge pump
u - res o
Sub-threshold leakage power is avital component in the total powerconsum tion as scalin of devicedimensions and threshold voltageresults in increased sub-thresholdleakage
-negligible when compared to thetotal power
Total power consumed (transistorw se ca cu a ons s .
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L P Filt
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Low Pass Filter
Principle: Cutoff frequency of the filter is approximately equal to the
maximum frequency of the VCO => the filter will reject signals atrequenc es a ove t e max mum requency o t e
RC filter acts as a AC voltage divider circuit that discriminates against high,
Low-pass filter smoothes out the abrupt control inputs from the chargeum
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High Level System Design of a Low
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High Level System Design of a Low
ass er INSTANCE parameters
fcutoff= 1/ (2*R*C); where R=1K and fcutoff=788MHz
Figure: Simulation results of the Verilog-A code for
a low pass filter for an input voltage of 0.7Va low pass filter for an input voltage of 0.7VFigure: Simulation results of the Verilog-A code for
a low pass filter on a dB scale.a low pass filter on a dB scale.
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Analog Design and Simulation Results
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Analog Design and Simulation Results
Figure: Circuit diagram of a low pass RC filter
Figure: Simulation results for the low pass RC filterthe low pass RC filter
on a dB scale.on a dB scale.
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Comparative Simulation Results of Analog
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p g
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Pass Filter
Fig: Comparative view of the simulation results of the
low pass filter for the analog and Verilog-A system
Fig: Comparative view of the simulation results of the
low pass filter for the analog and Verilog-A system
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Mixed Signal Analysis
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Mixed Signal Analysis na og c rcu s
Signals are continuously varying voltages, currents or frequencies =>provide accuracy
analog circuits
Digital circuits
- =provide speed
Digital library can be easily built as any digital circuit would be a
elements like flip-flops Issues with Analog Circuits
Gate leakage
Mixed signal circuits g accuracy an spee a ong w ow cos an ow power consump on
provide improved system reliability and flexibility
System performance is usually limited by the a2d or d2a interfaces as the
spee o e a a convers on as o e accoun e
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Mixed Signal Analysis on VCO and
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Mixed Signal Analysis on VCO and
requency v er
VCO Analog design => Transistor level
Frequency divider Digital design => Behavioral Verilog code
Frequency of operation:
For VCO, fVCO = 717.96 MHz For analog frequency divider, fa = 358.98 MHz
For digital frequency divider, fd = 394.03 MHz
Difference in frequency is due to:
egu ar capac t ve oa ng
Gate tunneling or leakage The difference in frequencies can be removed by adding a capacitor CLOAD of
. .loading
Optimized Values of the Output Metric: ^ = .
P^ = 61.354 W
PL^ = 647.38 pW
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Mixed Signal Analysis: Experimental Results
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Mixed Signal Analysis: Experimental Results
Figure: Block diagram of the VCO along with an analog frequency divider and a digital frequency divider
,
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