time multiplexed beam-forming with space-frequency transformation
TRANSCRIPT
Analog Circuits and Signal Processing
Series Editors
Mohammed Ismail, The Ohio State UniversityMohamad Sawan, University of Montreal
For further volumes:http://www.springer.com/series/7381
Wei Deng • Reza MahmoudiArthur H. M. van Roermund
Time MultiplexedBeam-Forming withSpace-FrequencyTransformation
123
Wei DengDepartment of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands
Reza MahmoudiDepartment of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands
Arthur H. M. van RoermundDepartment of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands
ISBN 978-1-4614-5045-0 ISBN 978-1-4614-5046-7 (eBook)DOI 10.1007/978-1-4614-5046-7Springer New York Heidelberg Dordrecht London
Library of Congress Control Number: 2012943632
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Objectives of this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.4 Book Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Basic Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Receiver System Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.2 Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.3 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Phase Modulation Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3 Phased-Array Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Single and Multipath Receiver: A System Approach . . . . . . . . . . . 213.1 Translating ADC Parameters to RF Domain . . . . . . . . . . . . . . . 21
3.1.1 ADC Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.1.2 ADC Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.1.3 ADC Non-Linearity. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 Mapping ADC Parameters to System Design . . . . . . . . . . . . . . 263.3 Receiver System Optimization Method. . . . . . . . . . . . . . . . . . . 29
3.3.1 Receiver Signal Flow Diagram . . . . . . . . . . . . . . . . . . . 293.3.2 Optimization Method. . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Analog Beam-Forming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.5 Digital Beam-Forming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.6 General Case of Beam-Forming . . . . . . . . . . . . . . . . . . . . . . . 403.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
v
4 Two-Step Beam-Forming: Multiplexing Architecture. . . . . . . . . . . 454.1 Multiplexing Architecture Introduction. . . . . . . . . . . . . . . . . . . 454.2 Spatial to Frequency Mapping. . . . . . . . . . . . . . . . . . . . . . . . . 484.3 Two Steps of Spatial Filtering. . . . . . . . . . . . . . . . . . . . . . . . . 484.4 Phased-Array Analog and Digital Co-Design . . . . . . . . . . . . . . 494.5 Generalized Phased-Array System Design . . . . . . . . . . . . . . . . 49
5 Multiplexing Architecture, Ideal Behavior . . . . . . . . . . . . . . . . . . 515.1 Analog Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1.1 Properties of the Switching Signal . . . . . . . . . . . . . . . . 525.1.2 Pulse Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535.1.3 Combination in the Analog Domain . . . . . . . . . . . . . . . 56
5.2 Spatial to Frequency Mapping. . . . . . . . . . . . . . . . . . . . . . . . . 575.2.1 Space to Frequency Mapping Coefficient Dn . . . . . . . . . 575.2.2 Translation from Voltage to Power Domain, Dn to Pxn . . 615.2.3 Coarse Beam Pattern RxN by Frequency Selectivity . . . . 63
5.3 Digital De-multiplexing and Phase-Shifting . . . . . . . . . . . . . . . 655.4 Array Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 Multiplexing Architecture, Non-Ideal Behavior . . . . . . . . . . . . . . . 736.1 Angle Deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736.2 Non-Ideal Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.3 Noise in a Multiplexing System . . . . . . . . . . . . . . . . . . . . . . . 776.4 Frequency Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786.5 System Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796.6 Power Flow Diagram for a Multiplexed Architecture . . . . . . . . . 806.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7 Designs for the 30 GHz Components . . . . . . . . . . . . . . . . . . . . . . 857.1 Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857.2 LNA and Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.2.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867.2.2 Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.3 LNA-Multiplexer-Mixer Combination . . . . . . . . . . . . . . . . . . . 907.3.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907.3.2 Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937.4.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937.4.2 Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.5 Input Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977.5.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977.5.2 Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
vi Contents
7.6 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007.6.1 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007.6.2 Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027.6.3 Trouble Shooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8 System Integration and Verification . . . . . . . . . . . . . . . . . . . . . . . 1078.1 System with One Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078.2 System with Four Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.2.1 Demonstration with One Input Signal . . . . . . . . . . . . . . 1108.2.2 Demonstration with Two Input Signals . . . . . . . . . . . . . 111
8.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Contents vii
Glossary
Symbol Description Unit
A Signal amplitude VBW Bandwidth Hzcn Complex Fourier coefficients for generic switching signalc’n Complex Fourier coefficients for equal time slot duration sd Adjacent antenna distance mDn Coefficient function of the nth order harmonic VfC Carrier frequency HzfMUL Sampling rate for multiplexer in the multiplexing system HzfS Sampling rate for each path in the multiplexing system Hzk Antenna numberK Number of antennasL Power rejection ratio of desired viewing angle to
un-desired viewing anglen Harmonic numberN Number of harmonicsPxn Power contained in the nth pair of side frequency mWPyn Power transferred to the fundamental frequency from the nth pair mWRxN Array coarse pattern mWRxN Array final pattern mWSNR Signal to noise ratiotS Starting time delay of the switching signal sTS Period of the switching signal sDN Angle deviation degreeDDFE Distortion contribution by the RF front-end referred to ADC outputDNFE Noise contribution by the RF front-end referred to ADC inputDP1 Margin to the ADC full scale range powerDP2 Energy reduction from one tone input to two tone inputs (by each tone)DS Distance difference for adjacent channels in the wave
propagation directionm
Dt Progressive time delay between two adjacent channels, caused by h s
ix
a1 Positive amplitude of the switch signal Va2 Negative amplitude of the switch signal Vb1 Interference suppression flexibility of the general beam-forming systemb2 Noise reduction flexibility of the general beam-forming systemu Electric phase difference between two adjacent channels caused by h rad/degreeh Angle of incidence in spatial domain degreeØ Angle of electric phase shifter c in spatial domain degreec Electric phase shifter between two adjacent channels rad/degreek Wavelength ms Duration for each time slot (pulse width) in the multiplexing system sv1 Interference suppression flexibility of the multiplexed architecturev2 Noise reduction flexibility of the multiplexed architecture
x Glossary
Chapter 1Introduction
1.1 Motivation
Silicon-based technology has had a dramatic impact on the world of wirelesstechnology. Wireless devices have become part of our life: smart phones, satellitenavigation system, home wireless network, etc., and it is getting more and morepopular. Today we can access digital information in virtually every corner of theglobe. This trend has made the wireless communication one of the fastest growingsegments of the modern technology industry.
The vast majority of today’s wireless standards and applications are accom-modated around 1–6 GHz. This is initially due to the early technology access.Along with the technology progress indicated by Moore’s law [1], the componentsexpenses around these frequencies are getting cheaper, leading to a rapid expan-sion of these systems. One of the downsides of this expansion is the resultinglimitations of available bandwidth. The defined systems are capable of supportinglight or moderate levels of wireless data traffic. As in Bluetooth [2], its maximumdata rate is 3 Mbps at 2.4 GHz.
Driven by the customer demands, especially the fast growing wireless portabledevices market, the requirement of supporting multi-standard applications hasbeen recognized. Lacking of channel capacity has become one of the bottlenecksof low frequency applications. Furthermore, as predicted by Edholm’s law [3], therequired data rates (and associated bandwidths) have doubled every 18 monthsover the last decade. This trend is shown in Fig. 1.1 for cellular, wireless local areanetworks and wireless personal area networks for last 16 years.
Applications operating at 1–6 GHz are suitable for long distance communica-tions. However, the spectrum congestion and data rate limitation motive designersexploring new solutions. As stated by Shannon [4], the maximum availablecapacity of a communication system increases linearly with channel bandwidthand logarithmically with the signal-to-noise ratio. Therefore, one of the choices isto look upwards in the high frequencies where more bandwidth could be available.
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_1,� Springer Science+Business Media New York 2013
1
One of the high frequency applications is the indoor personal communicationsand wireless fidelity at 60 GHz [5]. Around 7 GHz spectral spaces has beenallocated worldwide for unlicensed use. In order to design circuits at 60 GHz, thetransistor cut-off frequency fT needs to be typically around 200 GHz. At thismoment, the process for making such a device is still relatively expensive thanlower frequency transistors. On contrary, making transistors with fT around100 GHz is quite matured in worldwide foundries increasing availability at low-cost. Therefore and in order to demonstrate the principles outlined in this book, thesystem and circuits are implemented at 30 GHz.
Besides, there are two applications defined by the Federal CommunicationsCommission (FCC) around 30 GHz. Local Multipoint Distribution Services(LMDS) [6], can be considered as one of these applications. It is a broadbandwireless access technology originally designed for digital television transmission(DTV). It was conceived as a fixed wireless, point-to-multipoint technology forutilization in the last mile. LMDS commonly operates on microwave frequenciesacross the 26 GHz and 31 GHz bands. Another application is the satellite Ka-bandcommunication [7]. Ka-band transmission is viewed as a primary means formeeting the increasing demands for high data rate services of space explorationmissions. At Ka-band, deep space communications is allocated 500 MHz ofbandwidth compare to the 50 MHz of bandwidth allocated to the X-band [8];leading to even greater increase in throughput when using Ka-band.
1.2 Background
At 30 GHz, the wave propagation path loss, the noise of the receiver, and theoutput power of the transmitter are more problematic to cope with than lowfrequencies. However, at this frequency, the millimeter-wave operation canfacilitate very small antenna apertures for the array receptors, since the electro-magnetic wavelength is very short. This property allows highly miniaturized,
Fig. 1.1 Data rate trendpredicted by Edholm’s law
2 1 Introduction
lightweight phased-array to be manufactured, a key for compensating the path lossand alleviating the RF transceiver front-end requirements.
The ability to individually control both amplitude and phase of each element inthe array is known as beam-forming1 [9]. Beam-forming can be separated into twocategories: analog beam-forming, and digital beam-forming. As indicated by itsname, analog beam-forming controls the amplitude and phase of each element inthe analog part of the receiver chain. Phase shifters are commonly used in theanalog beam-forming phased-array architecture for adjusting the phase of eachantenna path and steering the beam [10–11]. Phase shifter can be implemented indifferent parts of a transceiver, such as at RF [12–15], at IF [16–19], or at LO[20–22]. On the other hand, digital beam-forming controls the amplitude and phaseof each element in the digital part of the receiver chain. As a result, the phaseshifter is implemented in the digital domain by various algorithms [23–27]. Inpractice, these two beam-forming techniques have their own pros and cons. Theanalog beam-forming technique enhances the SNR and rejects the interferencesbefore the ADC and the ADC dynamic range is relaxed. However, due to the phasecompensation in the analog domain, the phase information of the incidence signalis not available for digital signal processing. On the other hand, the digital beam-forming technique conveys the incidence signal amplitude and phase informationinto the digital domain, which provides more flexibility. Nevertheless, the hard-ware implementation per antenna channel, especially the power hungry ADCs,will increase the overall power consumption, area and cost. The demand for aflexible phased-array architecture that takes advantage of both analog and digitalbeam-forming is enormous.
In the past few years, research has been performed in this area. Reference [28]presents a technique for realizing phase-amplitude weighting for phased-arrayantennas using sampling of antenna elements signals. In this architecture, beam-forming is achieved in the analog domain. Traditional phase shifters are replacedby programmable switches that improve the flexibility of the analog beam-form-ing. The drawback for this architecture is similar as other analog beam-formingstructures: phase information of the incidence signal is lost before the digital signalprocessing, which limits the further flexibility improvement. Reference [29] pre-sents a code-modulating path-sharing multi-antenna receiver for spatial multi-plexing and beam-forming. It uses code modulation in the RF domain todistinguish antenna signals before combining them and sending the resulting signalthrough a single path, so it is possible to recover the signals in the digital domain.This architecture realizes beam-forming in the digital domain, and compared todigital beam-forming, it reduces hardware consumption in the analog domain. Thedrawbacks for this architecture are that the signal bandwidth expansion after thechannel coding requires a very demanding ADC, and the coding complexity makes
1 Phased-array architecture is usually used together with beam-forming technique. Sometimes,we also use ‘beam-steering’ or ‘beam-patterning’. In this book, we only use ‘beam-forming’ forsimplicity.
1.2 Background 3
it not suitable for a large number of arrays. Instead of code modulation, reference[30] presents a similar concept using a time division multiplexed scheme fordigital beam-forming which achieves a reduction of RF hardware by multiplexingseveral individual elements of the antenna array into a single RF channel prior tothe LNA, and de-multiplexing the combined signal before the analog low passfilter and ADC. This architecture has only limited improvement on the hardwareconsumption, and it achieves no improvement on the use of multiple ADCs. Itintroduces a noise problem because the pin diode multiplexer is placed before theLNA.
1.3 Objectives of this book
As previously mentioned, current literature mostly focuses on phased-array circuitimplementations. A system approach analysis method is lacking. This leads to anon-optimized result. Furthermore, a flexible phased-array receiver that can relaxthe ADC design in the analog domain (advantage of analog beam-forming), andstill preserves the initial phase information in the digital domain (advantage ofdigital beam-forming) is needed. Moreover, from implementation point of view,the possibility to realize this idea at 30 GHz with low-cost technology is of par-ticular interested. Hence, the main objectives of this book are therefore:
• provide a system approach analysis method for phased-array receivers.• investigate a flexible phased-array structure with both analog and digital beam-
forming properties.• investigate a real low-cost integrated solution of the 30 GHz phased-array front-
end system and verify its performance and to draw conclusions on future work.
The strategy followed for the first objective is to introduce a system optimi-zation method for a single path receiver; mapping a phased-array receiver to anequivalent single path receiver model; and then apply the optimization method tothe equivalent model.
The strategy followed for the second objective is shown in Fig. 1.2. It shows afunctional block diagram of such a phased-array receiver. It combines K paths intoone path by an analog combination block, with initial phase information preserved.Then, an analog signal processing block processes the combined signal to relax theADC design. After the ADC, the digital signal processing block separates thecombined signal into the original K paths, and the initial phase information isrecovered. The phase shifters are implemented in the digital domain just like atraditional digital beam-forming. And, at last, the phase compensated signals areadded together to form the desired beam-pattern.
The strategy followed for the third objective is: based on the provide tech-nology, identify the critical components of the system and characterize themindividually at 30 GHz before complete system integration; implement systemfirstly with only one channel to check the initial integration performance;
4 1 Introduction
implement the complete phased-array system with four channels and verify themeasurement result with pre-developed theory.
1.4 Book Outline
This book is organized in the following way. Chapter 2 introduces some basicsconcepts and required theories that will be used in the following chapters. To bemore particular, it includes receiver system basics, phase modulation basics, andphased-array basics. Chapter 3 provides a system approach analysis method forsingle and multi-path receivers, which is the answer to the first objective of thisbook. The strategy followed is applied to analog and digital beam-forming in thischapter. Using the results from the previous analysis, the system approach for thegeneral case of beam-forming is extracted.
Chapters 4–6 provide a multiplexing architecture with analog and digital beam-forming properties, which is the answer to the second objective of this book.Chapter 4 introduces the architecture, and the tagged along new concepts. Chapter5 provides a detailed analysis for the multiplexing architecture. Chapter 6 studiesthe non-ideal behaviors of this architecture.
Chapters 7 and 8 are about the circuit and system implementation of themultiplexing phased-array architecture, which is the answer to the third objectiveof this book. Chapter 7 addresses the component design at 30 GHz. Chapter 8discusses the system integration of the individual components listed in Chap. 7.Note that this book mainly covers the multiplexing phased-array receiver part. Forthe transmitter part, only a power amplifier component design is described in Sect.7.6 to explore the feasibility. Chapter 9 is reserved for conclusions.
Analog combination
Analogsignal
processingADC
Digital signal
processing
Output
Digital domain
1
2
k
K
1
2
k
K
delay1
Phase-shifter
delay2
delay3
delay4
Fig. 1.2 Flexible phased-array receiver shown in functional blocks
1.3 Objectives of this book 5
Chapter 2Basic Concepts
This chapter introduces some basics concepts and required theories that will be usedin the following chapters. Section 2.1 explains basic concepts in communicationsystems, including noise, linearity, and dynamic range which will be frequently usedin Chaps. 3 and 4. Section 2.2 explains phase modulation basics, which will be usedas the guideline to analysis and explain the multiplexing phased-array system inChap. 4. Section 2.3 discusses the basic theory of phased-array.
2.1 Receiver System Basics
Noise and linearity are the most frequently used concepts in receiver designs. Lownoise and high linearity are desired and demanded in most communication sys-tems. However, to achieve low noise and high linearity is not always easy.
2.1.1 Noise
The noise performance of the receiver is measured with noise factor (F), which is ameasure of how much the signal-to-noise ratio is degraded through the system[31]. We note that
F ¼ SNRin
SNRout¼ Sin=Nin;source
Sin � Gð Þ=Nout;total¼ Nout;total
Nout;source¼ 1þ Nout;added
Nout;sourceð2:1Þ
where Sin is the available input signal power, G is the available power gain, Nout,
total is the total noise power at the output, Nout, source is the noise power at theoutput originating at the source, and Nout, add is the noise power at the output addedby the electronic circuitry. This shows that the minimum possible noise factor,
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_2,� Springer Science+Business Media New York 2013
7
which occurs if the electronics adds no noise, is equal to 1. Noise figure NF isrelated to noise factor F by
NF ¼ 10 log10 F ð2:2Þ
It can be derived that NF is the ratio of the receiver’s signal-to-noise ratio(SNR) at the output to that at the input, which can be expressed in dB format asfollows
SNRout;dB ¼ SNRin;dB � NF ð2:3Þ
Equation (2.3) indicates that the NF represents the amount of SNR degradationafter the signal is processed by the receiver.
In Fig. 2.1, assuming that all stages are matched to the system characteristicimpedance, the overall noise factor of the system is determined by the gain and noisefactor of each stage as in (2.4), and the overall gain of the system is shown in (2.5)
Ftotal ¼ F1 þF2 � 1
G1þ F3 � 1
G1G2þ � � � þ Fn � 1
G1G2 � � �Gn�1ð2:4Þ
Gtotal ¼ G1 � G2 � � �Gn�1 � Gn ð2:5Þ
.Equation (2.4) is known as Friis’s formula [32], which indicates that the noise
factor of the first stage is most critical to the system noise performance because thenoise due to each cascade stage is suppressed by the available power gain pre-ceding it.
Figure 2.2 shows the equivalent noise model of a single receiver stage. Neq,in isthe input equivalent noise, and Neq,out is the output equivalent noise.
The output equivalent noise can be expressed as
Neq;out;dBm ¼ Neq;in;dBm þ GdB
¼ Nfloor;dBm þ NF þ GdBð2:6Þ
where Nfloor represents the noise floor of the stage. In a cascaded system (Fig. 2.1),the output of one stage feeds the input of the next. The total output equivalentnoise can be expressed as
Ntotal; eq; out; dBm ¼ 10 log kT � BWð Þ þ NFtotal þ Gtotal; dB
¼ �174dBmþ 10 logðBWÞ þ NFtotal þ Gtotal; dBð2:7Þ
G1
N F1
G2
N F2
G3
N F3
Gn
N Fn
Fig. 2.1 Noise cascading system
8 2 Basic Concepts
where kT*BW is the receiver input noise floor, and NFtotal and Gtotal are the systemtotal noise figure and gain, respectively. In (2.7), k = 1.38*10-23 J/K is theBoltzmann’s constant [33]. T is the temperature. BW is the bandwidth in Hertz. kTcorresponds to the minimum equivalent noise per Herz for a receiver at room tem-perature (290 K), that is -174 dBm/Hz. NFtotal is the total noise figure of the system,and it is derived in (2.4). Gtotal is the total available gain (in dB) of the system, and it isderived in (2.5).
2.1.2 Non-Linearity
Any unwanted signal fed into a receiver is called interference and it generallydegrades the signal to noise ratio of the wanted signal. Most interference comesfrom the signals intended for other users or other applications. The interferencepower can be orders of magnitude higher than the desired signal power and maycorrupt the signal as a result of receiving non-linear behavior. Any real receiver isa nonlinear system that responses linearly only if the input signal is sufficientlysmall. When the input signal increases beyond some extent, the nonlinear behaviorof the receiver becomes evident.
If a sinusoid is applied to a nonlinear system, the output generally exhibitsfrequency components that are integer multiples of the input frequency. They arecalled harmonics of the input frequency.
For simplicity, assuming nonlinear property of the system can be written asTaylor expansion, we limit our analysis to third order, and assume nonlinear termsabove the third order are negligible, y(t) in Fig. 2.3 can be derived as
yðtÞ ¼ a1A � cos xtð Þ þ a2A2 � cos2 xtð Þ þ a3A3 � cos3 xtð Þ
¼ a2A2
2|ffl{zffl}
DC
þ a1Aþ 3a3A3
4
� �
cos xtð Þ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
fundamental
þ a2A2
2cos 2xtð Þ þ a3A3
4cos 3xtð Þ
|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
harmonics
ð2:8ÞOne figure of merit for receiver linearity is the gain compression point. The-
oretically, the receiver’s output power increases linearly with the injected inputpower regardless of the input power level, as shown in Fig. 2.4 [34] by the dashedline. The solid line in Fig. 2.4 depicts a typical input/output transfer function of areal receiver.
It can be seen that at low input power level, the real I/O curve can be approxi-mated with the straight line. As Pin increases, Pout gradually deviates from the linearcurve and is eventually saturated. The point at which Pout is 1 dB lower than its
G
N FNeq ,in Neq ,out
Fig. 2.2 Equivalent noisemodel of a single receiverstage
2.1 Receiver System Basics 9
linear theoretical value is called the input 1-dB compression point (ICP1 dB). Theimportance of this point is that it indicates where the receiver starts to leave the linearregion and the saturation becomes a potentially serious problem. The receiver alsogenerates spurs at the harmonics of the signal frequency when the receiver goes intocompression.
Figure 2.5 shows two closely spaced interferences at f1 and f2 in the vicinity ofsignal band, where the strongest interference commonly originates. After passingthe nonlinear system, the output signal ytwo(t) can be derived as
ytwoðtÞ ¼ a1xtwoðtÞ þ a2x2twoðtÞ þ a3x3
twoðtÞ¼ a2A2 � � � DCð Þ
þ A a1 þ94a3A2
� �
cos x1t þ cos x2t½ � � � � Fundamentalð Þ
þ 12a2A2 cos 2x1t þ cos 2x2t½ � � � � HD2ð Þ
þ a2A2 cos x1 þ x2ð Þt þ cos x1 � x2ð Þt½ � � � � IM2ð Þ
þ 14a3A3 cos 3x1t þ cos 3x2t½ � � � � HD3ð Þ
þ 34a3A3
cos 2x1 þ x2ð Þt þ cos 2x1 � x2ð Þt½ �þ
cos 2x2 þ x1ð Þt þ cos 2x2 � x1ð Þt½ �
( )
� � � IM3ð Þ
ð2:9ÞOne of the important linearity specifications in (2.9) is the third-order inter-
modulation point (IM3). When the interference power is high enough, the receivergenerates noticeable spurs at ± nf1 ± mf2 due to intermodulation, where n andm are integers including zero. Two of these spurs, located at 2f1 - f2 and 2f2 - f1,
Fig. 2.3 Nonlinear system,one-tone input
1dB
ICP 1dB
OCP 1dB
Pin
[dBm ]
Pout
[dBm ]
Fig. 2.4 1-dB compressionpoint
10 2 Basic Concepts
are particularly threatening to the received signal because they can fall into thesignal band and become impossible to eliminate by filtering. The power of the 3rdorder distortion increases 3 dB per 1 dB increase of the input power. Figure 2.6shows the typical curves of the main tone and the third-order intermodulation poweras a function of Pin.
The third-order interception point is obtained by extrapolating the main-toneoutput at the slope of 1 dB/1 dB and the third-order distortion curve at 3 dB/1 dBfrom the low input power level until they intersect with each other, as shown inFig. 2.6. The x-coordinate of the intersection point is called the input referredthird-order interception point (IIP3), and the y-coordinate is called the outputreferred third-order interception point (OIP3).
In a cascaded system as shown in Fig. 2.1, the overall IIP3 of the system isgiven by
1IIP3; total
¼ 1IIP3; 1
þ G1
IIP3; 2þ G1G2
IIP3; 3þ � � � þ G1G2G3 � � �Gn�1
IIP3; nð2:10Þ
It can be seen from (2.10) that in a cascade system the linearity requirements onthe receiver components at the back-end are more stringent because their effects onthe overall system are ‘magnified’ by the preceding gain. We should emphasizethat (2.10) is merely an approximation. In practice, more precise calculations orsimulations must be performed to predict the overall IP3.
2.1.3 Dynamic Range
Dynamic range (DR) is defined as the ratio of the maximum input power level thatthe circuit can tolerate to the minimum input power level that the circuit canproperly detect [35]. DR specifies how well the system can handle signals withvarious power levels.
The lower bound of the dynamic range is set by the receiver sensitivity, definedas the lowest input signal power a receiver can appropriately process. To calculatethe receiver sensitivity, one starts from the maximum bit error rate (BER) the datatransmission can tolerate in the absence of interference. To achieve this BER, thereceiver must provide a minimum SNRout to the subsequent demodulator. There-fore, a minimum SNRin must be achieved at the receiver input, which is given by
SNRin;min; dB ¼ SNRout;min;dB þ NFtotal ð2:11Þ
Assuming the receiver input is impedance matched to the antenna, the receiversensitivity can be obtained as
Fig. 2.5 Nonlinear system,two-tone input
2.1 Receiver System Basics 11
Pin;min;dBm ¼ NFtotal þ 10 log kT � BWð Þ þ SNRout;min;dB
¼ NFtotal � 174dBmþ 10 logðBWÞ þ SNRout;min;dBð2:12Þ
The upper limit of the dynamic range has various definitions that result indifferent bounds [36], but all are related to the linearity of the receiver. Forinstance, the most common definition, the spurious-free dynamic range (SFDR),defines the maximum allowed input signal power as the one causing the maximumintermodulation product equal to the output noise power. From Fig. 2.6, this inputpower level can be solved by using the graphical method, which is given by
Pin;max; dBm ¼23
IIP3; total; dB þ13
NFtotal � 174dBmþ 10 log BWð Þ½ � ð2:13Þ
From (2.12) and (2.13), the receiver dynamic range can be found by
DRdB ¼ Pin;max; dBm � Pin;min; dBm
¼ 23
IIP3; total; dB � NFtotal þ 174dBm� 10 log BWð Þ� �
� SNRout;min; dB
ð2:14Þ
2.2 Phase Modulation Basics
Modulation is the process of modifying a high-frequency signal (called the carriersignal) with low-frequency information (called the modulating signal). The twomost common types of modulation are amplitude modulation (AM) and frequencymodulation (FM) [37]. These two forms of modulation modify the carrier’samplitude or frequency, respectively, according to the instantaneous value of themodulating signal. Phase modulation (PM) is similar to frequency modulation(FM) except that the phase of the carrier waveform is varied, rather than itsfrequency.
P in
[dBm]
P out
[dBm]
1st
3rd
IIP 3
Fig. 2.6 Third order inputintercept point
12 2 Basic Concepts
Assume carrier signal vc(t) and modulating signal vm(t)
tc tð Þ ¼ Vc cos hc tð Þ½ �¼ Vc cos 2pfct þ /cð Þ
ð2:15Þ
tm tð Þ ¼ Vm cos 2pfmtð Þ ð2:16Þ
where V, f, and Ø are the amplitude, frequency and phase, respectively. Combining(2.15) and (2.16), the phase modulated signal in time domain is given by
tpm tð Þ ¼ Vc � cos 2pfct þ /c þ kp � tm tð Þ� �
ð2:17Þ
The instantaneous phase Øi of the carrier is
/i ¼ /c þ kp � tm tð Þ ð2:18Þ
where kp is the change in carrier phase per volt of modulating signal, called phasesensitivity (rad/volt). Øc is usually 0. Defining b as the phase deviation, the maxamount by which the carrier phase deviates from its unmodulated value, we get
b ¼ kp � tm tð Þj jmax¼ kp � Vm ð2:19Þ
Substituting (2.19) into (2.17), the phase modulated signal can be expressed as
tpm tð Þ ¼ Vc � cos 2pfct þ kp � Vm � cos 2pfmtð Þ� �
¼ Vc � cos 2pfct þ b � cos 2pfmtð Þ½ �ð2:20Þ
Expanding the above equation with Fourier analysis, and using the Besselfunction [38] to determine the spectrum of a phase modulated signal, we achieve
tpm tð Þ ¼ Vc � J0 bð Þ � cos 2pfctð Þ
þ Vc � J1 bð Þ � cos 2p fc þ fmð Þt þ p2
h i
þ cos 2p fc � fmð Þt þ p2
h in o
þ Vc � J2 bð Þ � cos 2p fc þ 2fmð Þt þ p½ � þ cos 2p fc � 2fmð Þt þ p½ �f g
þ Vc � J3 bð Þ � cos 2p fc þ 3fmð Þt � p2
h i
þ cos 2p fc � 3fmð Þt � p2
h in o
þ Vc � J4 bð Þ � cos 2p fc þ 4fmð Þt½ � þ cos 2p fc � 4fmð Þt½ �f g
þ Vc � J5 bð Þ � cos 2p fc þ 5fmð Þt þ p2
h i
þ cos 2p fc � 5fmð Þt þ p2
h in o
þ � � � ð2:21Þ
Figure 2.7 shows the Bessel function Jn(b) versus b for n = 0 to n = 6.Some properties of the Bessel function can be discovered as follows:
• The higher side frequencies are insignificant in the PM spectrum when b is low.• When b B 0.25, only J0(b), J1(b) have a significant value.
2.2 Phase Modulation Basics 13
The power in a sinusoidal signal depends only on its amplitude and is inde-pendent of frequency and phase. It follows that the power in a PM signal equals thepower in the un-modulated carrier
PPM ¼12� V2
c ð2:22Þ
The total power in a PM signal is the sum of the power of the sidebands and thecarrier power. Hence, for the 1-tone modulation, the total power can also beobtained by summing the power in all spectral components in the PM spectrum
PPM ¼12
V2c ¼
12
V2c J2
0 bð Þ þ 2X1
n¼1
J2n bð Þ
" #
ð2:23Þ
Obviously, the power in the side frequencies is obtained only at the expense ofthe carrier power
J20 bð Þ þ 2
X1
n¼1
J2n bð Þ ¼ 1 ð2:24Þ
Power contained in the carrier frequency and the first N pairs of sidefrequencies is given by
Fig. 2.7 Bessel functions forn = 0 to n = 6
14 2 Basic Concepts
rN ¼ J20 bð Þ þ 2
XN
n¼1
J2n bð Þ ð2:25Þ
Because the exact spectrum of the phase modulated signals is difficult toevaluate in general, formulas for the approximation of the spectra are very useful.As a rule-of-thumb, when N = b ? 1
rbþ1 ¼ J20 bð Þ þ 2
Xbþ1
n¼1
J2n bð Þ ¼ 0:9844 ð2:26Þ
Equation (2.26) indicates that approximately 98 % of the power of a phasemodulated signal lies within the bandwidth covered by the first N = b ? 1 pairs ofside frequencies. It is the minimum number of pairs of side frequencies that alongwith fc., account for 98 % of the total PM power. Carson’s bandwidth can bedefined as
BWc ¼ 2 � bþ 1ð Þ � fm ð2:27Þ
This formula gives a rule-of-thumb expression for evaluating the transmissionbandwidth of PM signals; it is called Carson’s rule [39]. It gives an easy way tocompute the effective bandwidth of PM signals from power perspective. In laterchapters, this method will be used to evaluate the effective bandwidth of the timemultiplexed receiver.
2.3 Phased-Array Basics
Phased-array antenna systems is one of the widely used multiple antenna systems inhigh frequency applications. In wave theory, a phased-array is a group of antennasin which the relative phases of the respective signals feeding the antennas are variedin such a way that the effective radiation pattern of the array is reinforced in a desireddirection and suppressed in undesired directions [40]. Comparing with a conven-tional single path antenna system, two of the main benefits that a phased-array canprovide are signal to noise ratio (SNR) enhancement and interference suppression[41–47] as a result of beam-forming.
A phased-array receiver consists of several signal paths, each connected to aseparate antenna. Generally, radiated signal arrives at spatially separated antennaelements at different times. An ideal phased-array compensates for the time-delaydifference between the elements and combines the signal coherently to enhance thereception from the desired direction, while rejecting emissions from other direc-tions. The antenna elements of the array can be arranged in different spatialconfigurations.
Figure 2.8a shows a simplified phased-array system model. For a plane wave, thesignal arrives at each antenna element with a progressive time delay Dt as in Fig. 2.8b.
2.2 Phase Modulation Basics 15
This delay difference between two adjacent elements is related to their distance d andthe signal angle of incidence h by
Dt ¼ d � sin hc
ð2:28Þ
where c is the speed of light. While an ideal delay can compensate the arrival timedifferences at all frequencies, in narrow-band applications it can be approximatedvia other means. For a narrow-band signal, the amplitude and phase change slowlyrelatively to the carrier frequency. Therefore, we only need to compensate for theprogressive phase difference
u ¼ b � DS ¼ 2pk� d sin h ð2:29Þ
Where u is the electric phase difference between two adjacent channels; b is thephase constant; DS is the distance difference for adjacent channel in the wavepropagation direction; k = c/f is the wave-length in the air. Assume that d = k/2,
u ¼ p � sin hDt ¼ sin h
2f
�
ð2:30Þ
For example, the incoming angle of 7.2� corresponds to an electrical phase shiftof 22.5�. From the above equation, we can also find the relation between u and Dt as
u ¼ 2p � Dt
TSð2:31Þ
where Ts is the period of the propagation wave. Figure 2.8b shows the relationbetween time and phase.
In a receiver chain, for a given modulation scheme, a maximum acceptable biterror rate (BER) translates to a minimum signal-to-noise ratio (SNR) at the baseband output of the receiver (input of the demodulator). For a given receiver sen-sitivity, the output SNR sets an upper limit on the noise figure of the receiver. Thenoise figure (NF) is defined as the ratio of the total output noise power to theoutput noise power caused only by the source, as shown in (2.11), which cannot bedirectly applied to multiport systems, such as phased-arrays. Consider the n-pathphased-array system, shown in Fig. 2.9. Sin is the input signal power; Nin is theinput noise power; N1 and N2 are the 1st and 2nd stage added noise power,respectively; G1 and G2 are the available power gain of the 1st and 2nd stage,
Ts
t
(2 )
( )
d
S
(a) (b)
θ
θ
Δ
Fig. 2.8 a Simplifiedphased-array system model.b Time and phase relation
16 2 Basic Concepts
respectively; k is the antenna number; K is the number of antennas; Ø is the phasedifference between two adjacent channels to compensate the phase differenceintroduced by angle of incidence h. We assume here that the noise power Nin andN1 are equal for all channels.
Since the input signals are added coherently, taking into account the weightingfactor for each channel when combiners are implemented in analog domain [48],then
Sout ¼ KG1G2Sin ð2:32Þ
The antenna’s noise contribution is primarily determined by the temperature ofthe object(s) at which it is pointed. When antenna noise sources are uncorrelated,such as in indoor environment, and also the front-end noise sources are uncorre-lated, the output total noise power is given by
Nout ¼ Nin þ N1ð Þ � G1G2 þ N2G2 ð2:33Þ
Thus, compared to the output SNR of a single-path receiver, the output SNR ofthe array is improved by a factor between K and K2, depending on the noise andgain contribution of different stages. The array noise factor can be expressed as
F ¼ K Nin þ N1ð ÞG1G2 þ N2G2
KNinG1G2
¼ KSNRin
SNRoutð2:34Þ
G1
Sin
G1
G1
G1
N1
N1
N1
N1
N2
G2
Sin
Sin
Sin
Nin
Nin
Nin
Nin
Sout
Nout
1
2
k
K
Fig. 2.9 Simplified model for n channels phased-array
2.3 Phased-Array Basics 17
which shows that the SNR at the phased-array output can be even larger than theSNR at the input if K [ F. For a given NF, an n-array receiver improves thesensitivity by 10log(K) in decibels compared to a single-path receiver. Forinstance, an 8 element phased-array can improve the receiver sensitivity by 9 dB.
Phased-array can enhance the receiving signal power, as shown in Fig. 2.10.Assume each antenna of a phased-array receives P0 power form the main beamdirection. After phase shift and combining, assuming no loss in between, thecombined power in the main beam direction is P0 ? 20log(K).
An additional advantage of a phased-array is its ability to significantly attenuatethe incident interference power from other directions. In a single-chain receiver,the linearity performance reflects on the third order input intercept point (IIP3). Itis in many cases dominated by the interferer instead of the desired signal.A phased-array receiver has the advantage of enhancing the desired signal byadding the path signals in-phase, and reject the unwanted interferer (from anotherangle) by adding the path signals out-of-phase. This can be expressed as
sSUM ¼X
K
k¼1
A tð Þ � ej2pfCt � ej k�1ð Þu � e�j k�1ð Þc ð2:35Þ
Where sSUM is the signal at the output; A(t) is the amplitude of the incoming signaland fC is the carrier frequency; u is the input signal electric phase difference (can beeither desired or unwanted signal), and c is the electric phase compensation (fordesired signal) on each path and c = p*sinØ; k is the antenna number; K is thenumber of antennas. Furthermore, assuming antenna spacing d = k/2 (k is the signalwavelength), the space angle h(deg) can be transferred to a phase difference by
u ¼ 2pk� d � sin h ¼ p � sin h ð2:36Þ
0P
0 20logP K
At the main beam direction
0P
1
20P
0P
0P
k
K
Fig. 2.10 Simplified model of phased-array receiving system
18 2 Basic Concepts
Combining (2.35) and (2.36), and taking only the absolute amplitude of sSUM, thenormalized array gain, ASUM, can be expressed as (for normalized signal amplitude,A(t) = 1 V)
ASUM ¼X
K
k¼1
ejðk�1Þp sin h � e�jðk�1Þp sin /
�
�
�
�
�
�
�
�
�
�
ð2:37Þ
When K = 1, it is a single antenna receiver without any directivity. Hence, thearray gain is unity for all angles of incidence. When K = 1, multiple antennasproduce antenna patterns which are a function of K, desired viewing angle hd, andun-desired viewing angle hi. Assuming hd = 0�, adjusting Ø to the desired signalresults Ø = 0�. ASUM can be expressed in (2.38), and plotted in Fig. 2.11 withK = 1, 2, 4, 8 as examples.
ASUM;dB ¼ 20 logX
K
k¼1
ej k�1ð Þp sin h
�
�
�
�
�
�
�
�
�
�
ð2:38Þ
Here, we define a suppression factor L that describes the power rejection for hi
relatively to the power at hd
L ¼ f n; hi; hdð Þ ð2:39Þ
For example, assume K = 4 and hi = 35� as shown in Fig. 2.11, the suppres-sion from the peak (K = 4) is 12 dB - (-5 dB) = 17 dB, hence L = f(n = 4,hi=35�, hd=0�) = -17 dB (note that L in terms of dB is always a negative number,corresponding to a power loss or power gain smaller than one).
Fig. 2.11 Phased-arrayantenna gain patterns, whenK = 1,2,4,8
2.3 Phased-Array Basics 19
Chapter 3Single and Multipath Receiver: A SystemApproach
There are many ways to categorize receiver architectures. One of them is tocategorize them into single-path receiver and multi-path receivers. A multi-pathreceiver is composed of many single-path receivers, hence they have someproperties in common. Nevertheless, multi-path gives another dimension of designfreedom to the receiver structure: the spatial dimension. In other words, a multi-path receiver has more properties than a single-path receiver. In this chapter, wewill discuss single- and multi-path receivers from a system point of view.
We will start with single-path receiver analysis. As we know that a receiverchain can be separated into RF and ADC parts, at Sect. 3.1, ADC parameters aretranslated into the RF domain, so that we can have a fair comparison/trade-offbetween them on system level. After that, the design trade-offs are discussed inSect. 3.2. The discussions are based on noise and linearity. An optimizationmethod is introduced in Sect. 3.3 to optimize the system for different applicationsand purposes. The two categories of phased-array receivers: analog beam-formingand digital beam-forming are discussed in Sects. 3.4 and 3.5, respectively. Both ofthem are first made equivalent to a single-path receiver, and then analyzed by themethod in Sects. 3.1–3.3. Section 3.6 introduces receiver structure that takesoptimum advantage of both analog and digital beam-forming. Section 3.7 con-cludes this chapter.
3.1 Translating ADC Parameters to RF Domain
The rapid growth of wireless communication has resulted in a shift of RF appli-cations towards high frequencies. The increased bandwidth and dynamic rangerequires a systematic design strategy for RF receivers. RF system engineers aremainly focusing on the performance and power consumption of RF front-ends.
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_3,� Springer Science+Business Media New York 2013
21
The lack of a proper relation between RF blocks and ADC has led to the over-specifications of these blocks and a non-optimized system [49–58].
Figure 3.1 shows a simplified receiver chain including both RF front-end andADC, where the interferers cause the dominant distortion. RF front-ends are usuallycharacterized by noise figure (NF), power gain, third order input intercept point(IIP3) and power consumption [59]. The established theory enables the calculationof overall NF and IIP3 in cascaded RF blocks through the transformation of NF andIIP3 of each individual block. An extension of this theory enables the optimization ofthe overall power consumption through proper dimensioning of the individual RFblocks [60]. However, the main obstacles to a systematic design strategy for overalloptimization are the lack of:
• a proper translation of ADC parameters into RF domain;• a proper design flow reflecting the relation between RF and ADC blocks;• a set of variables, enabling the proper dimensioning of individual block
performance.
3.1.1 ADC Model
Figure 3.2 shows the simplified front-end and ADC model. The main task of theNyquist filter and the VGA consists in reducing the dynamic range of the ADC byproviding some filtering of the blocking signals and the adjacent channels inter-ference, and adjusting the signal level to the input range of the ADC.
The ADC component is modeled by two blocks: the non-linearity block and theADC noise block. It is assumed that the transferred output signal has a unity gain,and no offset errors, compared to the input analog signal.
3.1.2 ADC Noise
In ADC design, the parameters of interest are peak-to-peak full scale voltage (vFS),1
sampling frequency (fsample), and number of bits (n). When noise is the product of
ADC
Signal Adj. chan. 1
Alt. chan. 2
Band Select
RF Front-End
Fig. 3.1 Simplified receiver chain
1 Without loss of generality, we assume here that the output of the ADC is a voltage.
22 3 Single and Multipath Receiver: A System Approach
quantization, the signal to quantization noise ratio (SQNR) of an ideal ADC withfull scale sinusoid wave as input is given by SQNR = 6.02n ? 1.76 [61].Figure 3.3 shows the ADC quantization mechanism, where qS is the ADC quan-tization noise in fundamental interval (fsample/2).
In case of oversampling, the signal bandwidth (BW) is less than fsample/2. Hencethe ADC quantization noise in the signal bandwidth BW can be further reduced asa result of the process gain, which is indicated by fsample/(2*BW). Figure 3.4 showsthe voltage relations.
However, in practice, the ADC is not a stand-alone component; it is used incombination with the RF blocks in a receiver chain. From this perspective,assuming the input impedance of the ADC is 50 X, the parameters of interest canbe described as full scale input signal power2 (PFS), sampling frequency (fsample),ADC signal to noise ratio (SNRADC), channel bandwidth (BW), and ADC noisefactor (FADC). Figure 3.5 shows the conceptual translation from ADC noise designparameters in volt to RF design parameters in mW. Note that this translationassumes a 50 X matching at the input of the ADC, and the ADC noise factor(FADC) contains the contribution of quantization as well as thermal noise.
It is more suitable to use effective number of bits (ENOBnoise) instead of n, because itincludes both ADC quantization noise (Q noise) and thermal noise (T noise), assumingthat quantization noise behaves the same as thermal noise and has no correlation with the
LNA
Front End
VGA
Band Select
Non-linearity
ADC Model
Nyquist filter Quantization noise
Thermal noise
(n, fsample)
Mixer
Fig. 3.2 Simplified front-end and ADC model
peakv
peakv−
sq
FSv
Fig. 3.3 ADC quantizationmechanism
2 Assume a pure sine wave input.
3.1 Translating ADC Parameters to RF Domain 23
signal. In this case, one can write: SNRADC = 6.02ENOBnoise ? 1.76. After properderivation, the noise figure of the ADC, NFADC, can be expressed as
NFADC ¼ PFS;dBm � 10 log kT � BWð Þ þ 10 logfsample
2 � BW
� �
þ SNRADC;dB|fflfflfflfflfflffl{zfflfflfflfflfflffl}
6:02ENOBnoiseþ1:76
2
6
4
3
7
5
ð3:1Þ
With the help of (3.1), we can directly include ADC noise into cascaded noisecalculations of receiver systems.
3.1.3 ADC Non-linearity
Non-linearity is the other major concern in ADC design. In a typical design, thereare two parameters of interest. Firstly, the effective full scale range voltage (vFS,eff),and secondly, the harmonic distortion. For simplicity, we limit our analysis tomemory-less, time-variant systems and assume then
yðtÞ � a1xðtÞ þ a2x2ðtÞ þ a3x3ðtÞ ð3:2Þ
Figure 3.6 visualizes the non-linearity model of the ADC.where vinput is the magnitude of the fundamental of the analog input spectrum, notethat vinput \ vFS,eff.. vh1 is the magnitude of the fundamental at the output. vh2 and
SQNR
ADC Q noise in fundamental intervel FSvADC Q noise
density (per Hz)ADC Q noise in signal BW
Volt
2
samplef
BWBW ⋅
Fig. 3.4 Voltage relations in ADC design
Assume 50matching resistance
SQNRADC Q noise in
fundamental interval FSvADC Q noisedensity(per Hz)
ADC Q noise in signal BW
ADC Noise power in fundamental interval
(T+Q)
ADCSNRmW
Volt
FSPADCN
ADC noise power in Channel BW (T+Q)
ADCF
kT ⋅ BWNoise floor
2samplef
BWBW
2
samplef
BW⋅
⋅
Fig. 3.5 Conceptual translation of ADC noise parameters to RF domain
24 3 Single and Multipath Receiver: A System Approach
vh3 is the magnitude of the second and third harmonic at the output, respectively.In (3.2), if vinput = A, and x(t) = Acosxt, then
yðtÞ ¼a1A cos xt þ a2A2 cos2 xt þ a3A3 cos3 xt
¼ a2A2
2þ a1Aþ 3a3A3
4
� �
|fflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflffl}
vh1
cos xt þ a2A2
2|ffl{zffl}
vh2
cos 2xt þ a3A3
4|ffl{zffl}
vh3
cos 3xt ð3:3Þ
However, from RF system perspective, interferer signals often cause the domi-nant distortion (see Fig. 3.1). Thus the third order input intercept point IIP3ADC canbe used to describe the ADC global nonlinear property. IIP3ADC is a function of thefundamental output interference signal (Iout), output third order intermodulationdistortion product (DIM3,adc). Considering the unity transfer of the ADC(GADC = 1), one can express IIP3ADC as
IIP3ADC;dBm ¼ OIP3ADC;dBm
¼IM3�1
ADC;dB
2þ Iout;dBm ¼
32
Iout;dBm �12
DIM3;ADC;dBm ð3:4Þ
where OIP3ADC is the ADC output 3rd order intercept point, and (IM3ADC)-1 is theratio between Iout and DIM3,ADC. Figure 3.7 shows intermodulation in an ADCsystem. The input two tone signals allocate in frequency f1 and f2, respectively.They pass through an ADC system with nonlinear property described in Fig. 3.6,and the output third order intermodulation product falls in frequency 2f1-f2 and2f2-f1, respectively.
Similar to (3.3), vinput = A. Assuming input x(t) = (A/2)*(cosx1t ? cosx2t),then
yðtÞ ¼ a1 þ94a3
A
2
� �2" #
A
|fflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
vfund
cos x1t þ cos x2tð Þ
þ 34a3
A
2
� �3
|fflfflfflfflfflffl{zfflfflfflfflfflffl}
vIM3;ADC
cos 2x2 � x1ð Þt þ cos 2x1 � x2ð Þt½ � þ � � � ð3:5Þ
f 3ff
inputv 1hv
3hv
ADC
2hv
2f
Fig. 3.6 Non-linearitymodel of ADC
3.1 Translating ADC Parameters to RF Domain 25
From (3.3) and (3.5), we can find the relation between vh3 and vIM3,ADC as
vIM3;ADC ¼34a3
A
2
� �3
¼ 38
vh3 ð3:6Þ
Hence, (3.4) can be re-written in terms of 3rd order harmonic power as
IIP3ADC;dBm ¼32
Iout;dBm �12
H3ADC;dBm � 10 log38
ð3:7Þ
where H3ADC is the power of the ADC 3rd order harmonics. To guarantee theintegrity of the signal, two auxiliary parameters, DP1 and DP2 are usuallyintroduced.
• DP1 is the margin to the ADC full scale range power, for example DC offset andoverloading behavior, which depends on the ADC architecture. PFS/DP1 indi-cates the ADC effective input full scale power, which is the counterpart of vFS,eff.
• DP2 is the energy reduction from one tone input to two tone inputs (by eachtone), which is usually half of voltage (6 dB). Hence, PFS/(DP1*DP2) is theinput interferer power (by each tone).
Figure 3.8 shows the conceptual translation from ADC non-linearity designparameters in volt to RF design parameters in dBm. Note that this translationassumes a 50 X matching at the input of ADC.
In the following chapters, it is assumed that interference signals are the dom-inant causes for ADC distortion in the desired channel, which means that DIM3,ADC
is the dominant distortion component. Moreover, DIM3,ADC is replaced by DADC
which means ADC distortion power.
3.2 Mapping ADC Parameters to System Design
In many cases, the system performance is defined in terms of BER, which is afunction of signal to noise and distortion ratio (SNDR). SNDR can be separatedinto signal to noise ratio (SNR) and signal to distortion ratio (SDR), in order todistinguish the contribution of noise and distortion, and to enable the possibility ofa trade-off for an optimum performance. From this perspective, it is very importantto analyze the impact of ADC noise and distortion on the performance of thesystem SNR and SDR. Assuming the phases of the distortion components of
2f1-f2 f1f2 f2f1 2f2-f1
2inputv
3,IM ADCv
fundv
ADC
Fig. 3.7 Intermodulation inan ADC system
26 3 Single and Multipath Receiver: A System Approach
different stages uncorrelated [62], the equivalent total noise and distortion powerof the system can be formulated as (first order approach)
Ntot;dBm ¼ NADC;dBm þ DNFE;dB ð3:8Þ
Dtot;dBm ¼ DADC;dBm þ DDFE;dB ð3:9Þ
where Ntot,dBm is the equivalent total noise power of the system referred to ADCinput; Dtot,dBm is the equivalent total distortion power of the system referred to theADC output; DNFE,dB and DDFE,dB are the noise and distortion contribution bythe RF front-end referred to ADC input and output, respectively. Defining SADC
and Sout as the signal power at the ADC input and output, one can formulate SNRand SDR as
SNRdB ¼ SADC;dBm � Ntot;dBm ¼ SADC;dBm � NADC;dBm þ DNFE;dB
� �
ð3:10Þ
SDRdB ¼ Sout;dBm � Dtot;dBm ¼ Sout;dBm � DADC;dBm þ DDFE;dB
� �
ð3:11Þ
Combining Eq. (3.10) and (3.11) with the results achieved in previous sections,enables the embedding of the ADC into the overall system characterization asdepicted in Fig. 3.9.3
• The X1- axis is the ADC block noise parameters. It has been explained inFig. 3.5.
• The Y1- axis is the ADC block non-linearity parameters. It has been explainedin Fig. 3.8.
• The X- axis represents the signal and noise relation at the input of ADC on asystem level. NADC is the noise contribution of the ADC; DNFE is the noisecontribution by the RF front-end referred to the ADC input; Ntot is the
Assume 50matching resistance
,FS effv
mW
Volt
ADCOIP3
( )ADCD
3ADCH outI3,IM ADCD
( 3 )ADCIIPFSP
( )inI
2P
13ADCIM
3hv
FSv
1P
= = =
Δ Δ
−
Ω
Fig. 3.8 Conceptual translated ADC non-linearity parameters to RF domain
3 In this figure, to keep the 3rd order intermodulation product a straight line, we need to use dBmcoordinate scale.
3.2 Mapping ADC Parameters to System Design 27
equivalent total noise power of the system referred to ADC input; SNR is thesignal to noise ratio; SADC is the input signal power; IADC is the remaining inputinterferer power after the filter and the VGA.
• The Y- axis represents the signal and distortion relation at the output of ADC ona system level. Iout is the output interferer level; Sout is the output signal power;SDR is the signal to distortion ratio; Dtot is the equivalent total distortion powerof the system referred to the ADC output; DDFE is the distortion contribution bythe RF front-end referred to the ADC output;
Assuming the ADC has a unity transfer as indicated by line A, we haveSADC = Sout; IADC = Iout; IIP3ADC = OIP3ADC. Line B shows the power of thethird order intermodulation product, which grows at three times the rate at whichthe main components increases, and we see that DADC is generated from IADC.From Fig. 3.9, we can rewrite SNR and SDR for the total system as
SNRdB ¼ SADC;dBm � 10 log kT � BWð Þ þ NFADC þ DNFE;dB
� �
ð3:12Þ
dBSNR
,FS dBmP
,3
ADC dBmIIP
10log2
samplef
BW
⎛ ⎞⎜ ⎟⋅⎝ ⎠ ,ADC dBSNR
ADC noise in fundamental
interval (T+Q)
ADCNF
( )10log kT BW⋅
,3ADC dBmOIP
1,3ADC dBIM −
dBSDR
,3ADC dBmH
, 1,FS dBm dBP P− Δ
X
YY1
3, ,( )IM ADC dBmD=
2,dBPΔ
,FE dBNΔ
,FE dBDΔ
Equiv. tot noise
Equiv. tot distortion
A(1:1)
B(1:3)
,ADC dBmI,ADC dBmS,ADC dBmN ,tot dBmN
,out dBmI
,tot dBmD
,ADC dBmD
,out dBmS
X1
dBm
dBm
dBmdBm
Fig. 3.9 ADC to system power (dBm) mapping for noise and distortion
28 3 Single and Multipath Receiver: A System Approach
SDRdB ¼ Sout;dBm � 3 PFS;dBm � DP1;dB � DP2;dB
� �
� 2IIP3ADC;dBm þ DDFE;dB
� �
ð3:13Þ
Equations. (3.12) and (3.13) link system parameters (SNR, SDR) with ADCparameters (NFADC, IIP3ADC).
3.3 Receiver System Optimization Method
The predefined specifications of wireless standards are the starting point for thedesign strategy. Standards usually include: bandwidth of the signal (BW), signal tonoise ratio (SNR) (derived from BER and modulation scheme), desired input signalpower (Sin) and input interferer power (Iin) for intermodulation characterization.This allows us to determine the receiver total noise figure and total input interceptpoint, as
NFtot ¼ Sin;dBm � SNRdB � 10 logðkT � BWÞ ð3:14Þ
IIP3tot;dBm ¼Iin;dBm � Sin;dBm þ SNRdB
2þ Iin;dBm ð3:15Þ
Furthermore, the type of ADC dictates PFS, DP1 and DP2, which in turn (PFS-
DP1-DP2) fixes the interferer power level at the input of the ADC (IADC).
3.3.1 Receiver Signal Flow Diagram
Optimizing the overall performance of the receiver chain demands a design flow,containing fixed parameters and variables. Figure 3.10 represents such a flowdiagram for receiver signal, noise and distortion.
This flow consists of three fronts:
• Antenna front, which is at the input of the receiver. IIP3FE, IIP3tot, and Iin arenon-linearity related parameters, where IIP3FE and IIP3tot are 3rd order inputintercept point of front-end and total receiver, respectively; Imax is the adjacentchannel interference power, Iin is the in-band interference power (by each tone).Sin is the minimum input signal power. Ntot,in and NFE are noise relatedparameters, where Ntot,in is the equivalent total receiver noise referring to theantenna; NFE is the equivalent front-end noise referring to the antenna. FFE andFtot are front-end and total receiver noise factor, respectively.
• After the LNA, the adjacent channel interference Imax is processed by the filterand VGA. As a result, Imax is amplified to the same power level as Iin at the inputof ADC. To simplify the later analysis, we only assume the presence of Iin.
3.2 Mapping ADC Parameters to System Design 29
• ADC input front, which is at the input of the ADC. It is the same as X- axe inFig. 3.9.
• ADC output front, which is at the output of the ADC. It is the same as Y- axe inFig. 3.9. Note that DP1 is the margin to the ADC full scale range power, andDP2 is the energy reduction from one tone input to two tone inputs (by eachtone), which is usually 6 dB (1/2 of voltage).
From antenna to ADC input, the available power gain is represented by GFE.From ADC input to ADC output, it is assumed that the ADC has a unity transfer.From Fig. 3.10, DNFE can be expressed as
DNFE ¼Ftot � GFE
FADCð3:16Þ
Utilizing the noise factor relation of a cascade (RF front-end plus ADC), andusing Eq. (3.16), the noise factor of front-end and ADC can be derived in (3.17)and (3.18), respectively
FFE ¼ Ftot 1� 1DNFE
� �
þ 1GFE
ð3:17Þ
FADC ¼Ftot � GFE
DNFEð3:18Þ
ANTENNA
ADCI outI
ADCN
totN
ADCS
FSP
totD
ADCD
ADCF
inI
inS
,tot inNEquiv. tot noise,
referred to antenna
FENtotF
FEF
ADC Input ADC Output
FEG
1 2P Δ PΔ +
3ADCIIP
FEIIP3
totIIP3
FENΔFEDΔ
3ADCOIP
(related to IIP3ADC)
FED
outS
kT BW⋅
LNA MIX+VGA/FILT
maxI
Fig. 3.10 Receiver signal, noise and distortion power flow diagram
30 3 Single and Multipath Receiver: A System Approach
As expected, we can see that FFE has a direct4 relation with DNFE, and FADC hasan inverse5 relation with DNFE. Keeping Ftot, GFE constant, adjusting DNFE canresult in the trade-off between front-end and ADC noise. Similarly, from Fig. 3.10,DDFE can be expressed as
DDFE ¼IIP3ADC
IIP3tot � GFE
� �2
ð3:19Þ
Through the cascade relations of IIP3 and Eq. (3.19), the 3rd order inputintercept point of front-end and ADC can be derived in (3.20) and (3.21),respectively
IIP3FE ¼IIP3tot
1� 1ffiffiffiffiffiffiffiffi
DDFEp
ð3:20Þ
IIP3ADC ¼ IIP3tot � GFE �ffiffiffiffiffiffiffiffiffiffiffiffi
DDFE
p
ð3:21Þ
It shows that IIP3FE has an inverse relation with DDFE, and IIP3ADC has a directrelation with DDFE. Keeping IIP3tot, GFE constant, adjusting DDFE can result inthe trade-off between front-end and ADC linearity. Instead of tuning fourparameters (FFE, IIP3FE, FADC, IIP3ADC) to achieve system optimization, we cannow reduce to two tuning parameters (DNFE, DDFE), and it simplifies the systemdesign.
3.3.2 Optimization Method
Two variables, DNFE and DDFE, can be used to trade-off between RF front-endsand ADC to achieve the system requirements. These variables enable:
• the trade-off between the RF front-end and ADC performance.• the adaption of RF front-end and ADC performance for different system
specifications.
If the functions of these variables versus power consumption of their describedblocks are given, they further more enable:
• the trade-off between RF front-end and ADC performance for minimum systempower consumption.
• the comparison of individual block with different designs or different technol-ogies, to find minimum system power consumption.
4 With direct relation, we mean when DNFE increases, FFE also increases.5 With inverse relation, we mean when DNFE increases, FADC decreases.
3.3 Receiver System Optimization Method 31
The impact of the choice between different scenarios on the system powerconsumption can be investigated through the following relation [63]:
Psys ¼ PC;FE �IIP3FE
NFEþ PC;ADC �
IIP3ADC
NADCð3:22Þ
where PC,FE and PC,ADC by definition denote the power coefficient of the front-endand ADC, respectively. Figure. 3.11 shows the system design flow chart of theabove presented method.
3.4 Analog Beam-Forming
Depending on the location where the required phase shifters are placed, the beam-forming of a phased-array can be classified as RF, LO, IF or digital beam-forming.In this section, we take the IF beam-forming architecture as an example.Figure 3.12a shows a phased-array receiver in which signal and noise power levelat the antenna inputs are Sin and NFL (‘FL’ stands for ‘floor’), respectively. Thefront-end block includes LNA and mixer. To simplify the analysis, we assume thefilter and VGA are ideal and they amplify the adjacent channel interference to thesame power level as the in-band interference at the input of the ADC.
The front-end (FE) equivalent noise power (NFE) is the noise power referred tothe input. The front-end gain (GFE) enlarges the signal as well as the noise. Theanalog to digital converter (ADC) converts the analog signal into the digitaldomain, but also adds quantization noise (NADC). Assuming a unity gain ADC anda lossless and noise-free phase shifter and combination of signal and noise fromeach path, at point A, the correlated signals from all antenna inputs are added in
Fig. 3.11 System designflow chart
32 3 Single and Multipath Receiver: A System Approach
voltage, nevertheless, the uncorrelated noise from each path are added in power,6
taking into account the weighting factor for each channel when combiners areimplemented in analog domain, yielding
SA ¼ Sin � ðK � GFEÞ ð3:23Þ
NA ¼ ðNFL þ NFEÞ � GFE ¼ ð1K� NFL þ
1K� NFEÞ � ðK � GFEÞ ð3:24Þ
From (3.23) and (3.24), we are able to project phased-array receiver inFig. 3.12a into an equivalent single-path structure in Fig. 3.12b. The equivalentvalues for NFL, NFE and GFE are (1/K)�NFL, (1/K)�NFE and K�GFE, respectively. Allthe blocks after point A are maintained. Note that K�GFE consists by two parts,
F-E
Sin
FENFEG
F-E
F-E
F-E
FLNSin
Sin
Sin
ADC
ADCN
3Ø
2Ø
Ø
0
F-E
Sin
1FEN
K
FEK G1
FLNK
A
ADC
ADCN
FLN
FLN
FLN
FEG
FEG
FEG
1ADCG
AFEN
FEN
FEN
1ADCG
1
2
k
K
=
=⋅⋅⋅
(a)
(b)
Fig. 3.12 a Analog phased-array receiver on block level. b Equivalent single-path structure fora regards noise and gain
6 Assuming the distance between adjacent antenna elements is equal to k/2, so the antennas aredecoupled with each other. Hence the thermal noise can be considered as un-correlated
3.4 Analog Beam-Forming 33
antenna array gain K, and front end gain GFE. From Fig. 3.12b, we can derive theinput referred total noise power as
Ntot;in ¼1K� NFL þ
1K� NFE þ
1K � GFE
� NADC ð3:25Þ
Hence, the total noise factor (Ftot) of the phased-array receiver is
Ftot ¼Ntot;in
NFL¼ 1
K� 1þ NFE
NFL
� �
þ 1K � GFE
� NADC
NFLð3:26Þ
The equivalent Friis noise equation for the phased-array receiver is
Ftot ¼1K� FFE þ
1K� FADC � 1
GFEð3:27Þ
where FFE and FADC represent noise factor of the front-end and ADC, respectively.It is obvious that thanks to the antenna array gain, both front-end and ADC inputreferred noises are reduced.
A design flow for a single-path receiver which indicates two variables that canbe used for the trade-off between RF and ADC blocks was introduced in Fig. 3.10.Similarly, Fig. 3.12b is the equivalent single-path structure for an analog phased-array receiver, so applying the same design flow for Fig. 3.12b, we can generatethe analog phased-array noise power (mW) flow diagram in Fig. 3.13. The dif-ference is that NFE, FFE, and GFE are replaced by (1/K)* NFE, (1/K)* FFE, and K*GFE, respectively. At the antenna front, number K indicates the system hasK antennas. Before the ADC input front, the dashed line ‘Analog Combine’ meansthat the mutipath input signals are combined at this place, and form only one pathfurther on. Similar to (3.16), DNFE in Fig. 3.13 can be expressed as
DNFE ¼Ftot � K � GFE
FADCð3:28Þ
Combining (3.27) and (3.28), the noise factor of front-end and ADC can bederived in (3.29) and (3.30), respectively
FFE ¼ K � Ftot 1� 1DNFE
� �
þ 1GFE
ð3:29Þ
FADC ¼Ftot � K � GFE
DNFEð3:30Þ
FFE has a direct relation with DNFE, and FADC has an inverse relation withDNFE. Keeping Ftot, GFE, and K constant, adjusting DNFE can result in the trade-offbetween front-end and ADC noise.
Similar to Fig. 3.13, we can generate the phased-array distortion power (mW)flow diagram in Fig. 3.14. Compared with Fig. 3.10, GFE is replaced by K*GFE*L,where L is the power rejection factor in (2.39). After analog combination, the
34 3 Single and Multipath Receiver: A System Approach
distortion power from K channels is added together. Taking into account theweighting factor during analog combination, the combined distortion power isdenoted by DFE. Assuming interferers power Iin dominate the receiver non-line-arity performance, the equivalent Friis linearity equation for a phased-array is
1IIP3tot
¼ 1IIP3FE
þ K � GFE � LIIP3ADC
ð3:31Þ
DDFE in Fig. 3.14 can be expressed as
MULTI ANTENNA
totF
1FEF
K⋅ ADCF
1FEN
K⋅
FEK G⋅
totN
FENΔ,tot in
N
ADC INPUT
kT BW⋅Analog
Combination
K
ADCN
Fig. 3.13 Analog phased-array noise power flowdiagram
MULTI ANTENNA
ADCD
FEK G L
FED
ADC OUTPUT
kT BW
ADC INPUT
totD
FED
3 ADCIIP3 FEIIP
3 totIIP
AnalogCombination
K
ADCIoutI
inI
⋅ ⋅
⋅
Δ
Fig. 3.14 Analog phased-array distortion power flowdiagram
3.4 Analog Beam-Forming 35
DDFE ¼IIP3ADC
IIP3tot � K � GFE � L
� �2
ð3:32Þ
Combining (3.31) and (3.32), the IIP3FE and IIP3ADC can be derived in (3.33)and (3.34), respectively
IIP3FE ¼IIP3tot
1� 1ffiffiffiffiffiffiffiffi
DDFEp
ð3:33Þ
IIP3ADC ¼ IIP3tot � K � GFE � L �ffiffiffiffiffiffiffiffiffiffiffiffi
DDFE
p
ð3:34Þ
It shows that IIP3FE has an inverse relation with DDFE, and IIP3ADC has a directrelation with DDFE. Keeping IIP3tot, GFE, and L constant, adjusting DDFE canresult in the trade-off between front-end and ADC linearity. Figs. 3.13 and 3.14can be combined in Fig. 3.15, which shows the signal, noise and distortion power(mW) flow of an analog phased-array receiver.
Note that in Fig. 3.15, after the dashed line ‘Analog Combination’, the flow isthe same as the single-path flow shown in Fig. 3.10. In brief, there are two types ofpower flow in Fig. 3.15,
ADC Input ADC Output
FEK G L⋅ ⋅
totF
kT BW⋅
,tot inN
totN
FENΔ
ADCF ADCD
FEDΔ
totD
3 ADCIIP3FEIIP
3totIIP
FEK G⋅
MULTI ANTENNA
inS
ADCN
AnalogCombination
K
FED
ADCIoutI
inI
ADCS outS
1FEF
K⋅
1FEN
K⋅
Fig. 3.15 Analog phased-array signal, noise and distortion power flow diagram
36 3 Single and Multipath Receiver: A System Approach
• The flow of the interference signal from Iin to IADC, suppressed due to the powerrejection factor L.
• The flow of the desired signal from Sin increased to SADC, due to signal additionin voltage domain.
3.5 Digital Beam-Forming
With digital beam-forming (DBF), a signal from each channel is carried fromantenna to digital domain, where the beam-forming algorithms are implemented.The flexibility of beam-forming algorithms is its main advantage. As shown inFig. 3.16a, a DBF combines the signal in the digital domain, after the ADC. Thefront-end block includes LNA and mixer. To simplify the analysis, we assumethe filter and VGA are ideal and they amplify the adjacent channel interference tothe same power level as the in-band interference at the input of the ADC.
(a)
(b)
F-E
F-E
B
F-E ADC
F-E
Sin
FLNSin
Sin
Sin
ADCN
ADCN
ADCN
ADCN
3Ø
ADC
ADC
ADC
2Ø
Ø
0
F-E
SinB
ADCNK
ADC
FEK G⋅1
FLNK
⋅
1
1
1
1
FLN
FLN
FLN
Digital domain
Digital domain
FEN
FEN
FEN
FEN
FEG
FEG
FEG
FEG
1FEN
K⋅
1
2
k
K
Fig. 3.16 a Digital phased-array receiver on block level. b Equivalent single-path structure fora regards noise and gain
3.4 Analog Beam-Forming 37
At point B, the signal is added in voltage and noise is added in power.7 The totaloutput signal power, SB, and noise power, NB, can be formulated as
SB ¼ Sin � K2 � GFE ¼ Sin � ðK � GFEÞ � K ð3:35Þ
NB ¼ NFL þ NFEð Þ � K � GFE þ NADC � K
¼ 1K� NFL þ
1K� NFE
� �
� K2 � GFE
� �
þ NADC � K ð3:36Þ
From (3.35) and (3.36), we are able to project the phased-array receiver inFig. 3.16a onto an equivalent single-path structure in Fig. 3.16b. The equivalentvalues for NFL, NFE and GFE are (1/K)�NFL, (1/K)�NFE and K�GFE, respectively.From Fig. 3.16b, we can derive the input referred total noise power as
Ntot;in ¼1K� NFL þ
1K� NFE þ
1K � GFE
� NADC ð3:37Þ
Hence, the total noise factor (Ftot) of the phased-array receiver is
Ftot ¼Ntot;in
NFL¼ 1
K� 1þ NFE
NFL
� �
þ 1K � GFE
� NADC
NFLð3:38Þ
The equivalent Friis noise equation for phased-array is
Ftot ¼1K� FFE þ
FADC � 1GFE
� �
ð3:39Þ
where FFE and FADC represent noise factor of the front-end and ADC, respectively.It is obviously that thanks to the antenna array gain, both front-end and ADC inputreferred noises are reduced.
Based on the equivalent single-path structure for digital phased-array shown inFig. 3.16b, we can generate the phased-array noise power (mW) flow diagram inFig. 3.17. Comparing with Fig. 3.10, the difference is that NFE, FFE, and GFE arereplaced by (1/K)* NFE, (1/K)* FFE, and K2* GFE, respectively. At the antenna,ADC input, and ADC output front, number K indicates the system has K antennas.Noise of ADC at ADC input front is the sum of ADC noise from K channels,denote by K*NADC and K*FADC. After the ADC output front, the dashed line‘Digital Combination’ means that the multipath input signals are combined at thisplace, and forms only one path further on. Similar to (3.16), DNFE can beexpressed as
7 Assuming the distance between adjacent antenna elements is equal to k/2, so the antenna isdecoupled with each other. Hence the thermal noise can be considered as un-correlated. Alsoassuming thermal noise is equal to or larger than quantization noise, as it then de-correlates thequantization noise of various ADCs
38 3 Single and Multipath Receiver: A System Approach
DNFE ¼Ftot � K � GFE
FADCð3:40Þ
Combining (3.39) and (3.40), the noise figure of front-end and ADC can bederived in (3.41) and (3.42), respectively
FFE ¼ K � Ftot 1� 1DNFE
� �
þ 1GFE
ð3:41Þ
FADC ¼Ftot � K � GFE
DNFEð3:42Þ
One can see that NFFE has a direct relation with DNFE, and NFADC has a reverserelation with DNFE. Keeping NFtot, GFE, and K constant, adjusting DNFE can resultin the trade-off between front-end and ADC noise.
Similar to Fig. 3.17, we can generate the phased-array distortion power (mW)flow diagram in Fig. 3.18. From ADC input to Digital Combine front, interferencesignal power is suppressed by a factor of K2*L, where L is the power rejectionfactor in (2.39). Both front-end and ADC distortion power are added together fromK channels, denoted by K*DFE and K*DADC, respectively. Assuming interfererspower Iin dominant the receiver linearity performance, equivalent Friis linearityequation for phased-array is
1IIP3tot
¼ffiffiffiffi
Kp
IIP3FEþ
ffiffiffiffi
Kp� GFE
IIP3ADCð3:43Þ
DDFE in Fig. 3.18 can be expressed as
DDFE ¼IIP3ADC
IIP3tot � GFE
� �2
� 1K
ð3:44Þ
2FEK G
MULTI ANTENNA
ADC OUTPUT
ADC INPUT
1FEF
K⋅
1FEN
K⋅
kT BW⋅
,tot inN
totF
totN
FENΔ
ADCK F⋅
ADCK N⋅
DigitalCombination
K K K
Fig. 3.17 Digital phased-array noise power flowdiagram
3.5 Digital Beam-Forming 39
Combining (3.43) and (3.44), the IIP3FE and IIP3ADC can be derived in (3.45)and (3.46), respectively
IIP3FE ¼IIP3tot �
ffiffiffiffi
Kp
1� 1ffiffiffiffiffi
DDp
ð3:45Þ
IIP3ADC ¼ IIP3tot � GFE �ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
K � DDFE
p
ð3:46Þ
It shows that IIP3FE has a reverse relation with DDFE, and IIP3ADC has a directrelation with DDFE. Keeping IIP3tot, and GFE constant, adjusting DDFE can resultin the trade-off between front-end and ADC linearity. Figures 3.17 and 3.18 can becombined in Fig. 3.19, which shows the signal, noise and distortion power (mW)flow of a digital phased-array receiver. Note that beam-forming is placed in digitaldomain, hence the suppression factor L is in the right part of the plane.
There are two types of power flow in Fig. 3.19
• The flow of interference signal from Iin increase to IADC with single-path front-end gain GFE. Then from IADC suppressed to Iout due to power rejection factor L.
• The flow of desired signal from Sin increased to Sout, due to signal added involtage.
3.6 General Case of Beam-Forming
As explained in the previous sections, beam-forming can be implemented in theanalog domain or digital domain. Analog beam-forming (ABF) combines thesignal from the antennas in the analog domain and relaxes the dynamic range ofthe following receiver blocks. However, the phase information from each antennais also lost after the combination. On the other hand, digital beam-forming (DBF)conveys signal amplitude and phase into the digital domain, which provides more
MULTI ANTENNA
ADCK D⋅
FEDΔ
ADC OUTPUT
kT BW⋅
ADC INPUT
totD
3ADCIIP3FEIIP
3totIIP
DigitalCombination
FEG
K K K
FEK D⋅
2K L⋅ADCI
outI
inI
Fig. 3.18 Digital phased-array distortion power flowdiagram
40 3 Single and Multipath Receiver: A System Approach
flexibility and control of the signal in terms of applying various algorithms.Nevertheless, the hardware replication, especially the power hungry ADCs, willincrease the overall power consumption, area and cost.
For a more general case of beam-forming, instead of either analog or digitalbeam-forming, one can think of a way in between, which means beam-forming ispartly done in analog domain, and partly done in digital domain. In Sect. 3.4,Fig. 3.15 shows a signal, noise and distortion power flow diagram of an analogphased-array system, where the signals combine occurs before ADC. In Sect. 3.5,Fig. 3.19 shows a power flow diagram of a digital phased-array system, where thesignals combine occurs after ADC. Using properties from both Figs. 3.15 and3.19, one can design a power flow diagram for general case beam-forming, whichis shown in Fig. 3.20.
One can notice that except for parameters that has been explained previously,there are two extra parameters: b1 and b2. They indicate the flexibility of the beam-forming system.
As shown in Table 3.1, when b1 = K and b2 = 1, the system is analog beam-forming system, which is the same as Fig. 3.15; When b1 = K2 and b2 = K, thesystem is digital beam-forming system, which is the same as Fig. 3.19, WhenK \ b1 \ K2 and 1 \ b2 \ K, the system is partly analog, and partly digital beam-forming. On system design level, b1 and b2 can be used as another designdimension to perform system optimization with various applications.
ADCInput
ADC Output
FEG
totF1
FEFK
⋅
1FEN
K⋅
kT BW⋅
,tot inN
totN
FENΔ
3ADCIIP3FEIIP
3totIIP
2FEK G⋅
MULTI ANTENNA
ADCK N⋅ FEDΔ
totD
2K L⋅
DigitalCombination
K K K
ADCK D⋅FEK D⋅
ADCI
outI
inI
inS
ADCSoutS
ADCK F⋅
Fig. 3.19 Digital phased-array signal, noise and distortion power flow diagram
3.6 General Case of Beam-Forming 41
3.7 Conclusion
This chapter has presented system approaches to both single- and multi-pathreceivers. With single-path receiver, a design flow for trade-off between RF front-end and ADC block performance by translating ADC parameters into RF domainis introduced. This approach indicates two variables, DNFE and DDFE, forachieving optimum dynamic range in a receiver chain. Associating these variablesto the power consumption enables the trade-off between RF and ADC block forminimum overall power consumption. After that, two types of multi-path receiver,namely, analog beam-forming and digital beam-forming are analyzed as a singlechain receiver with their equivalent model. It started with analyzing the differencebetween phased-array and single-chain receivers from noise and linearity per-spectives and the result indicates that for both cases, the total noise figures arereduced due to non-correlated noise adding, and the total IIP3 are increased due tointerference cancellation. At last, this chapter provided a general case of beam-
ADCInput
1 FEG Lβ ⋅ ⋅
totF1
FEFK
⋅
1FEN
K⋅
kT BW⋅
,tot inN
totN
FENΔ
3ADCIIP3FEIIP
3totIIP
MULTI ANTENNA
2 ADCNβ ⋅
2 ADCDβ ⋅
FEDΔ
totD
AnalogCombination
K
DigitalCombination
ADC Output
K
outI
inI
inS
outS
2 ADCFβ ⋅2 FEDβ ⋅
1 FEGβ ⋅
Fig. 3.20 Signal, noise and distortion power flow diagram of a general beam-forming system
Table 3.1 Parameter difference with analog and digital beam-forming
Analog beam-forming Digital beam-forming
b1 K K2
b2 1 K
42 3 Single and Multipath Receiver: A System Approach
forming analysis, and two parameters b1 and b2 are introduced to indicate theflexibility of the beam-forming. When K \b1 \ K2 and 1 \b2 \ K, the system ispartly analog, and partly digital beam-forming. On system design level, b1 and b2
can be used as another design dimension to perform system optimization withvarious applications.
3.7 Conclusion 43
Chapter 4Two-Step Beam-Forming: MultiplexingArchitecture
A multiplexing phased-array architecture combines K antenna paths into one pathby dividing the signal into different time slots. The signals from the antennas arereceived in rapid succession, one after the other, each using its own time slot. Aftermixing, filtering, and analog to digital conversion, the multiplexed signal isde-multiplexed in the digital domain, and digital phase shifters are applied tocompensate the phase differences for each channel. In the end, signals are com-bined again in the digital domain, and the desired signal is picked up by means ofdigital filtering. This chapter presents the concept of multiplexing phased-arrayarchitecture and its major properties. The detailed analysis of this architecture isdiscussed in Chap. 5 and 6.
4.1 Multiplexing Architecture Introduction
Figure 4.1 shows a flexible phased-array receiver architecture matches with Fig.1.2. The analog combination block is implemented by an K:1 multiplexer, whichchops up the channel into sequential time slices. As such, the phase informationfrom each channel is carried to the digital domain. The analog signal processingblock is implemented by a mixer and a band-pass filter. In digital domain, thecombined signal is separated again by a de-multiplexer which is synchronized withthe multiplexer. After that, the phase difference of each channel is compensated bya digital phase shifter, where the beam-forming algorithms can be applied.The major properties of the multiplexing system can be summarized as thefollowing:
• No analog phase shifter is implemented at the RF front-end. The phase shifter isonly implemented in digital domain.
• The multiplexer can be seen as a beam-forming component in itself, because theclock generator generates switching pulses with phase delays. But, assuming the
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_4,� Springer Science+Business Media New York 2013
45
analog filter is not present, then the de-multiplexer in digital domain compen-sates the previous generated phase delays, and the original input phaseinformation are preserved for the digital phase-shifter.
• The analog band pass filter is used to relax the following ADC design in twoaspects. Firstly, ADC bandwidth is relaxed. The band pass filter bandwidth willdetermine the ADC bandwidth. And secondly, it creates a coarse spatial filter(because of the combination usage with the multiplexer) which filters out thespatial interferences, to relax the ADC dynamic range. The details will beexplained in Chap. 5.
• The digital phase shifter provides the flexibility to compensate the non-idealphase influences in the analog path, and formalize the final array patter in digitaldomain with high speed and accuracy.
Figure 4.2 shows the simplified model for multiplexing structure to explain thefrequency spectrum transformation from point A to B, where h is the angle ofincidence, BWanalog is the analog filter bandwidth, and [ is the digital phasecompensation. Point A and B are located right after multiplexer and de-multi-plexer, respectively. At point A, the frequency spectrum for h = 0� has only onecomponent located in the fundamental tone (n = 0). The frequency spectrum forh = 0� has multiple components located throughout the spectrum. Depending onthe condition applied to parameters BWanalog and [, the spectrum at point B fordifferent angle of incidence behaves differently. The detailed explanation of thistransformation will be explained in Chap. 5.
The time division multiplexing phased-array receiver uses a clock controlledmultiplexer to combine K paths into one. The switch-driving waveform is shownin Fig. 4.3. At time slot one, channel one is connected, and all other channels aredisconnected. At time slot two, channel two is connected, and all other channelsare disconnected, etc. The time slot for each channel is designed to be equal.
In Fig. 4.3, s represents the duration for each time slot, and TS represents oneperiod in which all the channels have been connected once. We have
TS ¼ K � s ð4:1Þ
Multiplexer
LO
Clock generatorMULf
Sf
ADC
Digital domain
31
2
k
K
1
2
k
K
LNA
MixerAnalog-
filter
De-multiplexer
Phase-shifter
Digital-filter
Coarsespatialfiltering
Finalspatialfiltering
2
0
analogBW digitalBW
Fig. 4.1 Multiplexing system structure
46 4 Two-Step Beam-Forming: Multiplexing Architecture
Fig. 4.2 Simplified model for multiplexing structure to explain the frequency spectrum trans-formation from point A to B
1
t
τ ST
2
k
K
Multi.
t
t
t
t
Fig. 4.3 Switch drivingwaveform for multiplexingsystem
4.1 Multiplexing Architecture Introduction 47
fMUL ¼1s¼ K
TS¼ K � fS ð4:2Þ
To recover the signal from each path correctly in the digital domain, thesampling rate for each path (fS) must fulfill the Nyquist sampling theory [64]
fS [ 2 � BW ð4:3Þ
where BW is the single side bandwidth of the incoming modulated signal. As aresult, the multiplexer sampling rate fMUL can be expressed as
fMUL ¼ K � fS [ 2K � BW ð4:4Þ
which means that the larger the signal bandwidth BW, or the larger the antennanumber K, the faster the sampling speed fMUL. On the other hand, for a dedicatedtechnology, the sampling speed fMUL has a upper limit, which also limits theincoming signal bandwidth when K is fixed, or limits the total antenna number ifthe incoming signal bandwidth BW is fixed.
4.2 Spatial to Frequency Mapping
The phased-array multiplexing architecture can achieve spatial domain to fre-quency domain mapping in the following way:
• In the spatial domain, the angular information h (in degrees) at the antenna frontis translated to a wave-front time delay Dt (in second) between adjacentchannels.
• In time domain, the time delay Dt can be modeled (assuming narrow band) as awaveform phase difference u (in rad) between adjacent channels.
• The multiplexer is acting like a kind of phase modulation. Through the K:1multiplexing, an input signal with phase difference u is modulated to the carrier.
• Using Fourier transform, the phase modulated signal is presented in the fre-quency domain with a unique frequency pattern.
The detailed spatial domain to frequency domain mapping is explained inSect. 5.2.1.
4.3 Two Steps of Spatial Filtering
The phased-array multiplexing architecture can achieve two steps of spatial fil-tering in the following way:
• The coarse spatial filtering is realized by the analog band-pass filter as shown inFig. 4.1. Because of the unique mapping from spatial to frequency domain, a
48 4 Two-Step Beam-Forming: Multiplexing Architecture
filter in frequency domain can result in a filter in spatial domain. This filter isused to filter out the spatial interferences far away from the desired angle ofincidence, to relax the specification requirement for the following ADC. Notethat it is called coarse spatial filtering, because it is a coarse-selectivity.
• The final spatial filtering is realized after the digital band-pass filter as shownin Fig. 4.1. It is the place where the final array pattern is formed. Afterde-multiplexer and phase-shifter, the achieved final array pattern is similar to aconventional phased-array pattern. Note that the final selectivity can only beapplied within the region that is defined by the coarse-selectivity.
The detailed coarse and final spatial filtering is explained in Sect. 5.2–5.4.
4.4 Phased-Array Analog and Digital Co-Design
As previously explained, the design of the phased-array multiplexing architecturecan be separated in two parts: the coarse spatial filtering in analog domain, and thefinal spatial filtering in digital domain. Hence, the phased-array functionality isachieved by a co-design in the analog and digital domain with different designfocus.
• In the analog part, the focus of the design is the coarse spatial filtering band-width. If the bandwidth is too small, the final array pattern in the digital domaincannot be achieved. (Note that the final selectivity can only be applied withinthe region that is defined by the coarse-selectivity.) If the bandwidth is too large,the coarse-selectivity is not effective, and the ADC design specification cannotbe relaxed, because of the interference. Hence it is a trade-off, and it is deter-mined by the number of antennas K, the analog filter bandwidth BWa, and theswitching frequency fS.
• In the digital part, the focus of the design is on the digital beam-steering speedand accuracy. It is determined by the implementation of the digital phase-shifter.
The idea of phased-array analog and digital co-design is to make both analogand digital designs programmable, so that we can achieve phased-array func-tionality with more flexibility.
4.5 Generalized Phased-Array System Design
With a programmable phased-array structure, the separation between analog anddigital beam-forming is not so sharp anymore. Besides the phase-shifter, we cantake more design parameters into considerations, so the phased-array functional-ities can be achieved partly in analog and partly in digital domain. In Sect. 3.6,
4.3 Two Steps of Spatial Filtering 49
a generalized beam-forming model is presented. The phased-array multiplexingarchitecture is one of the realizations of such a generalized beam-forming model.
• From interference point of view, the array pattern is partly formed in analog andpartly in digital domain.
• From noise point of view, in analog domain, the multiplexing phased-array has asimilar structure as analog phased-array, in terms of K:1 combination. Hence thenoise behavior is also similar to an analog phased-array. But with such a noisecost, we still keep the flexibility to perform the final phase-steering in the digitaldomain.
The detailed flow diagram of a multiplexing phased-array is presented inSect. 6.6.
50 4 Two-Step Beam-Forming: Multiplexing Architecture
Chapter 5Multiplexing Architecture, IdealBehavior
Figure 4.1 shows the block diagram of a multiplexing phased-array receiver. Thesignal is processed in the following different steps: analog switching, analogcombining, analog mixing, analog filtering, AD conversion, digital switching,digital phase shifting, digital combining, and in the end filtering. In this chapter,we will mathematically analyze this architecture in detail. Section 5.1 discussesthe architecture up to the first combination which is the analog combination. Theproperties of the combined signal will be discussed using traditional phase mod-ulation theory. Based on the result, a new coefficient function Dn will be intro-duced in Sect. 5.2 to explain the properties of the combined signal. Based on theproperties of the combined signal, we introduce a new concept, which is a fre-quency to space filtering transformation. Section 5.3 discusses the digital part ofthe architecture. A mathematical analysis is applied to the digital de-multiplexingand phase shifting. After the second combination, in digital domain, the arraypattern of the multiplexing architecture is simulated in Sects. 5.4 and 5.5 concludeswhat has been discussed in this chapter.
5.1 Analog Multiplexing
As shown in Fig. 4.1, the multiplexing phased-array architecture starts with trans-ferring signals from multiple channels into one channel. This process can beseparated into two steps, namely switching and combining. In this section, we willfirst introduce the idea of a pulse modulated phased-array signal of a single channel,and then extend the model into multiple channels and the combination of them.
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_5,� Springer Science+Business Media New York 2013
51
5.1.1 Properties of the Switching Signal
Switching is a fundamental part of a multiplexing architecture. In time domain, theswitching signal can be represented by a square wave, as shown in Fig. 5.1, whereTS = 1/fS is the period of the pulse train; tS is the starting time delay of the pulse;a1 and a2 are the positive and negative amplitude, respectively; s is the pulse widthof the pulse.
In one period [0, Ts], u(t) can be expressed as
uðtÞ ¼a2 0� t\tSa1 tS� t\tS þ sa2 tS þ s� t\TS
8
<
:
ð5:1Þ
As we know, this waveform can be represented over (-?, +?) by the complexexponential Fourier series as [65]
uðtÞ ¼Xn¼1
n¼�1cnejn�2pfSt ð5:2Þ
where n is the harmonic order number, fS = (1/TS), and the complex Fouriercoefficients cn can be expressed in two different situations, for n = 0,
c0 ¼1TS�Z TS
0u tð Þ � dt
¼ 1TS�Z tS
0a2 � dt þ
Z tSþs
tS
a1 � dt þZ TS
tSþsa2 � dt
� �
¼ a1 � a2ð Þ � sTS
þ a2
ð5:3Þ
and for n = 0,
ST
t
( )u t
St
1
2
0
α
α
τ
Fig. 5.1 Switching signal
52 5 Multiplexing Architecture, Ideal Behavior
cn ¼1TS�Z TS
0u tð Þ � e�jn�2pfSt � dt
¼ 1TS�Z tS
0a2 � e�jn�2pfSt � dt þ
Z tSþs
tS
a1 � e�jn�2pfSt � dt þZ TS
tSþsa2 � e�jn�2pfSt � dt
� �
¼ a1 � a2
n � p � e�jnpfS 2tSþsð Þ � sin n � pfSsð Þ ð5:4Þ
Substituting cn from (5.3) and (5.4) into (5.2), u(t) can be further expressed as
uðtÞ ¼P
n¼0cnejn�2pfSt þ
Pn¼1
n¼�1n 6¼0
cnejn�2pfSt
¼ a1�a2ð Þ�sTS
þ a2
h i
þ a1�a2p �
Pn¼1
n¼�1n 6¼0
sin n�pfSsð Þn � e�jn�pfS 2tSþsð Þ � ejn�2pfSt
2
6
4
3
7
5
ð5:5Þ
Figure 5.2 shows the amplitude part of the frequency spectrum of u(t), for thepositive part of the frequency axis.
At each integer multiples of harmonic TS/s, the envelope of u(t) drops to zero.
5.1.2 Pulse Modulation
According to communication theory [66], any physical band-pass waveform canbe represented by
sðtÞ ¼ Re m tð Þ � ej2pfCt� �
ð5:6Þ
Where Re{.} denotes the real part of {.}, m(t) is called the complex envelope ofs(t), and fC is the associated carrier frequency. In a phased-array receiving system,the signals arriving in each channel are the original signal with different phaseshifts. The signals received by the kth antenna element can be written as
M U Lf
SS
Tf
0 1 2 TS/τn= 2TS/
2 SS
Tf Frequency
Amplitude
Sf 2 Sf0 τ ττ
. .
Fig. 5.2 Amplitude part of the frequency spectrum of u(t)
5.1 Analog Multiplexing 53
skðtÞ ¼ Re m tð Þ � ej2pfCtþðk�1Þun o
ð5:7Þ
where u is the differential carrier phase change between two consecutive antennaelements. The value of u (rad) can be written in the form
u ¼ 2pk� d sin hð Þ ¼ p � sin hð Þ ð5:8Þ
where d is the distance between two adjacent antennas, and assuming d = k/2; k isthe wavelength of the incoming signal; h is the incoming space angle in degrees.Furthermore, in a multiplexing phased-array receiving system, the signal in eachchannel is modulated by a pulse function u(t) which is described in Eq. (5.5). Thebehavior model of this modulation is shown in Fig. 5.3.
From Fig. 5.3, in general situation, the modulated signal in the kth channel canbe expressed as
xkðtÞ¼Re m tð Þ�ej�2pfCtþjðk�1Þuh i
�ukðtÞ
¼mðtÞ�cos 2pfCtþðk�1Þu½ � �Xn¼1
n¼�1cn;kejn�2pfSt
¼12
mðtÞ� ej�2pfCt �ejðk�1Þu �Xn¼1
n¼�1cn;kejn�2pfSt
|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
positive frequency
þe�j�2pfCt �e�jðk�1Þu �Xn¼1
n¼�1cn;kejn�2pfSt
|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
negative frequency
2
6
6
6
6
6
4
3
7
7
7
7
7
5
ð5:9Þ
1
2
k
K
21Re ( ) ( )Cj f tm t e u tπ⎡ ⎤⋅ ⋅⎣ ⎦
22Re ( ) ( )Cj f t jm t e u tπ ϕ+⎡ ⎤⋅ ⋅⎣ ⎦
2 ( 1)Re ( ) ( )Cj f t j KKm t e u tπ ϕ+ −⎡ ⎤⋅ ⋅⎣ ⎦
2 ( 1)Re ( ) ( )Cj f t j kkm t e u tπ ϕ+ −⎡ ⎤⋅ ⋅⎣ ⎦
Fig. 5.3 Model of multiplexing phased-array pulse modulation
54 5 Multiplexing Architecture, Ideal Behavior
where cn,k is the complex Fourier coefficients for the kth channel. In the frequencydomain, the modulated signal has both positive and negative frequencies. Here, weconsider only positive frequencies. Substituting cn from (5.3) and (5.4) into (5.9),xk(t)|positive can be expressed as
xkðtÞjpositive
¼ 12 mðtÞ � ej�2pfCt � ejðk�1Þu �
Pn¼1
n¼�1cn;kejn�2pfSt
� �
ð5:10Þ
The above equation can be expanded into different frequency components.Table 5.1 lists the components until the n = ±4 harmonic.Each frequency component is uniquely defined, and can be identified by four
different properties: frequency component, harmonic number, amplitude, andphase. Closely investigating which parameters of the square wave (Fig. 5.1) andincoming signal (Fig. 5.3) contribute to the above frequency spectrum, we canbreak Eq. (5.10) down into three different properties: frequency, amplitude, andphase. Assuming a normalized case, 0.5*|m(t)| = 1 in (5.10), we can list how theseproperties are influenced:
• Parameters that can influence the frequency: fC; fS; n• Parameters that can influence the amplitude: a1; a2; fS; sk
• Parameters that can influence the phase: K; u; fS; sk; tS,k
The square wave amplitudes (a1, a2) directly relate to the component amplitude.The channel number (k), phase difference between two adjacent channel (u), andstarting time delay of the pulse (tS,k) directly relate to the component phase.Amplitude and phase are correlated by fS and sk. In frequency domain, summingall the channels means summing of all spectrum components from each frequencyof all channels. With a given system application target in mind, we can design theabove mentioned parameters such that the properties of the summed signal are as
Table 5.1 Component expansion of the kth channel pulse modulated signal
Number Frequency Component
n = 0 fC 12 mðtÞ � a1�a2ð Þ�sk
TSþ a2
h i
� ejðk�1Þu � ej�2pfCt
n = 1 fC ? fS 12 mðtÞ � a1�a2
p � sin pfSskð Þ � ej ðk�1Þu�2pfStS;k�pfSsk½ � � ej2pðfCþfSÞt
n = 2 fC ? 2fS 12 mðtÞ � a1�a2
2p � sin 2pfSskð Þ � ej ðk�1Þu�4pfStS;k�2pfSsk½ � � ej2pðfCþ2fSÞt
n = 3 fC ? 3fS 12 mðtÞ � a1�a2
3p � sin 3pfSskð Þ � ej ðk�1Þu�6pfStS;k�3pfSsk½ � � ej2pðfCþ3fSÞt
n = 4 fC ? 4fS 12 mðtÞ � a1�a2
4p � sin 4pfSskð Þ � ej ðk�1Þu�8pfStS;k�4pfSsk½ � � ej2pðfCþ4fSÞt
n = -1 fC - fS 12 mðtÞ � a1�a2
p � sin pfSskð Þ � ej ðk�1Þuþ2pfStS;kþpfSsk½ � � ej2pðfC�fSÞt
n = -2 fC - 2fS 12 mðtÞ � a1�a2
2p � sin 2pfSskð Þ � ej ðk�1Þuþ4pfStS;kþ2pfSsk½ � � ej2pðfC�2fSÞt
n = -3 fC - 3fS 12 mðtÞ � a1�a2
3p � sin 3pfSskð Þ � ej ðk�1Þuþ6pfStS;kþ3pfSsk½ � � ej2pðfC�3fSÞt
n = -4 fC - 4fS 12 mðtÞ � a1�a2
4p � sin 4pfSskð Þ � ej ðk�1Þuþ8pfStS;kþ4pfSsk½ � � ej2pðfC�4fSÞt
5.1 Analog Multiplexing 55
needed. For example, in [28], these parameters are designed to reach maximumamplitude at frequency fC - fS.
5.1.3 Combination in the Analog Domain
In a multiplexing receiver system, the channels are conducting one after eachother, sequentially. When one channel is conducting, other channels must beisolated. Moreover, the conducting time during of each channel is evenly dis-tributed in period TS. Figure 5.4 describes such a square wave.
For simplicity, assuming all paths sk equal to 1/(K�fS), and assuming also a1 = 1,a2 = 0, tS,1 = 0/(K�fS), tS,2 = 1/(K�fS), tS,k = (k - 1)/(K�fS), tS,K = (K - 1)/(K�fS),Eq. (5.10) simplifies to xk(t)|equal-paths as
xkðtÞjequal�paths
¼ 12 mðtÞ � ej�2pfCt � ejðk�1Þu �
Pn¼1
n¼�1c0n;kejn�2pfSt
� �
ð5:11Þ
Note that for this specific situation of all equal paths, we use c0n;k as the complexFourier coefficients. Note also that u is the differential carrier phase changebetween two consecutive antenna elements. As shown in Fig. 5.3, the pulsemodulated signals from all channels are summed together. Substituting u from(5.8) into (5.11), the summed signal in the time domain can be expressed as
1
1τ
,2St
1α
2α0
,S kt
kτ
2
tST
,S Kt
Kτ
k
2τ
K
t
t
t
Fig. 5.4 Multiplexing pulses
56 5 Multiplexing Architecture, Ideal Behavior
xsumðtÞ ¼X
K
k¼1
xkðtÞjequal�path¼12
mðtÞ � ej2pfCt
�Xn¼1
n¼�1
XK
k¼1
c0n;k � ejðk�1Þ�p sin hð Þ
" #
� ejn�2pfSt
( )
ð5:12Þ
5.2 Spatial to Frequency Mapping
Define Dn as the coefficient function of the nth order harmonic
DnðK; hÞ ¼X
K
k¼1
c0n;k � ejðk�1Þ�p sin hð Þ ð5:13Þ
Dn is determined by two variables, K and h, in which K is the number of antennasand h is the incoming signal angle of incidence. Substituting (5.13) into (5.12),xsum(t) can be expressed as
xsumðtÞ ¼12
mðtÞ � ej2pfCt �Xn¼1
n¼�1DnðK; hÞ � ejn�2pfSt ð5:14Þ
Taking the Fourier transform of (5.14), we obtain
Xsumðf Þ ¼12
Mðf Þ �Xn¼1
n¼�1DnðK; hÞ � dðfC � n � fSÞ ð5:15Þ
The above Eq. (5.15) indicates that the frequency spectrum of xsum(t) is mod-ulated by the incoming signal angle of incidence h. In another word, a multi-plexing phased-array architecture transfers space angle information into frequencyinformation. This property will be discussed in detail in Sect. 5.2.1.
5.2.1 Space to Frequency Mapping Coefficient Dn
To understand the summed phase modulated signal xsum(t), it is important tounderstand function Dn(K,h) first. In the following analysis, we assume fourantennas, normalized input signal, and normalized and equal paths, we get: K = 4,s4 = 1/(4�fS), a1 = 1, a2 = 0, tS,1 = 0/(4�fS), tS,2 = 1/(4�fS), tS,3 = 2/(4�fS),tS,4 = 3/(4�fS; 0.5*|m(t)| = 1. Taking all these assumptions into account, thesummed signal in (5.12) can be re-written as
5.1 Analog Multiplexing 57
xsumðtÞ ¼X
4
k¼1
xkðtÞjequal�path ¼ ej2pfCt �Xn¼1
n¼�1
X4
k¼1
c0n;k � ejðk�1Þ�p sin hð Þ
" #
� ejn�2pfSt
( )
ð5:16Þ
From (5.13), the Dn(K,h) for four antennas can be expressed as
Dnð4; hÞ ¼X
4
k¼1
c0n;k � ejðk�1Þ�p sin hð Þ ð5:17Þ
Substituting Eqs. (5.3) and (5.4) into (5.17), and expending the amplitude ofDn(4,h) and ignore the phase component, we have
Dnð4; hÞj j ¼14 �P
4
k¼1ejðk�1Þp sin hð Þ
n ¼ 0
1np � sin np
4
�
� e�jnp4 �P4
k¼1ej ðk�1Þ�p sin hð Þ�n�pfS�2tS;k½ �
n 6¼ 0
8
>><
>>:
ð5:18Þ
Substituting u from (5.8) into (5.18), Table 5.2 extends the relation of harmonicnumber n and |Dn(4,h)|, until the ± 4th harmonic.
Table 5.2 Relation of n and |Dn(4,h)|
when n = 0 (fC)| D0| 1=4ð Þ � 1þ eju þ ej2u þ ej3u
when n = 1-(fC ? fS)| D1| ffiffiffi
2p
=ð2pÞ �
� e�jp4 þ ej u�3p4ð Þ þ ej 2u�5p
4ð Þ þ ej 3u�7p4ð Þ
when n = -1 ((fC - fS)| D-1| ffiffiffi
2p
=ð2pÞ �
� ejp4 þ ej uþ3p4ð Þ þ ej 2uþ5p
4ð Þ þ ej 3uþ7p4ð Þ
when n = 2 (fC ? 2fS)| D2| 1=ð2pÞð Þ � e�jp2 þ ej u�3p
2ð Þ þ ej 2u�5p2ð Þ þ ej 3u�7p
2ð Þ
when n = -2 (fC - 2fS)| D-2| 1=ð2pÞð Þ � ejp2 þ ej uþ3p
2ð Þ þ ej 2uþ5p2ð Þ þ ej 3uþ7p
2ð Þ
when n = 3 (fC ? 3fS)| D3| ffiffiffi
2p
=ð6pÞ �
� e�j3p4 þ ej u�9p
4ð Þ þ ej 2u�15p4ð Þ þ ej 3u�21p
4ð Þ
when n = -3 (fC - 3fS)| D-3| ffiffiffi
2p
=ð6pÞ �
� ej3p4 þ ej uþ9p
4ð Þ þ ej 2uþ15p4ð Þ þ ej 3uþ21p
4ð Þ
when n = 4 (fC ? 4fS)| D4| 0when n = -4 (fC - 4fS)| D-4| 0
58 5 Multiplexing Architecture, Ideal Behavior
From the table, for given n, |Dn(4,h)| is a function of u, and thus, via (5.8), of h.Hence, we can make a two dimensional table based on Table 5.2 to look up thevalue of |Dn(4,h). Table 5.3 shows the value of |Dn(4,h)| for different h andn combinations. Table column represents the harmonic (amplitude) distribution fora certain angle of incidence h. For example, 0 means the fundamental tone fC, ± 1means sidebands fC ? fS and fC - fS, etc.
The dashed line (within) indicates the minimum required harmonics to have atlease 90 % (as an example) of total power for a certain angle of incidence h. Forexample, if h = 30�, 0.92 = 0.81 has not reached 90 % of total power;0.92 ? 0.32 = 0.9 has reached exactly 90 % of total power, so the dashed line isdrawn at n = ±3. From the above analysis, |Dn(4,h)| has the property of
D�nð4;�hÞj j ¼ Dnð4; hÞj j ð5:19Þ
Moreover, at even harmonic number, when n = 0, 2, 4, 6, 8…
Dnð4; hÞj j ¼ D�nð4; hÞj j ¼ D�nð4;�hÞj j ð5:20Þ
(5.19) and (5.20) is also true for other k values. So we have
Table 5.3 Values of |Dn(4,h)| with different h and n combinations
Θn 0 10 20 30 40 50 60 70 80 90
-8 − − – – – – – – – –-7 – 0.058 0.110 0.129 0.113 0.079 0.044 0.019 0.004 –-6 – 0.049 0.052 – 0.078 0.147 0.189 0.208 0.212 0.212-5 – 0.046 0.039 – 0.036 0.049 0.040 0.022 0.006 –-4 – – – – – – – – – –-3 – 0.136 0.256 0.300 0.264 0.184 0.103 0.044 0.010 –-2 – 0.147 0.155 – 0.234 0.441 0.568 0.622 0.636 0.637-1 – 0.229 0.194 – 0.180 0.245 0.200 0.108 0.030 –0 1.000 0.823 0.409 – 0.231 0.267 0.191 0.093 0.024 –1 – 0.407 0.767 0.900 0.791 0.552 0.309 0.131 0.031 –2 – 0.147 0.155 – 0.234 0.441 0.568 0.622 0.636 0.6373 – 0.076 0.065 – 0.060 0.082 0.067 0.036 0.010 –4 – – – – – – – – – –5 – 0.081 0.154 0.180 0.158 0.110 0.062 0.026 0.006 –6 – 0.049 0.052 – 0.078 0.147 0.189 0.208 0.212 0.2127 – 0.033 0.028 – 0.026 0.035 0.029 0.015 0.004 –8 – – – – – – – – – –
The dashed line (within) indicates the minimum required harmonics to have at least 90 % of totalpower
5.2 Spatial to Frequency Mapping 59
D�nð4;�hÞj j ¼ Dnð4; hÞj jDnð4; hÞj j ¼ D�nð4; hÞj j ¼ D�nð4;�hÞj j ðn ¼ 2; 4; 6 � � �Þ
ð5:21Þ
Figure 5.5 shows the spectrum of |xsum(t)| with incidence angels of 0, 30, 60, 90�.For different angle of incidence, the spectrum looks differently. At 0�, the peak
is centered at fC; at 10�, the energy is spreading from fC to fC ? fS and fC - fS; at30�, the peak is centered at fC ? fS, and energy of fC goes to zero. At 60�, theenergy is spreading to many harmonics in the spectrum. The spectrum of xsum(t) is
Cf
sumX
1.0
0
θ=0°
f
Cf0
θ=30°
f
0
θ=60°
f
C Sf f+C Sf f−
Cf
0
θ=10°
fCf
C Sf f+C Sf f−
1.0
1.0
1.0
sumX
sumX
sumX
(d)
(c)
(b)
(a)
Fig. 5.5 Amplitude part of the spectrum of Xsum(f) for a h = 0� b h = 10� c h = 30� d h = 60�
60 5 Multiplexing Architecture, Ideal Behavior
phase modulated. As Sect. 4.2 explained, a multiplexing phased-array architecturetransfers space angle information into frequency information. Furthermore, there isa unique translation from incoming angle of incidence h to frequency spectrumpattern.
5.2.2 Translation from Voltage to Power Domain,Dn to Pxn
Power in a sinusoidal signal depends only on its amplitude, and is independent offrequency and phase [67]. Remember that in Sect. 2.2, we have discussed in (2.24)that the power of the carrier is spread over the various side components as afunction of h. Hence, we also have
X1
n¼�1DnðK; hÞj j2 ¼ 1 ð5:22Þ
Define Pxn(K,h) as the power contained in the nth pair of side frequency
Px0ðK; hÞ ¼ D0ðK; hÞj j2
PxnðK; hÞ ¼ DnðK; hÞj j2þ D�nðK; hÞj j2n ¼ 0
n� 1
(
ð5:23Þ
Thus, (5.22) can also be written as
X1
n¼0
PxnðK; hÞ ¼ 1 ð5:24Þ
Table 5.4 Values of Pxn(K,h) with different h and n combinations (when K = 4).
nθ 0 1 2 3 4 5 6 7 8 9
0 1.000 – – – – – – – – –
10 0.678 0.218 0.043 0.024 – 0.009 0.005 0.005 – 0.003
20 0.167 0.627 0.048 0.070 – 0.025 0.005 0.013 – 0.008
30 – 0.811 – 0.090 – 0.032 – 0.017 – 0.01
40 0.053 0.658 0.109 0.073 – 0.026 0.012 0.013 – 0.008
50 0.071 0.365 0.389 0.041 – 0.015 0.043 0.007 – 0.005
60 0.036 0.135 0.646 0.015 – 0.005 0.072 0.003 – 0.002
70 0.009 0.029 0.775 0.003 – 0.001 0.086 – – –
80 – 0.002 0.808 – – – 0.090 – – –
90 – – 0.811 – – – 0.090 – – –
The dashed line (within) indicates the minimum required harmonics to have at lease 90 % of totalpower
5.2 Spatial to Frequency Mapping 61
Note that (5.24) does not mean physically adding the power. It is a powerproperty indication over all harmonics. Table 5.4 shows the value of Pxn(K,h) withdifferent h and n combination, when K = 4. Table row represents the harmonicpower distribution for a certain angle of incidence h. For example, 0 means thefundamental tone fC, 1 means sidebands fC ± fS, etc.
The dashed line (at left) indicates the minimum required harmonics to have atlease 90 % (as an example) of total power. Figure 5.6a plots the values fromTable 5.4. For h sweeping from 0 to 90�, the value of Pxn(K,h) is shown, with n asa parameter (n from 0 to 6).
Table 5.4 and Fig. 5.6a show that at different angles of incidence, the energyconcentrates in different side frequencies. For example, at 0�, all energies are storedin n = 0, which is the fundamental frequency. At 30�, 81 % of the energies are storedin n = 1, and the rest of the energies are only stored in the odd harmonics. At 90�,81 % of the energies are stored in n = 2, and the rest of the energies are only stored inthe even harmonics. The above properties give the translation from space/angledifference into frequencies spectrum/energy difference.
Figure 5.6b again shows the Pxn(K,h) plot, but now for 16 antennas. Comparingwith Fig. 5.6a, the side frequency energy is more concentrated around the corre-sponding spatial angle, which indicates a better spatial resolution.
Fig. 5.6 Pxn(K,h) as a function of h, n = 0,1,2,3,4,5,6 a when K = 4, b when K = 16
62 5 Multiplexing Architecture, Ideal Behavior
5.2.3 Coarse Beam Pattern RxN by Frequency Selectivity
The normalized power sum of the first N pairs of harmonics is given by
RxNðK; hÞ ¼X
N
n¼0
PxnðK; hÞ
¼ D0ðK; hÞj j2þX
N
n¼1
DnðK; hÞj j2þ D�nðK; hÞj j2h i
ð5:25Þ
Note that (5.25) does not mean physically adding the power. It is a powerproperty indication over harmonic pairs up until number N. For example, in case offour antenna elements (K = 4), and 10� of angle of incidence (h = 10�)
Rx0 ¼ Px0 ¼ 0:678 ðN ¼ 0ÞRx1 ¼ Px0 þ Px1 ¼ 0:896 ðN ¼ 1ÞRx2 ¼ Px0 þ Px1 þ Px2 ¼ 0:939 ðN ¼ 2ÞRx3 ¼ Px0 þ Px1 þ Px2 þ Px3 ¼ 0:963 ðN ¼ 3Þ
ð5:26Þ
Following (5.26), we can mark in Tables 5.3 and 5.4 dashed line representingthe boundary of the minimum required harmonics to have at lease 90 % of totalpower. Two plots of RxN(K,h) (in dB) as a function of h are shown in Fig. 5.7.
Fig. 5.7 RxN(K,h) as a function of h, N = 0,1,2,3, a when K = 4, b when K = 16
5.2 Spatial to Frequency Mapping 63
From Fig. 5.7a, one can notice that the array coarse-pattern looks differently forvarious N. If N increases, the array coarse-pattern in space becomes less selective,meaning less spatial filtering effect. Note that N denotes the first N pairs ofsideband frequencies which are preserved after analog band-pass filtering, as in(5.25), which represent the effect of the frequency filter. Hence, the above figureshows that a filter in the frequency domain results in a filter in space domain. Thisphenomenon is shown more clearly in Fig. 5.8.
Figure 5.7b again shows the Rxn(K,h) plot, but for 16 antennas. Comparing withFig. 5.7a, with we see that for equal step of filter bandwidth increase in frequencydomain, the spatial filter bandwidth is increasing with better resolution. It confirmsour analysis in Fig. 5.6.
Figure 5.8a shows that the band-pass filter passes only the 0th order harmonicsignal. The corresponding array coarse-pattern Rx0(4,h) is displayed, and the -3 dBspatial bandwidth is h = [-13�, 13�]. It means that signals coming from -13 to 13�in space are allowed to pass (attenuation less than 3 dB), and the signals coming fromother degrees are attenuated. Similarly, Fig. 5.8b shows that a band-pass filter thatpasses the 0th and 1st order signals. The corresponding array coarse-pattern Rx1(4,h)is displayed, and the -3 dB spatial bandwidth is h = [-48�, 48�]. Figure 5.8c showsthat a band-pass filter that passes the 0th, 1st, and 2nd order signals. The corre-sponding array coarse-pattern Rx2(4,h) is displayed, and the -3 dB spatial band-width is h = [-90�, 90�], which means almost no spatial selectivity applied. Notethat in this book, we only discuss the brick-wall filter [68]. Taking other filters(meaning different weight function for the spectrum components), one can get dif-ferent spatial patterns. Small part of the desired signal that located outside the filter
( )sumx t
0 f
0
0
fC-2fS fC-fS fC fC+fS fC+2fS
ffC-2fS fC-fS fC fC+fS fC+2fS
ffC-2fS fC-fS fC fC+fS fC+2fS
( )sumx t
( )sumx t
N=0
N=1
N=2
Rx0(4,θ)
Rx1(4,θ)
Rx2(4,θ)
θ
θ
θ
(a)
(b)
(c)
Fig. 5.8 Frequency to space filtering, with array coarse-pattern, for K = 4, a N = 0, b N = 1,c N = 2
64 5 Multiplexing Architecture, Ideal Behavior
bandwidth is blocked by the band-pass filter. This part of the missing signal can notbe calibrated or compensated in the digital domain, so after the digital demodulation,the bit error rate (BER) of the desired signal will slightly degrade. To choose the filterbandwidth, there is a trade-off between interference suppression requirement andBER requirement. In this book, we choose filter bandwidth based on the interferencesuppression specification. In practice, we should always check the influence to BERdegradation.
5.3 Digital De-multiplexing and Phase-Shifting
Figure 5.5 shows that the multiplexing phased-array architecture translates theinput signal for each angle of incidence h to a specific frequency spectrum pattern.Figure 5.8 shows that a filter in frequency domain results in a filter in spacedomain and hence forms the array coarse-pattern. Figure 5.9 shows how the signalis further processed in the digital domain. First, the signal is de-multiplexed fromone path back to four paths, and then these four signals are phase shifted accordingto the desired viewing angle and combined. At last, a band-pass filter is used toclean up the frequency spectrum.
In practice, the summed multiplexed signal from (5.14) passes through themixer, the filter, and the ADC to reach at the input of de-multiplexer. To simplifythe analysis, we assume a normalized situation, 0.5*|m(t)| = 1, and the transferfunctions of the mixer, the filter, and the ADC equal to one. So the complexenvelope of the input signal is Dn(K,h), as shown in Fig. 5.9. The input signal isfurther processed by de-multiplexer and digital phase shifter. Note that the de-multiplexer is using the same switching frequency fS as the multiplexer.Figure 5.10a–e shows the frequency mixing of each input harmonic componentdue to de-multiplexing. This process can be understood by the following steps:
De-multiplexer
delay
delay
delay
delay
Digital phase-shifter
Band-passfilter
0 1 2-1-2HarmonicOrder
Complex envelope:
Dn(K,θ)
yn,1(t)
yn,2(t)
yn,3(t)
yn,4(t)
yn,sum(t)
Fig. 5.9 Signal processing in digital domain
5.2 Spatial to Frequency Mapping 65
First, due to de-multiplexing, the frequency components for each channel at thede-multiplexer input are mixing to other locations with step size fS. Next, thedigital phase delay component (per channel) applies a desired phase shift to thefundamental tone in order to add them in-phase (n = 0). Thirdly, the phaseadjusted fundamental tones from the previous step are added in-phase (per
0 1 2 3 4-4 -3 -2 -1HarmonicOrder
0 1 2 3 4-4 -3 -2 -1
0 1 2 3 4-4 -3 -2 -1
0 1 2 3 4-4 -3 -2 -1
0 1 2 3 4-4 -3 -2 -1
( )1,ky t−
( )0,ky t
( )2,ky t−
( )1,ky t
( )2,ky t
(a)
(b)
(c)
(d)
(e)
Fig. 5.10 Frequency mixingand spectrum reformation ofone channel, a n = -2b n = -1 c n = 0 d n = 1e n = 2
66 5 Multiplexing Architecture, Ideal Behavior
channel). And finally, fundamental components from all four channels are addedtogether.For example, at Fig. 5.10a, the n = -2 component is transferred to:
• the -4th order component via the -2nd (n = -2) harmonic term• the -3rd order component via the -1st (n = -1) harmonic term• the -2nd order component via the DC term• the -1st order component via the 1st (n = 1) harmonic term• the fundamental component via the 2nd (n = 2) harmonic term
of the switching function in (5.5). The same frequency mixing mechanism appliesto input harmonic components n = -1, 0, 1, and 2 in Fig. 5.10b–e, respectively.However, not all the mixing products are of interest. The digital phase shifters aredesigned for maximizing the signal amplitude at the fundamental frequency(n = 0). So only the mixing products which fall into the fundamental frequencyneeds to be further processed, as highlighted in Fig. 5.10. Note that the abovefigure only shows the mixing result of one channel. In case of K channels, theabove analysis happens K times and the K results are then summed together. InFig. 5.9, yn,k(t) is defined as the complex envelope after mixing the nth harmoniccomponent to the fundamental frequency (n = 0) form the kth channel. Forexample, after frequency mixing in Fig. 5.10a, the complex envelope at the fun-damental frequency (n = 0) is y-2,k(t). Table 5.5 displays a two dimensionalparameter matrix, assuming the number of channels is four (K = 4).y-2,sum(t) means the sum of the fundamental tones (n = 0) from 4 channels, fromwhich the fundamental tone is converted from n = -2 harmonic for each channel.This definition can be extended for all other yn,sum(t). The column of Table 5.5 ismatched to the Fig. 5.10 explanation.
Taking n = -2 as an example, y-2,k(t) can be express as
y�2;1ðtÞ ¼ D�2ð4; hÞ � c02;1 � ej�0c
y�2;2ðtÞ ¼ D�2ð4; hÞ � c02;2 � ej�1c
y�2;3ðtÞ ¼ D�2ð4; hÞ � c02;3 � ej�2c
y�2;4ðtÞ ¼ D�2ð4; hÞ � c02;4 � ej�3c ð5:27Þ
where c is the digital phase shifter in radians. Applying the definition of Dn in(5.17), we get
Table 5.5 Parameter matrix of yn,k(t), when K = 4
k n 1 2 3 4 sum
n = -2 y-2,1(t) y-2,2(t) y-2,3(t) y-2,4(t) y-2,sum(t)n = -1 y-1,1(t) y-1,2(t) y-1,3(t) y-1,4(t) y-1,sum(t)n = 0 y0,1(t) y0,2(t) y0,3(t) y0,4(t) y0,sum(t)n = 1 y1,1(t) y1,2(t) y1,3(t) y1,4(t) y1,sum(t)n = 2 y2,1(t) y2,2(t) y2,3(t) y2,4(t) y2,sum(t)
5.3 Digital De-multiplexing and Phase-Shifting 67
Dnð4;/Þ ¼X
4
k¼1
c0n;k � ejðk�1Þ�p sin /ð Þ ð5:28Þ
Let c = p*sin (Ø), we get
y�2;sumðtÞ ¼ y�2;1ðtÞ þ y�2;2ðtÞ þ y�2;3ðtÞ þ y�2;4ðtÞ
¼ D�2ð4; hÞ �X
4
k¼1
c02;k � ejðk�1Þ�p sin /ð Þ
¼ D�2ð4; hÞ � D2ð4;/Þ
ð5:29Þ
Applying the same calculation to Fig. 5.10b–e results in
y�1;sumðtÞ ¼ D�1ð4; hÞ � D1ð4;/Þy0;sumðtÞ ¼ D0ð4; hÞ � D0ð4;/Þy1;sumðtÞ ¼ D1ð4; hÞ � D�1ð4;/Þy2;sumðtÞ ¼ D1ð4; hÞ � D�2ð4;/Þ
ð5:30Þ
If we preserve all sidebands power (extend to infinite) and transfer them to thefundamental frequency (n = 0) through de-multiplexing, the complete input car-rier power is preserved. If the desired phase delay is applied to each path, at thefundamental tone (n = 0), all folded frequency components are added in phase,and at other location (n = 0), all folded frequency components are added out-of-phase. Hence, the complete input carrier power is preserved at the fundamentaltone (n = 0), and we can obtain the power at the fundamental tone by fist addingthe in-phase signal and then take the square of the sum, as
y�1;sumðtÞ þ � � � y�1;sumðtÞ þ y0;sumðtÞ þ y1;sumðtÞ þ � � � þ yþ1;sumðtÞ
2¼ 1 ð5:31Þ
Substituting (5.30–5.31), we obtain
D0ðK; hÞ � D0ðK;/Þ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
fundamental term
þX1
n¼1
DnðK; hÞ � D�nðK;/Þ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
positive harmonic terms
þX1
n¼1
D�nðK; hÞ � DnðK;/Þ|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
negative harmonic terms
2
¼ 1
ð5:32Þ
Note that (5.32) means physically adding the converted signal (from otherharmonics) with phase information at the fundamental frequency (n = 0). DefiningPyn(K,h,Ø) as the power transferred to the fundamental frequency from the nthpair of side frequency, we obtain
Py0ðK; h;/Þ ¼ D0ðK; hÞ � D0ðK;/Þ n ¼ 0PxnðK; h;/Þ ¼ DnðK; hÞ � D�nðK;/Þ þ D�nðK; hÞ � DnðK;/Þ n� 1
ð5:33Þ
68 5 Multiplexing Architecture, Ideal Behavior
Thus, (5.32) can also be written as
X1
n¼0
PynðK; h;/Þ
2
¼ 1 ð5:34Þ
The normalized power sum of the first N pairs of harmonics is given by
RyNðK; h;/Þ ¼X
N
n¼0
PynðK; h;/Þ
2
¼ D0ðK; hÞ � D0ðK;/Þ þX
N
n¼1
DnðK; hÞ � D�nðk;/Þ
þX
N
n¼1
D�nðK; hÞ � DnðK;/Þ
2
ð5:35Þ
Equation (5.35) shows the array pattern after de-multiplexing. Remember thatin (5.25) and Fig. 5.7, RxN(K,h) shows the array pattern after multiplexing. In thenext section, the array pattern after multiplexing and de-multiplexing are plotted asa function of space angle of incidence h.
5.4 Array Pattern
Following the discussion from the previous section, Fig. 5.11 shows the arraypatterns RxN(K,h) and RyN(K,h,Ø) as a function of h. Here, we take an example offour antenna elements (K = 4); the normalized power sum of the 1st pairs ofsideband frequencies which are preserved after analog band-pass filtering (N = 1),
-80 -60 -40 -20 0 20 40 60 80-70
-60
-50
-40
-30
-20
-10
0
θ, Angle of Incidence [degree]
Nor
mal
ized
Arr
ay G
ain
[dB
]
Rx1
Ry1
Fig. 5.11 RxN, RyN as afunction of h, when K = 4,N = 1, Ø = 10�
5.3 Digital De-multiplexing and Phase-Shifting 69
as shown in Fig. 5.8b; and a desired viewing angle of 10� (Ø = 10�). Note thatRxN is the beam pattern before de-multiplexing and digital combination, while RyN
is the beam pattern after it.As in Fig. 5.8b, Rx1 results from a frequency filter with bandwidth larger than
the 1st sideband but smaller than the 2nd sideband. Energies stored in the 0th and1st sidebands are preserved, which is the ‘‘available signal power’’, and sidebandsignals above 2nd order are filtered out. After de-multiplexing and digital phaseshifting (with Ø = 10�), we obtain Ry1 which is the recovered pattern. It cannotexceed the pattern given by Rx1. Ry1 is peaked at 10� as expected. Figure 5.12shows the polar diagram of RxN(K,h) and RyN(K,h,Ø). It shows that the final array(in red line) pattern can only stay within the area defined by the array coarse-pattern (in dashed blue line).
0.2
0.4
0.6
0.8
1
30
210
60
240
90
270
120
150
330
180 0
Rx1
Ry1
Fig. 5.12 Polar diagramof RxN, RyN, when K = 4,N = 1, Ø = 10�
-80 -60 -40 -20 0 20 40 60 80-70
-60
-50
-40
-30
-20
-10
0
θ, Angle of Incidence [degree]
Ry N
, N
orm
aliz
ed A
rray
Gai
n [d
B]
N=0N=1N=10
Fig. 5.13 RyN as a functionof h with N = 0, 1, 10, whenK = 4, Ø = 10�
70 5 Multiplexing Architecture, Ideal Behavior
Remember in Fig. 5.7, we explained that the array coarse-pattern looks dif-ferently for various N. If N increases, array coarse-pattern in space becomes lessselective, meaning less spatial filtering effect. In Fig. 5.13, the array final-pattern isplotted for various N.
Assuming K = 4, and Ø = 10�, a plot of RyN (N = 0, 1, 10) as a function of his shown in Fig. 5.13. It is also the array final-pattern. The ideal pattern shouldpeak at (10�, 0 dB). Compare these three lines, the blue line (N = 0) is peaking at(0�, -1.7 dB), the green line (N = 1) is peaking at (7.3�, -0.85 dB), and the redline (N = 10) is peaking at (9.7�, -0.12 dB). It means that the larger the N, thecloser the final-pattern to the ideal pattern. Hence there is a trade-off between arraycoarse-pattern and final-pattern for different N
• When N is large, which means the analog band-pass filter has a wide bandwidth,array coarse-pattern is less selective, but the array final-pattern is more accurate.
• When N is small, which means the analog band-pass filter has a narrow band-width, array coarse-pattern is more selective, but the array final-pattern is lessaccurate. However, we know this angle offset before-hand, so a look-up table indigital domain can be implemented to compensate this angle offset, but thepower loss due to narrow band filtering is not correctable in digital domain.
5.5 Conclusion
In this chapter, we have discussed the multiplexing architecture from a mathe-matical point of view. We used various models to understand the properties of thesystem. Firstly, the properties of the analog combined signal were described and asimilarity with traditional phase modulation theory was explained. Secondly, anew coefficient function Dn is introduced to help understand the properties of thecombined signal. Thirdly, we introduced a new concept: frequency to space fil-tering transformation. Next, by processing the signals in the digital domain, thefinal array pattern is achieved. Furthermore, the array pattern is compared with thetraditional analog beam-forming array pattern and key system parameters arerevealed.
5.4 Array Pattern 71
Chapter 6Multiplexing Architecture, Non-idealBehavior
In this chapter, a few important non-idealities of a multiplexing phased-arrayarchitecture are discussed. Section 6.1 discusses the angle deviation from theexpected viewing angle due to the finite analog filter bandwidth. Section 6.2presents the influence of non-ideal switches on the array pattern. Section 6.3discusses the noise performance in a sampling environment. Section 6.4 discussesthe impact of adjacent channel interference. Section 6.5 presents simulation resultsof the multiplexing architecture. Section 6.6 shows the signal, noise and distortionpower flow diagram of a multiplexing architecture, which is the realization of thegeneralized phased-array model presented in Sects. 3.6 and 6.7 concludes what hasbeen discussed in this chapter. Non-idealities like timing jitter impact and isolationbetween switch paths are not discussed in this chapter. They are recommended forfuture works.
6.1 Angle Deviation
Due to limited filter bandwidth, the formed viewing angle after de-multiplexingand digital phase shifting (in Fig. 5.13 this is the h value where the array patternhas its peak) is not the same as the expected viewing angle (desired signal angle ofincidence). Assuming DN(Ø) represents the angle deviation of the formed viewingangle from the expected viewing angle Ø, where N denotes the first N pairs ofsideband frequencies which are preserved after analog band-pass filtering. Definehpeak,N as the formed viewing angle after digital beam-forming, we have
DNð/Þ ¼ /� hpeak;N ð6:1Þ
For example in Fig. 5.13, the expected viewing angle is 10�, hence
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_6,� Springer Science+Business Media New York 2013
73
D1ð10�Þ ¼ 10� � 7:3� ¼ 2:7�
D10ð10�Þ ¼ 10� � 9:7� ¼ 0:3�ð6:2Þ
Figure 6.1 plots the relation shown in (6.1), where angle deviations DN versusthe expected viewing angle Ø.
It shows that the higher the N (thus larger filter bandwidth), the smaller the angledeviation DN, the closer the formed viewing angle is to the expected viewing angle.In case of infinite bandwidth (N = ?), the formed viewing angle can followexactly the expected viewing angle, which means that D? = 0. For K = 4, and aspatial viewing range of (-30�, +30�), the band-pass filter shown in Fig. 5.8(b)(N = 1) will result in an angle deviation between (-0.7�, 2.7�). As mentioned inSect. 5.4, the angle deviation caused by choosing a small N can be compensated byimplementing a look-up table in digital domain. And this table can be created basedon Fig. 6.1, but the power loss due to narrow band filtering is not correctable indigital domain.
6.2 Non-ideal Switches
In reality, the switches need to be implemented by electronic circuits that do notperform ideally. Assuming a1 being the switch loss when switch is on, and a2 beingthe finite channel isolation when switch is off, the on/off difference is a1 - a2.Considering the previous LNA stage can provide gain to compensate the switchloss, the absolute values of a1 and a2 are not of interest, thus we assume a nor-malized condition, a1 = 0 dB for the following analysis. The according non-idealvariation of |Dn(4,h)| in (5.18) can be expressed as (taking K = 4 as an example)
0 10 20 30 40 50 60 70 80 90-5
0
5
10
15
20
25
30
35
40
45
Φ, Expected viewing angle [degree]
ΔN
[deg
ree]
N=1N=2N=10
Fig. 6.1 DN (in degree) as afunction of Ø with N = 1, 2,10, when K = 4
74 6 Multiplexing Architecture, Non-ideal Behavior
Dnð4; hÞj jni¼
a1 � a2
4þ a2
� �
�X
4
k¼1
ejðk�1Þp sin hð Þ
�
�
�
�
�
�
�
�
�
�
n ¼ 0
a1 � a2
np� sin
np4
� �
� e�jnp4 �X
4
k¼1
ej ðk�1Þ�p sin hð Þ�n�pfS�2tS;k½ ��
�
�
�
�
�
�
�
�
�
n 6¼ 0
8
>>>><
>>>>:
ð6:3Þ
The index ‘ni’ refers to ‘non-ideal’. In the digital domain, the switchingbehavior is ideal, so there is no loss and infinite channel isolation, which results in
Dnð4;/Þj jni¼ Dnð4;/Þj j ð6:4Þ
Considering a non-ideal situation, we can re-write RxN in (5.25) as (whenK = 4)
RxNð4; hÞni ¼ D0ð4; hÞj j2ni
þPN
n¼1Dnð4; hÞj j2niþ D�nð4; hÞj j2ni
h i ð6:5Þ
Similarly, we can re-write RyN in (5.35) as (when K = 4)
RyNð4; h;/Þni ¼
D0ð4; hÞni � D0ð4;/Þ þX
N
n¼1
Dnð4; hÞni � D�nð4;/Þ þX
N
n¼1
D�nð4; hÞni � Dnð4;/Þ�
�
�
�
�
�
�
�
�
�
2
ð6:6Þ
Figure 6.2 shows a plot of RxN(4,h)ni and RyN(4,h,Ø)ni as a function of h forK = 4, N = 1 and Ø = 10�, and assuming a switch loss of a1 = 0 dB, and a finitechannel isolation of a2 = 25 dB. As the switch are non-ideal, the array patterns are
-80 -60 -40 -20 0 20 40 60 80-70
-60
-50
-40
-30
-20
-10
0
10
θ, Angle of Incidence [degree]
Nor
mal
ized
Arr
ay G
ain
[dB
]
Rx1ni
Ry1
ni
Fig. 6.2 RxNni, RyNni as afunction of h, when K = 4,N = 1, Ø = 10�
6.2 Non-ideal Switches 75
affected. Figure 6.3 shows the polar diagram of RxN(4,h)ni and RyN(4,h,Ø)ni.Figure 6.4 shows the array patterns as a function of h when N = 0, 1, 10.
Figure 6.5 shows the angle deviation as a function of Ø with N = 1, 2, 10,when K = 4, a1 = 0 dB, a2 = 25 dB.
Comparing this with Fig. 6.1, we see that for all N, the angle deviation hasbecome larger. Even with high filter bandwidth, the actual viewing angle stillcannot perfectly follow the expected viewing angle. For K = 4, within the range of30�, D1_ni has a deviation range between (-0.2�, 4.4�). The angle deviation canbe corrected in digital domain with a look-up table. However, the signal power
0.5
1
1.5
30
210
60
240
90
270
120
300
150
330
180 0
Rx1
ni
Ry1
ni
Fig. 6.3 Polar diagramof RxNni, RyNni whenK = 4, N = 1, Ø = 10�
-80 -60 -40 -20 0 20 40 60 80-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
θ, Angle of Incidence [degree]
Ry N
ni,
Nor
mal
ized
Arr
ay G
ain
[dB
]
N=0N=1N=10
Fig. 6.4 RyNni as a functionof h with N = 0, 1, 10, whenK = 4, Ø = 10�
76 6 Multiplexing Architecture, Non-ideal Behavior
loss hence also the modulated signal loss can give direct influence to BER. Therequirement of the switch on/off difference can be discussed following the BERanalysis.
6.3 Noise in a Multiplexing System
In a multiplexing system, not only the signal but also the noise is pulse modulated.Noise from other frequencies can be mixed into the frequency of interest, as shownin Fig. 6.6.
Assuming the noise spectrum is flat, and the noise RMS voltage is Vn,in, in asingle channel, after mixing, the noise power in the frequency of interest can beseparated into two parts: noise power from its own, Pnoise0, and noise powercontributed from the nth pairs of side frequencies, Pnoisen. Noise can be treated assignal without phase information. Based on Eq. (5.11), assume normalized resistorof 1X, the noise power can be expressed as
Pnoise0 Kð Þ ¼ 1K2 � V2
n;in n ¼ 0
Pnoisen Kð Þ ¼ 2 � 1np � sin np
K
� �� �2�V2n;in n� 1
(
ð6:7Þ
where n is the harmonic order number, and K is the number of antennas. Assuminga noise bandwidth BWnoise, and a signal bandwidth BWS, and the noise to signalbandwidth ratio as
Rn ¼BWnoise
BWSð6:8Þ
0 10 20 30 40 50 60 70 80 90-5
0
5
10
15
20
25
30
35
40
45
Φ, Expected viewing angle [degree]
ΔN
ni [
degr
ee]
N=1N=2N=10
Fig. 6.5 DNni (in degree)as a function of Ø withN = 1, 2, 10, when K = 4,a1 = 0 dB, a2 = 25 dB
6.2 Non-ideal Switches 77
Note that fS = 2*BWS. Defining Nr as the number of harmonic pairs that arecontained within the noise bandwidth, we assume the number of harmonic pairs isan integer, instead of a decimal. One can write for Nr with integer function,
Nr ¼ INTRn � 2
4
ð6:9Þ
The combined noise power of K paths can be directly summed over all chan-nels. Taking noise summed up until the Nrth side band
Pnsumr Kð Þ ¼ K �X
Nr
n¼0
Pnoisen Kð Þ ð6:10Þ
The noise power gain Gnoiser(K) can be denoted as the summed noise powerdivided by the original noise power (within the signal bandwidth)
Gnoiser Kð Þ ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Pnsumr Kð Þp
Vn;in
¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
1K þ 2K �
PNr
n¼1
1np � sin np
K
� �� �2
s ð6:11Þ
Figure 6.7 shows the relation between Gnoiser(K) and the bandwidth ratio Rn,for K = 4. It indicates that the smaller the ratio Rn, the better the noise reductionafter multiplexing. When noise and signal use the same frequency band, the noisereduction is 6 dB, which results in the same effect as in the conventional beam-forming.
6.4 Frequency Mixing
In Chap. 4, we have explained the trade-off between antenna number K, signalbandwidth BW, and channel sampling frequency fS through Eq. (4.4). For a singlechannel, according to the Nyquist theory, the condition for no loss of data
0 1 2 n N-1-2-n-N
fS=2*BWS
BWnoise
Harmonic order:
Fig. 6.6 Noise folding when sampling
78 6 Multiplexing Architecture, Non-ideal Behavior
information is fS [ 2BW. However, this condition is only valid when no inter-ference comes from the adjacent channel. When the adjacent channel interferencepresent, the signal and the interferer are both expanded in frequency at the mul-tiplexer’s output, leading to an irrecoverable spectrum overlap, as shown inFig. 6.8.
In order to prevent the spectrum overlap, the channel sampling frequency fSmust be increased to make sure the spectrum expansion is not causing any overlap.As shown in Fig. 6.9, if fS [ BWtotal, the interferer and signal spectrums areexpended together, where BWtotal is the summed spectrum of signal, interferer, andthe signal interferer frequency difference.
For a K channel multiplexer, the switching frequency of the multiplexer fMUL
needs to fulfill fMUL [ K*BWtotal to make sure no overlap for each channel.
6.5 System Simulations
Figure 6.10 shows the system simulation diagram for multiplexing architecture inAdvanced Design System (ADS). The goal for this test is to verify the spatial tofrequency mapping theory that delivered in Chap. 5. In this test, the desired and
Fig. 6.7 Relation of noisepower gain Gnoiser(K) withbandwidth ratio Rn, whenK = 4
f f
Interferer
Signal
fSBW
Fig. 6.8 Effect of adjacentchannel interferer
6.4 Frequency Mixing 79
interference signal comes from 30� and -30�, respectively, and their carrier fre-quency is the same. The phase shifter in digital domain is programmed at 30� toreceive the desired signal. To simplify the simulation complexity, the followsettings are applied: RF carrier frequency is 26 GHz, and sampling frequency foreach channel is 50 MHz.
Figure 6.11 shows the simulation result. Spectrum (a) is the combined spectrumof desired and interference signal and they are located in the same frequency.Spectrum (b) is the effect of multiplexing in a single path. Spectrum (c) shows the4 paths combined signal spectrum. Major part of the 30� signal shifts 50 MHztowards left, and major part of the -30� signal shifts 50 MHz towards right. Withdifferent angle incidence, the spectrum pattern shows differently. Spectrum (d) isthe effect of de-multiplexing in a single path and the phase compensation for 30�is also added. Spectrum (e) shows the 4 paths combined signal spectrum afterphase shifter. Due to the phase compensation, the desired 30� signal shifts back tothe original location, and the interference -30� signal spreads to other harmonicfrequencies. Spectrum (f) is the final desired signal spectrum after a digital band-pass filter.
6.6 Power Flow Diagram for a Multiplexed Architecture
In Chap. 3, we have introduced a signal, noise and distortion power (mW) flowdiagram for analog phased-array, digital phased-array, and general case phased-array structure, respectively. For the multiplexing phased-array structure, we canalso design a power flow diagram as shown in Fig. 6.12.
One can notice that except for parameters that has been explained previously,there are two extra parameters: v1 and v2. They indicate the flexibility of the beam-forming system. The final array pattern is formed in digital domain. Hence thesuppression factor L is located in the right part of the plane.
• v1 represents the array coarse-pattern interference suppression, as in Fig. 5.7. Itis varying between no coarse-pattern (v1 = 1), and final-pattern (v1 = 1/L).
• v2 represents the array noise suppression, as in Fig. 6.7. It is varying between nonoise suppression (v2 = 1), and maximum noise suppression (v2 = K).
f
Interferer
Signal
fBWtotal fS
Fig. 6.9 Signal and interferer spectrum expansion without overlap
80 6 Multiplexing Architecture, Non-ideal Behavior
Fig. 6.10 Multiplexing architecture system simulation diagram in ADS
6.6 Power Flow Diagram for a Multiplexed Architecture 81
In brief, there are two types of power flow in Fig. 6.12,
• The flow of the interference signal, from Iin suppressed to IADC, thanks to thearray coarse-pattern suppression. Then from IADC again suppressed to Iout due tothe array final-pattern suppression.
Fig. 6.10 continued
82 6 Multiplexing Architecture, Non-ideal Behavior
• The flow of the desired signal, from Sin increased to SADC, due to the front-endgain, and then from SADC to Sout with a power gain of one.
6.7 Conclusion
In this chapter, we have discussed a few important non-idealities of a multiplexingphased-array architecture. To reduce the analog filter bandwidth, hence the ADCbandwidth, we have introduced an actual viewing angle to the expected viewingangle deviation. The smaller the band-pass filter bandwidth, the larger the angledeviation. This deviation can be compensated by creating a look-up table in thedigital domain, but the power loss due to narrow band filtering is not correctable indigital domain. The channel isolation indicates the switching quality. If we don’thave a infinite channel isolation, even with high filter bandwidth, the actualviewing angle still can not perfectly follow the expected viewing angle. Thechannel isolation indicates the switching quality. If the channel isolation is notinfinite, even with infinite filter bandwidth, the actual viewing angle still can notperfectly follow the expected viewing angle. To achieve the best signal to noiseratio improvement, the incoming noise bandwidth to signal bandwidth ratio shouldbe small. If the signal and noise bandwidth are the same, then for a four antennaarray, the SNR improvement is 6 dB, which is the same improvement as theconventional beam-forming. For suitable applications, the power flow diagram canbe used as a guideline to specify the block parameters. The system simulation
Fig. 6.11 Multiplexing architecture system simulation result in ADS. Spectrum (a)–(f) corre-sponding to point a-f in Fig. 6.8, respectively
6.6 Power Flow Diagram for a Multiplexed Architecture 83
result shows that a multiplexing phased-array architecture can achieve spatial tofrequency mapping, and it is a good alternative for conventional phased-arrayarchitectures. Moreover, the simulation also shows that multiple sources (desiredsignal) selection is possible with this architecture.
ADCInput
1 L
totF
2
1FEF
2
1FEN
kT BW
tot ,inN
totN
FENΔ
3ADCIIP3 FEIIP
3 totIIP
FEG
MULTIANTENNA
ADCN
ADCD
FEDΔ
totD
1
1FEG
AnalogCombination
K
DigitalCombination
ADCOutput
K
FED
ADCI
o u tI
inI
inS
ADCS outS
ADCF
Fig. 6.12 Signal, noise and distortion power flow diagram of a multiplexing phased-array
84 6 Multiplexing Architecture, Non-ideal Behavior
Chapter 7Designs for the 30 GHz Components
In this chapter, the designs of the various components are reported, all for operation at30 GHz. The designs consist of LNA, multiplexer, mixer, clock generator, integrateddelay line, and power amplifier. Section 7.1 explains the design requirements for themultiplexing phased-array architecture. Sections 7.2 and 7.3 focus on LNA, multi-plexer, and mixer design. Moreover, sub-system performance including these threecomponents is reported. Section 7.4 is about the design of a clock generator whichprovides the switching signal. Section 7.5 discusses the delay line used to generatethe front-end input phase difference in the integrated system in Chap. 8. Section 7.6describes the switching power amplifier design. Section 7.7 concludes this chapter.
7.1 Design Requirements
The time multiplexing phased-array receiver uses a clock controlled multiplexer tocombine K paths into one. The combined path contains the signals from thevarious paths in different time slots. After down-conversion, band-pass filtering,and digitization, the time multiplexed signal is de-multiplexed by the synchronousclock to recover the original K signals in the digital domain. Then, the signals areprocessed by beam-forming algorithms. As this system differs from a conventionalreceiver system, besides the front-end gain, noise, as well as non-linearity per-formance, there are a few more parameters which need to be considered carefully.
• The multiplexer essentially incorporates a switch for each path which loads theLNA and drives the mixer. To minimize the influence to the LNA and mixerwhen changing of the switch status, the input (S11) and output (S22) matchingof the multiplexer should be maintained regardless of the switch status.
• In order to retain all amplitude and phase information from each antenna ele-ment up to the digital domain without mixing between each channel, the forward
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_7,� Springer Science+Business Media New York 2013
85
(S21) and reverse (S12) isolation of the multiplexer in an OFF (shut off) statusshould be designed to eliminate signals from other paths.
• To recover the signal from each path correctly in the digital domain, the samplingrate for each path (fS) must fulfill the Nyquist sampling theory: fS [ 2 BW, whereBW is the single-sided bandwidth of the incoming modulated signal. As a result,the multiplexer sampling rate fMUL can be expressed as: fMUL = K�fS [ 2 K�BW,which means that the incoming signal bandwidth is limited by the multiplexerswitching speed.
• The technology used for the design is the 0.25 lm SiGe BiCMOS process devel-oped by NXP semiconductors [69]. It provides HBT NPN transistors with fT/fmax upto 130/140 GHz, breakdown voltage of 2.0 V, measured at VBE = 0.65 V,moderate CCB, Rpinch = 3 kX/sq, RE = 2.5 X lm2, high trans conductance, andcompetitive low power-performance.
7.2 LNA and Multiplexer
7.2.1 Circuit Design
Design LNA using SiGe technology has been widely studied [70–74]. The dif-ferential LNA (as shown in Fig. 7.1) consists of a inductively degenerated cascadeQ1-Q2 and Q3-Q4, driving load inductors LC1-LC2. The cascaded LNA is
VCC
VinQ 1 Q 2
V o u t
6 m A
Q 3 Q 4
277pH 277pH
288pH
288pH188pH 188pH
L C 1 L C 2
LB1
LB2LE1 LE2
Q1-Q2:9.1µm/0.4µm
Q3-Q4:6.0µm/0.4µm
Fig. 7.1 Simplifiedschematic of a 30 GHz LNA
86 7 Designs for the 30 GHz Components
necessary to reduce the miller effect and feedback caused by Cmu, in order toincrease the power gain. Inductors LB1-LB2 and LE1-LE2 are selected togetherwith the emitter width of Q1-Q2 in order to realize noise and impedance matchingsimultaneously.
Emitter degeneration inductors LE1 and LE2 are used to to obtain Cin = C*opt,so that Cin and are Copt conjugated matched. The high impedance of the currentsource generates a virtual ground for them. Scaling the input transistor Q1-Q2(0.4 9 9.1 lm) brings the real part of the optimum source impedance for mini-mum noise figure close to 50 X at 30 GHz. The biasing voltage of Q1 and Q2 are2.2 V on the transistor base, in order to balance the output voltage swing and theremaining voltage headroom for the current source. Gyration of the emitterimpedance of LE1-LE2 in series with the base resistance of Q1-Q2 sets the realpart of the input impedance to 50 X thereby matching Re[Zin] in the desiredoperation range. The inductor LB1-LB2 connected in series with the base is madeseries resonant with the input loop to set the imaginary part of the input imped-ance. Inductors LC1-LC2 are selected as matching components to tune the LNAoutput and the following multiplexer input at 30 GHz.
The circuit implementation of the multiplexer is shown in Fig. 7.2. It consists ofparallel identical switches 1–4, with shared output load inductors LC3 & LC4. Theswitch uses current steering technique to minimize switching time. A differentialcommon-emitter stage, formed by transistor pair Q5-Q6, translates voltage intocurrent. The switching function is achieved by transistors Q7-Q10, where tran-sistor pair Q8-Q9 provide the core amplification element of the switch. Whencontrol voltage CO1 is high, Q8 & Q9 are biased in forward active region, and Q7& Q10 are in cut-off region, thus allowing the signal to pass from port 1 to 5.When CO1 is low, the bias current is steered toward transistors Q7 & Q10, whichconnects port 1 directly to the supply.
This topology inherently implements an absorptive switch. At input ports 1–4,it is ensured that the total current flow through the input transistors is alwaysconstant. At output port 5, the total current flow through the load inductors is alsoconstant. Hence, the source and load impedance of the low noise amplifier andmixer will remain constant regardless of the state of the switch.
Figure 7.3 shows the integrated die photo of the 30 GHz LNA and multiplexer.Note that RF input 2 is not power matched to the multiplexer. It is reserved forisolation measurement between each switch. The die area is 0.9 mm2 and theactive circuit occupies 0.2 mm2.
7.2.2 Measurements
Figure 7.4 shows the measurement setup for the 30 GHz LNA and multiplexer diedemonstrated in Fig. 7.3. The performance of the LNA-multiplexer combination ismeasured with switches of which the ON and OFF value can be varied with powersupply 2 and 3.
7.2 LNA and Multiplexer 87
Figure 7.5a and b show the S parameters of the circuit when the switch is in theON/OFF state, respectively. S11 and S22 remain constant regardless of the switchstatus. The transmission, measured by S21 is 14.4 dB in ON state and -9.3 dB inOFF state, which gives 23 dB of switch ON/OFF difference. Figure 7.5c shows acomparison between simulated and measured noise figure. The minimum mea-sured noise figure was 4.1 dB at 30 GHz. Figure 7.5d is IIP3 measurement, and theinput two tone frequencies are located at 29.950 and 30.050 GHz, respectively.
Q7 Q8 Q10Q9CO1
VCC
CO2
VCC
Switch1
Switch2
Port2
CO3 Switch3
Port3
CO4 Switch4
Port4
A
B
Q6Q5
6mA
Port1
188pH 188pH
Vout
LC3 LC4
Q5-Q10:6.0µm/0.4µm
Port5
Fig. 7.2 Simplifiedschematic of a 30 GHzmultiplexer
Fig. 7.3 Die photo of the30 GHz LNA andmultiplexer
88 7 Designs for the 30 GHz Components
Multiplexer
100
100
LNA
SignalGenerator
RFin30GHz
On-Chip
SpectrumAnalyzer 1
RFout30GHz
Powersupply 2
Powersupply 3
Switch-on3.3V
Switch-off2.9V
Powersupply 1
VCC3.3V
SpectrumAnalyzer 2
Fig. 7.4 Measurement setup of the 30 GHz LNA and multiplexer
Fig. 7.5 LNA-multiplexer measurement. a s-parameter when the switch is ON. b s-parameterwhen the switch is OFF. c Noise figure. d IIP3 measurement
7.2 LNA and Multiplexer 89
Hence the 3rd order intermodulation products are located at 29.850 and30.150 GHz, respectively. The measured IIP3 of the LNA multiplexer combinationis -10 dBm.
The measured isolation from switch 1 to switch 2 is 25.2 dB when switch 1 isON, and 28.7 dB when switch 1 is OFF. The power consumption is 44 mA, inwhich the LNA consumes 9 mA and the multiplexer consumes 35 mA.
7.3 LNA-Multiplexer-Mixer Combination
7.3.1 Circuit Design
The mixer design using SiGe technology has been presented extensively in theliteratures [75–80]. The mixer design is a double-balanced Gilbert cell as shown inFig. 7.6. It down-converts the RF signal at 30 GHz to the IF frequency of 10 GHz.Further down-conversion will be considered in a future design. The trans con-ductance part of the mixer Q11-Q12 interfaces with the multiplexer output byinductors LC3 & LC4 in Fig. 7.2, and it is optimized to achieve the highest powergain and the lowest noise figure simultaneously. The bias current density andtransistor size of the switching parts Q13-Q16 were chosen for the highest oper-ating speed to maximize the conversion gain. The emitter degeneration resistorsRE1-RE2 and the loading resistors RC1-RC2 are designed to trade-off the gain andthe linearity performance of the mixer. The DC biasing for the input transistorsQ11-Q12 is 1.7 V, and the DC biasing for the output transistors Q13-Q16 is 2.7 V.
Q13 Q14
VCC
Q16Q15
Vout
VinQ11 Q12
4mA
300Ohm 300Ohm
LO
RE1 RE2
RC1 RC2
Q11-Q12:2.5µm/0.4µm
Q13-Q16:1.0µm/0.4µm
Fig. 7.6 Simplifiedschematic of a 30 GHz mixer
90 7 Designs for the 30 GHz Components
Figure 7.7 shows the simplified schematic which combines the LNA, themultiplexer, the mixer and the inter-connections between them.
Figure 7.8 shows the integrated die photo of the above combined schematic.The die area is 0.9 mm2 and the active circuit occupies 0.2 mm2.
7.3.2 Measurements
Figure 7.9 shows the measurement setup for the 30 GHz LNA, multiplexer andmixer of the die that is demonstrated in Fig. 7.8. The performance of the LNA-multiplexer-mixer combination is measured with controllable switches imple-mented by power supply 2 and 3.
Q7 Q8 Q10Q9CO1
VCC
CO2
VCC
Switch1
Switch2
Port2
CO3 Switch3
Port3
CO4Switch4
Port4
A
B
Q6Q5
6mA
Port1
188pH 188pH
To MixerVCC
RF INQ1 Q2
6mA
Q3 Q4
277pH 277pH
288pH
288pH188pH 188pH
LC1 LC2
LB1
LB2LE1 LE2
Q13 Q14
VCC
Q16Q15
Mixer inQ11 Q12
4mA
300Ohm 300Ohm
LO
RE1 RE2
RC1 RC2
IF OUT
LC3 LC4
Port5
LNA Multiplexer Mixer
Fig. 7.7 Simplified schematic of the 30 GHz LNA, multiplexer, and mixer
Fig. 7.8 Die photo of the30 GHz LNA, multiplexer,and mixer
7.3 LNA-Multiplexer-Mixer Combination 91
The front-end measurement includes the LNA, the multiplexer, and the mixerwith controllable switches. To evaluate the linearity of the front-end, the input third-order intercept point (IIP3) were measured. Figure 7.10a shows the conversion gainof the front-end was measured with both ON/OFF switch situations as shown in. TheRF frequency was swept from 21 to 39 GHz with -33 dBm input power. Themeasured maximum conversion gain is 18.9 dB at 30 GHz, and the switch ON/OFFdifference is 23 dB, corresponding with the isolation measurement result in theprevious section. For the IIP3 measurement, two tones were applied to the RF input togenerate IF signals at 9.950 and 10.050 GHz. The third order intermodulation (IM3)products appear at 9.850 and 10.150 GHz, respectively. The results are shown inFig. 7.10b. The measured IIP3 of the circuit is -22 dBm. For input signal power of-45 dBm, it is sufficient to operate in a linear region.
Multiplexer
100
100
100
LNA
Mixer
SignalGenerator 1
RFin30GHz
On-Chip
SpectrumAnalyzer
IFout10GHz
SignalGenerator 2
LOin20GHz
Powersupply 2
Powersupply 3
Switch-on3.3V
Switch-off2.9V
Powersupply 1
VCC3.3V
Fig. 7.9 Measurement setupof the 30 GHz LNA,multiplexer, and mixer
Fig. 7.10 LNA-multiplexer-mixer measurement a conversion gain with switch ON/OFF status,b non-linearity IIP3
92 7 Designs for the 30 GHz Components
7.4 Clock Generator
7.4.1 Circuit Design
The timing clock generator converts the input clock into four non-overlappingpulses, the control signals CO1-CO4, each with 25 % duty cycle. The timingcircuit is driven by a sinusoidal input clock but its operation is digital, divided intwo parts: a modulus 4 counter and additional logic to obtain the four outputs.Table 7.1 represents the operation states of the timing circuit.
The modulus 4 counter is implemented as a two bit counter. The counting isdone in gray mode instead of binary. In this way, only one bit changes at thetransition between states. This is important in high-frequency operation because iteliminates overlapping and glitches on CO1-CO4 that might occur when theoutputs Q0 and Q1 have different switching speed. The circuit including themodulus 4 counters and additional logic is represented in Fig. 7.11.
The D-type flip-flops provide Q0 and Q1 outputs according to Table 7.1(D1 = Q0 and D0 = Q1/). The outputs CO1-CO4 are obtained by combining theflip-flop outputs Q1 and Q0 using only NOR gates.
CO1 ¼ Q1= � Q0= ¼ Q1þ Q0ð Þ=CO2 ¼ Q1= � Q0 ¼ Q1þ Q0=ð Þ=CO3 ¼ Q1 � Q0 ¼ Q1=þ Q0=ð Þ=CO4 ¼ Q1 � Q0= ¼ Q1=þ Q0ð Þ=
ð7:1Þ
The flip-flop and NOR gates use differential emitter-coupled logic (ECL), toaccommodate the differential control signals required to drive the four switchingcells. The external clock input is also made differential. Figure 7.12 shows thesimulated waveforms of the outputs CO1-CO4 connected to the switching input ofthe switch cells.
The simulations were performed with a 4 GHz input clock with differential100 X load. The peak to peak voltage swing on each output is larger than 600 mV,which is adequate to drive the switch well into ON/OFF state.
Figure 7.13 shows the photograph of the timing clock generator. The clockinput is at the left side while the other three sides are reserved for the three outputsCO1, CO3 and CO4. Output CO2 is internally matched to 100 X (see Fig. 7.14)due to limited number of spaces for bond-pad placement. The outputs also include
Table 7.1 Truth table operation of the timing circuit
Q1 Q0 CO1 CO2 CO3 CO4
0 0 1 0 0 00 1 0 1 0 01 1 0 0 1 01 0 0 0 0 1
7.4 Clock Generator 93
DC blocking capacitors for direct connection to the measurement setup. The diearea is 0.8 mm2 and the active circuit occupies 0.1 mm2.
7.4.2 Measurements
The output waveforms were measured with an Agilent MSO6104 oscilloscope. Thisoscilloscope has a bandwidth of 1 GHz which limits the maximum measurementfrequency, especially the rise time of the waveform (minimum of 0.35 ns).Figure 7.14 shows the measurement setup for the timing clock generator die shownin Fig. 7.13.
D1 Q1
Q1/
D0 Q0
Q0/
CO1
CO2
CO3
CO4
clk
Fig. 7.11 Timing clockgenerator circuit
0.0
-0.5
0.5
CO
1 [V
]
0.0
-0.5
0.5
CO
2 [V
]
0.0
-0.5
0.5
CO
3 [V
]
0.0
-0.5
0.5
CO
4 [V
]
1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.81.0 3.0
0.0
-0.4
0.4
Time [ns]
clk[
V]
Fig. 7.12 Simulated timingclock generator waveforms
94 7 Designs for the 30 GHz Components
Figure 7.15 shows the waveforms of the adjacent outputs CO3 and CO4 with aninput clock of 600 MHz. At the mean value of the waveforms (20 mV) there is nooverlapping. The rise time of the waveforms is close to 0.5 ns which is mainly dueto the oscilloscope. The operation range for this circuit is from 500 to 7 GHz.
Fig. 7.13 Die photo of thetiming clock generator
CO1
clk600MHz
D1 Q1
Q1/
D1 Q1
Q1/
On-Chip
CO2
CO3
CO4
100
Powersupply
VCC3.3V
SignalGenerator
Oscilloscope
Fig. 7.14 Measurementsetup of the timing clockgenerator
1 The input angle is fixed to 8.5�. The reason is firstly due to the limited probe number (systemimplementation in Chap. 8) and chip area, and secondly, satellite communication requiresviewing angle with in ±10�.
7.4 Clock Generator 95
Fig. 7.15 Waveforms of theadjacent outputs CO3 andCO4
(a)
(b)
(c)
(d)
200um
376umFig. 7.16 Transmission linestructures for generating26.6� electric phase shifting.a 376 lm. b 776 lm.c 1,176 lm. d 1,576 lm
96 7 Designs for the 30 GHz Components
7.5 Input Delay Line
7.5.1 Circuit Design
In order to test the phased-array performance, we need to generate phase shiftedinput signals for the four channels. Due to measurement equipment limitations, theinput phase shifts need to be generated on chip. Assuming a fixed incoming signal
Fig. 7.17 Transmission line structure. a Layout view. b Cross-section view
Table 7.2 Modeling parameters for the transmission lines
l c rS Z0 Loss Dt upH fF X X dB pS �
(a) 376 l 244 25 4 99 0.18 2.4 26.7(b) 776 l 495 50 8.2 99 0.36 4.75 53.8(c) 1,176 l 742 75 12.5 99.5 0.55 7.25 80.7(d) 1,576 l 989 100 16.6 99.5 0.74 9.7 107.5
7.5 Input Delay Line 97
angle of 8.5�,1 and adjacent antenna distance d = k/2, according to (2.30), thecorresponding electrical phase shift is 26.6�, and the corresponding time delay is2.4 ps. Figure 7.16 shows transmission line structures that can provide such a timedelay.
The built-up of the transmission line is shown in Fig. 7.17.The distance between the transmission lines is 5 lm, and the single transmission
line width is 5 lm. Table 7.2 shows the modeling parameters for the transmissionlines shown in Fig. 7.16.
Because we do not want to introduce extra phase difference besides the intendedones that were shown in Fig. 7.16, the distances from each transmission line-end tothe LNA input need to be equal for all channels. Structures in Fig. 7.18 have the samelength, and they are used in the system level layout to connect the transmission line-end to the LNA input with equal distance.
The distance between the transmission lines is 6 lm, and the single transmissionline width is 5 lm. Table 7.3 shows the modeling parameters for the transmissionlines shown in Fig. 7.18.
Figure 7.19 shows the test structure to monitor the accuracy of the modeling.All values are based on the simulated modeling parameters of the transmissionline.
(b)
(a) 138um
524um
262um
200um
Fig. 7.18 Transmission linestructures for equal distance toLNA input a type 1, b type 2
Table 7.3 Modeling parameters for the transmission lines
l c rS Z0 Loss Dt upH fF X X dB pS �
(a) Type 1 426 45 8.9 97 0.43 4.2 47.4(b) Type 2 427 43 7.1 99 0.31 4.2 46.5
98 7 Designs for the 30 GHz Components
The inductor pair LM1 and capacitor pair CM1 is designed to matchinput_1_4–100 X (differentially). Similarly, the inductor pair LM2 and capacitorpair CM2 is designed to match input_2_3–100 X (differentially). If the measure-ment agrees with this design, it means the transmission line model is correct.Figure 7.20 shows the integrated die photo of the transmission line test structure.
7.5.2 Measurements
Figure 7.21 shows the simulated and measured S11 results of the transmissionline test structure. The simulation result is built on the model listed in Table 7.2.
Input_1_4
160pH
250fF
376u
1576u
Type 2
50
Input_2_3
169pH
177fF
776u
1176u
Type 1
50
(a)
(b)
LM1
LM2
CM1
CM2
Fig. 7.19 Test structure for transmission line model. a Transmission line 376, 1,576 lm, andtype 1. b Transmission line 776, 1,176 lm, and type 2
Fig. 7.20 Die photo of thetransmission line teststructure
7.5 Input Delay Line 99
From this figure, we can see that the measured result is closely matched to thesimulated one. For example, at 30 GHz, the measured matching of 376, 1,576 lm,and type2 is -14 dB, and the measured matching of 776, 1,176 lm, and type1 is-17 dB. Both S11 are below -12 dB, hence the simulation model shown inTable 7.2 is accurate.
7.6 Power Amplifier
As explained in Chap. 1, although transmitter design is not the focus of this these,a switch controlled power amplifier is designed in this chapter for reference.
7.6.1 Circuit Design
Design power amplifier using SiGe technology has been widely studied [81–87].The simplified schematic of a 30 GHz class A power amplifier with switch con-trols, is shown in Fig. 7.22. The input of the power amplifier connects to a 100 X
Fig. 7.21 Transmission line test structure: simulation result of S11 from a input_1_4. b input_2_3.And measurement result of S11 from c input_1_4. d input_2_3
100 7 Designs for the 30 GHz Components
differential antenna, and the output matching network is designed through a large-signal load-line match to achieve large output power and high power efficiency.
The PA switch control uses the same mechanism as used in the multiplexerdesign. When the control voltage ‘Switch_on’ is higher than ‘Switch_off’, Q4 & Q5are biased in forward active region, and Q3 & Q6 are in cut-off region, thusallowing the signal to pass ‘Vin’ to ‘Vout’. When the control voltage ‘Switch_on’ islower than ‘Switch_off’, the bias current is steered toward transistors Q3 & Q6,which connects ‘Vin’ directly to the supply. To achieve an optimal power gainperformance, the emitter width of the bipolar transistor is chosen to be 20.7 lmand the DC current density is approximately 1 mA per lm-emitter-width. Togetherwith the output matching resistor of 20 X, in simulation, the power amplifierachieves an available gain of 16 dB and maximum output power of +20 dBm at30 GHz.
Q3 Q4
VCC
Q6Q5
Q1 Q2
Switch_off
Vin
143pH 143pH
Vout
108pH
Vbias
Switch_on
113pH
DCblock
250fF
0.2
DCblock
229fF
405pH
ACblock
Q1 – Q6: (20.7µm/0.4µm) X 6
0.2
250mA
20
A
Fig. 7.22 Simplified schematic of the 30 GHz power amplifier with switch controls
Fig. 7.23 Die photo of the30 GHz power amplifier
7.6 Power Amplifier 101
Figure 7.23 shows the die photo of the 30 GHz PA. The die area is 0.75 mm2
and the active circuit occupies 0.2 mm2.
7.6.2 Measurements
Figure 7.24 shows the measurement setup for the 30 GHz power amplifier. Theperformance of the PA is measured with switches that are controllable imple-mented by power supplies.
The measured spectrum with only DC biasing connected (without RF inputsignal) is shown in Fig. 7.25. The circuit is oscillating at frequency n*1.33 GHz. Itindicates that the PA bias loop is not stable.
PA
SignalGenerator
RFin30GHz On-Chip
SpectrumAnalyzer
RFout30GHz
Powersupply
Powersupply
Switch-on3.3V
Switch-off2.9V
Fig. 7.24 Measurementsetup of the 30 GHz poweramplifier
Fig. 7.25 Measured PA output spectrum
102 7 Designs for the 30 GHz Components
7.6.3 Trouble Shooting
To find the root cause of the PA instability, we first analyze the PA output stage. Aseparate PA output stage was available on die. It consists of input bond pads with
Fig. 7.26 Die photo of thepower amplifier output stageverification circuit
PAoutputstageTL TL
Port1 Port2
PA outputstage TL
Port1 Port2
Zin@30GHz: 29.3+j37.1
freq (29.50GHz to 30.50GHz)
S(1
,1)
S11Rawdata:
De-embeddeddata:
S11
freq (29.50GHz to 30.50GHz)
S(1
,1)
Zin@30GHz: 25-j4
Fig. 7.27 De-embedding PA output stage
2 Thanks to my colleague Yu Pei who helped to perform this simulation.
7.6 Power Amplifier 103
transmission lines, PA output stage, and output bond pads with transmission lines,as shown in Fig. 7.26.
With load, open, and short de-embedding structures of the bondpads withtransmission lines, we were able to characterize the loading resistance of the PAactive stage as shown in Fig. 7.27. The result shows that the output resistance is25 X. It is not exact 20 X as expected, but the impact of this difference is small.
Next, we checked the bias loop with momentum simulations in the followingsteps:2
• Transistor core cells are removed and pins are reserved for multilevel simulation.• Matrices of vias are merged for simulation to reduce meshes.• Circular shapes are replaced with rectangles to reduce meshes.• Resistors, MIM caps, and diodes are removed to reduce meshes.• Only necessary metal layers and VIAs are reserved for DC biasing, signal flow
and ground plane. We made sure that removing other layers will not influencethe circuit function.
• Removed elements are added to the schematic simulation.
The simplified layout for momentum simulation is shown in Fig. 7.28. Thesimulation schematic with Momentum cell and re-adding removed cells is shownin Fig. 7.29.
Fig. 7.28 Simplified layout for full EM (electromagnetic) momentum simulation
2 Thanks to my colleague Yu Pei who helped to perform this simulation.
104 7 Designs for the 30 GHz Components
The small signal simulation results of the above schematic are shown in Fig. 7.30.The results show that through the displayed frequency segment, the K factor
drops below 1 and the B1f factor drops below 0. It indicates that the PA is notunconditionally stable, and the reason is the non-optimized layout design byadding small base resistors (10 X) to transistor Q1 to Q6 in Fig. 7.22, we canimprove the PA stability as shown in Fig. 7.31.
The results show that through the displayed frequency segment, the K factorstays above 1 and the B1f factor stays above 0. It indicates that the PA is
Fig. 7.29 Simulation schematic with momentum cell and re-adding removed cells
Fig. 7.30 Small signal simulation results of the re-modeled PA a K factor, b B1f factor
7.6 Power Amplifier 105
unconditionally stable. In conclusion, for such a high power level circuit, only theEM simulation on the signal path is not sufficient. It is necessary to perform theEM simulation also including the biasing lines.
7.7 Conclusion
In this chapter, the various designs of 30 GHz components have been discussed. Itcomprises the LNA, the multiplexer, the mixer, the clock generator, the integrateddelay lines, and the power amplifier. The measurement of the PA shows unstablebehavior, and the root cause was found to be the non-optimized layout design.Simulation result shows that by adding small base resistors to the PA transistors,the un-stable problem can be avoided. The components will be connected toconstruct a time multiplexed phased-array receiver system in Chap. 8.
Fig. 7.31 Small signal simulation results of the re-modeled PA, adding small base resistorsa K factor, b B1f factor
106 7 Designs for the 30 GHz Components
Chapter 8System Integration and Verification
After demonstrating the 30 GHz components in the previous chapter, a fullyintegrated 30 GHz time multiplexed phased-array receiver in SiGe technology isintroduced in this chapter. Section 8.1 introduces a first integration of the system,in which only one channel is activated. Section 8.2 demonstrates an integratedsystem with four channels. The delay line explained from Chap. 7.5 is used togenerate fixed electronic phase shift of 26.6� which is equivalent to a spatiallyangle of 8.5�. Section 8.3 makes conclusions for this chapter.
8.1 System with One Channel
The time multiplexed phased-array receiver system with one activated channelincludes one LNA, the multiplexer, the mixer, and the clock generator. Note thatthe other three channels are internally terminated by 100 X resistors. The mea-surement setup of the system is shown in Fig. 8.1. The die photo of the fabricatedcircuit is shown in Fig. 8.2.
Figure 8.3 shows the input matching for the system with one channel activated.At 30 GHz, S11 is -30 dB.
Figure 8.4 shows the output spectrum of the mixer with a -38 dBm RF signalinput at 30 GHz, -5 dBm LO signal at 20 GHz, and -10 dBm clock signal at4 GHz (1 GHz clock for each channel). The output behaves as a switched 10 GHztone with 1 GHz sampling spacing and 25 % duty-cycle, confirmed by the theoryshown in Fig. 5.2.
Compared to a conventional receiver, the multiplexer with 25 % duty cyclereceives 1/4 of the input signal power, which gives another 12 dB drop for the 0thorder harmonic at 10 GHz (this drop will be compensated in the digital domain bycombining 4 paths together). Considering also the 3 dB loss in each cable, 4.7 dB
W. Deng et al., Time Multiplexed Beam-Forming with Space-Frequency Transformation,Analog Circuits and Signal Processing, DOI: 10.1007/978-1-4614-5046-7_8,� Springer Science+Business Media New York 2013
107
loss in each balun-probe setting and the conversion gain of 18.9 dB, the outputpower at 10 GHz can be calculated as
Multiplexer
100
100
100
LNA
Mixer
Signal Generator 1
RFin30GHz
On-Chip
SpectrumAnalyzer
IFout10GHz
Signal Generator 2
LOin20GHz
Clock generator
CLKin 4GHz
Power supply
VCC3.3V
Signal Generator 2
Fig. 8.1 Measurement setup of the system with one channel
Fig. 8.2 Die photo of thesystem with one channel
108 8 System Integration and Verification
�38 dBm|fflfflfflfflfflffl{zfflfflfflfflfflffl}
input power
�3 dB|fflffl{zfflffl}
cable loss
�4:7 dB|fflfflfflffl{zfflfflfflffl}
balun loss
þ18:9 dB|fflfflfflfflffl{zfflfflfflfflffl}
F�E gain
�12 dB|fflfflfflffl{zfflfflfflffl}
sampling loss
�4:7 dB|fflfflfflffl{zfflfflfflffl}
balun loss
�6 dB ¼ �49:5 dBm|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
cable lossð�2Þ
ð8:1Þ
Resulting in -49.5 dBm, which closely agrees to the value shown in marker 1(Fig. 8.4a).
8.2 System with Four Channels
With the successful design of the system with one channel and the demonstrateddelay lines introduced in Chap. 7.5, we can demonstrate the time multiplexedphased-array receiver system with four activated channels. The demonstrated
Fig. 8.3 Input matching for the system with one channel activated
Fig. 8.4 Measured one channel system output spectrum at IF, spectrum view a zoom in b zoomout. The output behaves as a switched 10 GHz tone with 1 GHz sampling spacing and 25 % duty-cycle
8.1 System with One Channel 109
system includes the delay lines, the LNA, the multiplexer, the mixer, and the clockgenerator.
8.2.1 Demonstration with One Input Signal
The system measurement includes the delay lines, the LNA, the multiplexer, themixer, and the clock generator. The measurement setup is shown in Fig. 8.5. Thedelay line explained from Chap. 7.5 is used to generate fixed electronic phase shiftof 26.6� which is equivalent to a spatial angle of 8.5�.
The die photo of the fabricated circuit is shown in Fig. 8.6. Note that the delaylines 376, 776, 1176, and 1576 um are used to make time delay, and the delay linestype 1 and type 2 are used to connect the line-ends with the LNA input with equalline distance.
Figure 8.7 shows the input matching of the system with four channels,including the delay lines. At 30 GHz, S11 is -21 dB.
Figure 8.8 shows the four channels system output spectrums at the mixer outputwith incoming signal angle of 8.5�. Figure 8.8a is the theoretical normalizedspectrum assuming ideal block components. Figure 8.8b is the simulated spectrumin Cadence with all blocks implemented in practice. Figures 8.8c and d are themeasured spectrums. The theoretical, simulated, and measured spectrums showgood agreement with each other. This confirms the theory explained in Chap. 5: thetime multiplexed phased-array architecture can achieve spatial domain to frequency
MultiplexerLNA
Mixer
Signal Generator 1
RFin30GHz
On-Chip
SpectrumAnalyzer
IFout10GHz
Signal Generator 2
LOin20GHz
Clock generator
CLKin 4GHz
Power supply
VCC3.3V
Signal Generator 2
376um
776um
1176um
1576um
Fig. 8.5 Measurement setup of system with four channels, incoming signal angle of 8.5�
110 8 System Integration and Verification
domain mapping. Moreover, with 8.5� spatial input, the major part of the energy isstored in the fundamental and ±1 harmonics. So in this case, an analog band-passfilter with a single sideband bandwidth larger than 1 GHz can successfully receivethis signal.
8.2.2 Demonstration with Two Input Signals
With a little change in the delay lines connections, we can make the systemdemonstrate two signal inputs. One signal comes from a spatial angle of 8.5�, andthe other signal comes from a spatial angle of -8.5�. The measurement setup is
Fig. 8.6 Die photo of thesystem with four channels,incoming signal angle of 8.5�
Fig. 8.7 Input matching forsystem with four channels,incoming signal angle of 8.5�
8.2 System with Four Channels 111
shown in Fig. 8.9. The spatial angle of 8.5� is generated from the following way ofconnections:
• The 376 um delay line is connected to the LNA 1 that opens at first.• The 776 um delay line is connected to the LNA 2 that opens at second.• The 1176 um delay line is connected to the LNA 3 that opens at third.• The 1576 um delay line is connected to the LNA 4 that opens at fourth.
The spatial angle of -8.5� is generated in the above way but with the oppositesequence:
• The 376 um delay line is connected to the LNA 4 that opens at first.• The 776 um delay line is connected to the LNA 3 that opens at second.• The 1176 um delay line is connected to the LNA 2 that opens at third.• The 1576 um delay line is connected to the LNA 1 that opens at fourth.
So connecting the 376 and 1576 um delay lines to LNA 1 and LNA 4 at thesame time; and connecting 776 and 1176 um delay lines to LNA 2 and LNA 3 atthe same time, we can generate two input signals from angle 8.5� and -8.5�.
Fig. 8.8 Four channels system output spectrums at IF, incoming signal angle of 8.5� a theoreticalb simulated c measured, zoom in d measured, zoom out
112 8 System Integration and Verification
The die photo of the fabricated circuit is shown in Fig. 8.10. Note that the delaylines 376, 776, 1176, and 1576 um are used to make time delay, and the delay linestype 1 and type 2 are used to connect line ends with LNA input with equal distance.
MultiplexerLNA
Mixer
Signal Generator 1
RFin30GHz
On-Chip
SpectrumAnalyzer
IFout10GHz
Signal Generator 2
LOin20GHz
Clock generator
CLKin 4GHz
Power supply
VCC3.3V
Signal Generator 2
376um
1576um
1176um
1576um
Fig. 8.9 Measurement setup of system with four channels, and two incoming signals, at angleof 8.5� and -8.5�
Fig. 8.10 Die photo of thesystem with four channels,and two incoming signals, atangle of 8.5� and -8.5�
8.2 System with Four Channels 113
Figure 8.11 shows the input matching of the system with four channels, includingthe delay lines. At 30 GHz, S11 is -20 dB.
Figure 8.12 shows the four channels system output spectrums at the mixeroutput with two incoming signals, at angle of 8.5� and -8.5�. Figure 8.12a is thetheoretical normalized spectrum assuming ideal block components. Figure 8.12bis the simulated spectrum in Cadence with all blocks implemented in practice.
Fig. 8.11 Input matching forsystem with four channels,two incoming signals angle of8.5� and -8.5�
Fig. 8.12 Four channels system output spectrums at IF, two incoming signals angle of 8.5� and-8.5� a theoretical b simulated c measured, zoom in d measured, zoom out
114 8 System Integration and Verification
Figures 8.12c and d are the measured spectrums. Also, with 8.5� and -8.5� spatialinputs, the major part of the energy is stored in the fundamental and ±1 harmonics.We can not separate these two input signals by the coarse filtering, because theyare symmetrical in space, and will give the same response. However, with finalspatial filtering in the digital domain, they can be separated. The simulated andmeasured spectrums have un-equal +1 and -1 harmonic amplitude, while the idealtheoretical spectrum has equal +1 and -1 harmonics amplitude. This is due to thenon-ideal delay lines and multiplexing switches. Comparing with Fig. 8.8, thefrequency spectrum pattern has changed due to incoming signal differences. Thisconfirms with the theory explained in Chap. 5.
8.3 Conclusion
In this chapter, we give three demonstrations of the time multiplexed phased-arrayreceiver. A system with one activated channel proves that the block componentsdesigned in Chap. 7 can be used to construct a working time multiplexing system.A system with four activated channels is demonstrated with two scenarios: onewith single fixed input signal from a spatial angle of 8.5�, and the other with twofixed input signals from spatial angles of 8.5� and -8.5�. These demonstrationsconfirm the theory explained in Chap. 5: the time multiplexed phased-arrayarchitecture can achieve spatial domain to frequency domain mapping. Moreover,with small angle of incidence (8.5�), the frequency spectrum energy is focused ona few major harmonics (fundamental, +1 and -1 harmonics). The core size of the4 channel system without area optimization is 1 by 1.2 mm, which is relativelysmall compare with conventional 4-channel phased-array systems.
8.2 System with Four Channels 115
Chapter 9Conclusions
This book provides a system approach analysis method for phased-array receivers.A single path receiver optimization method was studied first. A design flow fortrade-off between RF front-end and ADC block performance by translating ADCparameters into RF domain is introduced. This approach indicates two variables,DNFE and DDFE, for achieving optimum dynamic range in a receiver chain.Associating these variables to the power consumption enables the trade-offbetween RF and ADC block for minimum overall power consumption. After that,two types of multi-path receiver, namely, analog beam-forming and digital beam-forming are analyzed as a single chain receiver with their equivalent model. Itstarted with analyzing the difference between phased-array and single-chainreceivers from noise and linearity perspectives and the result indicates that for bothcases, the total noise figures are reduced due to non-correlated noise adding, andthe total IIP3 are increased due to interference cancellation. At last, this chapterprovided a general case of beam-forming analysis, and two parameters b1 and b2
are introduced to indicate the flexibility of the beam-forming. When K \ b1 \ K2
and 1 \ b2 \ K, the system is partly analog, and partly digital beam-forming. Onsystem design level, b1 and b2 can be used as another design dimension to performsystem optimization with various applications.
Two-step beam-forming using space-frequency transformation in a time-mul-tiplexed phased-array receiver has been introduced. This architecture can achievespatial domain to frequency domain mapping, and two steps of spatial filtering,namely coarse and final spatial filtering. These properties enable the possibility ofphased-array analog and digital co-design, and generalized phased-array systemdesign. Specifically, we have discussed the multiplexing architecture from amathematical point of view. We used various models to understand the propertiesof the system. Firstly, the properties of the analog combined signal were describedand a similarity with traditional phase modulation theory was explained. Secondly,a new coefficient function Dn was introduced to help understand the properties ofthe combined signal. Thirdly, we introduced a new concept: spatial to frequency
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transformation. Next, by processing the signals in the digital domain, the finalarray pattern was introduced. Furthermore, the array pattern was compared withthe traditional analog beam-forming array pattern and key system parameters havebeen revealed.
Furthermore, we have discussed a few important non-idealities of a multi-plexing phased-array architecture. To reduce the analog filter bandwidth, hence theADC bandwidth, we have introduced an actual viewing angle to the expectedviewing angle deviation. The smaller the band-pass filter bandwidth, the larger theangle deviation. This deviation can be compensated by creating a look-up table inthe digital domain, but the power loss due to narrow band filtering is not cor-rectable in digital domain. The channel isolation indicates the switching quality. Ifwe don’t have an infinite channel isolation, even with high filter bandwidth, theactual viewing angle still can not perfectly follow the expected viewing angle. Thechannel isolation indicates the switching quality. If the channel isolation is notinfinite, even with infinite filter bandwidth, the actual viewing angle still can notperfectly follow the expected viewing angle. To achieve the best signal to noiseratio improvement, the incoming noise bandwidth to signal bandwidth ratio shouldbe small. If the signal and noise bandwidth are the same, then for a four antennaarray, the SNR improvement is 6 dB, which is the same improvement as theconventional beam-forming. For suitable applications, the power flow diagram canbe used as a guideline to specify the block parameters. The system simulationresult shows that a multiplexing phased-array architecture can achieve spatial tofrequency mapping, and it is a good alternative for conventional phased-arrayarchitectures. Moreover, the simulation also shows that multiple sources (desiredsignal) selection is possible with this architecture.
At circuit level, the various designs of 30 GHz components have been dis-cussed. It comprises the LNA, the multiplexer, the mixer, the clock generator, theintegrated delay lines, and the power amplifier. The measurement of the PA showsunstable behavior, and the root cause was found to be the non-optimized layoutdesign. Simulation shows that by adding small base resistors to the PA transistors,the instability problem can be avoided. Furthermore, we have given three dem-onstrations of the time-multiplexed phased-array receiver. A system with oneactivated channel proves that the block components previously designed can beused to construct a working time multiplexing system. A system with four acti-vated channels has been demonstrated with two scenarios: one with single fixedinput signal from a spatial angle of 8.5�, and the other with two fixed input signalsfrom spatial angles of 8.5 and -8.5�. These demonstrations confirm the theoryexplained previously: the time-multiplexed phased-array architecture can achievespatial domain to frequency domain mapping. Moreover, with small angle ofincidence (8.5�), the frequency spectrum energy is focused on a few major har-monics (the fundamental, and the +1 and -1 harmonics). The core size of the 4channel system without area optimization is 1 mm by 1.2 mm, which is relativelysmall compare with conventional 4-channel phased-array systems.
This architecture is suitable for applications with limited viewing angle. With aband-pass filter at IF in front of the ADC in the analog domain, the suppressed
118 9 Conclusions
interference in both frequency and spatial domain can relax the ADC designcomplexity. Meanwhile, the preserved phase information is processed in digitaldomain for final array patterning and multiple source selection (if applicable).
9 Conclusions 119
Summary
This book is about the system analysis and design as well as circuit analysis anddesign of the time multiplexed phased-array receiver. This book provides systemapproaches to both single- and multi-path receivers. With single-path receiver, adesign flow for trade-off between RF front-end and ADC block performance bytranslating ADC parameters into RF domain is introduced. This approach indicatestwo variables for achieving optimum dynamic range in a receiver chain.Associating these variables to the power consumption enables the trade-offbetween RF and ADC block for minimum overall power consumption. After that,multi-path receivers, namely, phased-array receivers are presented. It starts withanalyzing the difference between phased-array and single-chain receivers fromnoise and linearity perspectives, and then provides a general analysis that takesadvantages of both analog and digital beam-forming. Two-step beam-formingusing space-frequency transformation in a time-multiplexed phased-array receiverhas been introduced. This architecture can achieve spatial domain to frequencydomain map-ping, and two steps of spatial filtering, namely coarse and final spatialfiltering. These properties enable the possibility of phased-array analog and digitalco-design, and generalized phased-array system design. Specifically, we havediscussed the multiplexing architecture from a mathematical point of view. Weused various models to understand the properties of the system. A new concept hasbeen introduced: spatial to frequency transformation. This architecture is suitablefor applications with limited viewing angle. With a band-pass filter at IF in front ofthe ADC in the analog domain, the suppressed interference in both frequency andspatial domain can relax the ADC design complexity. Meanwhile, the preservedphase information is processed in digital domain for final array patterning andmultiple source selection (if applicable). In order to verify the theory, thedemonstrators were implemented in block and system level with SiGe technology.The measurement results prove the new concepts that have been reported in thisbook.
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