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n 3 n 2 n 1 V DD LED3 LED2 LED1 LED1 LED2 LED3 D G S B n3 n2 n1 V DD M1 M2 M3 Fig.1a COEN 451 It is required to design a circuit which controls a bar display consisting of three LEDs as shown in Fig.1a. The operation of these LEDs is based on the level of the input signal: LED1 is ON when the input voltage reaches 0.5V LED1 and LED2 are both ON when the input signal reaches1.0 V. All LEDs are ON when the input signal reaches 1.5V. The circuit, which controls the display that consists of three transistors, each of a distinct threshold voltage as shown in Fig.1 b M1 is an NMOS transistor with a VTO=0.5V. M2 is the same type of transistor with a threshold voltage adjusted by an external voltage Ve. M3 is the same type transistor of M1 with a threshold voltage adjusted by an ion implantation process. a. Specify the threshold voltage of each of the transistors to achieve the required operation. b. Determine the value of the external voltage Ve. c. Determine the type and dose of the dopant so that the threshold voltage of M3 is adjusted from 0.5V to the required value. The transistors have the following parameters: tox =200A o , = 0.5 V 1/2 , s = -0.6V Maxime SCHNEIDER (ID: 6718809) Due date: September 24 th 2014 COEN 451 - Assignment 1

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COEN 451

Maxime SCHNEIDER (ID: 6718809)

Due date: September 24th 2014

COEN 451 - Assignment 1

It is required to design a circuit which controls a bar display consisting of three LEDs as shown in Fig.1a. The operation of these LEDs is based on the level of the input signal:

LED1 is ON when the input voltage reaches 0.5V

LED1 and LED2 are both ON when the input signal reaches1.0 V.

All LEDs are ON when the input signal reaches 1.5V.

The circuit, which controls the display that consists of three transistors, each of a distinct threshold voltage as shown in Fig.1 b

M1 is an NMOS transistor with a VTO=0.5V.

M2 is the same type of transistor with a threshold voltage adjusted by an external voltage Ve.

M3 is the same type transistor of M1 with a threshold voltage adjusted by an ion implantation process.

a. Specify the threshold voltage of each of the transistors to achieve the required operation.

b. Determine the value of the external voltage Ve.

c. Determine the type and dose of the dopant so that the threshold voltage of M3 is adjusted from 0.5V to the required value.

The transistors have the following parameters: tox =200Ao, = 0.5 V1/2, s = -0.6V

a /According to the wording, we have:

b /For transistor M2, we have:

N.A.

VSB = V

Since PN junctions have to be reversed biased, has to be positive to allow drain and source to work correctly. Therefore, = 2.55V.

Finally, we get

c /For transistor M3 we have:

Dopant is of p-type.

Since , other formula:

N.A.

Maxime SCHNEIDER (ID: 6718809)

Due date: October 1st 2014

COEN 451 - Assignment 2

Question 1

An nMOS transistor has a physical layout shown in Figure 1a. The transistor has the following device parameters:

Cox = 1.5fF/m2

n= 500cm2/V-sec

s = -0.6V

= 0.3V1/2

Cjsw = 0.7fF/m

CjB = 0.5fF/m2

= 0.015V-1

VTO = 1.0V

Note: 1division=1um

Figure 1a

a. Determine the following parasitic resistances and capacitances:

1. The transistor gate capacitance

2. The source (drain) capacitance

Note: Neglect the effect of the silicon outside the transistor area and metal line effect.

b. The above transistor is connected in a circuit with node voltages shown in Figure 1b.

Determine the channel resistance.

Figure 1b

Question 2

Determine the regime of operation for the transistors shown in Fig.2

Assume

VT0,N = - VT0,P = 0.8V

= 0.5 V1/2

sn = -sp = -0.6V

Fig.2

Question 1a /

Transistor gate capacitance is given by:

Area of the gate is .

So,

N. A.

Gate to drain capacitance is:

Area of the drain is

Perimeter of drain is

Thus,

N. A.

b /

BULK

DRAIN

GATE

SOURCE

This is a N-MOS transistor.

To determine the channel resistance, we first have to determine the operation region.

N. A.

=

N. A.

> transistor is ON.

N. A.

=

> Transistor is working in Saturation region.

In saturation region, Resistance is calculated as following:

with

N.A.

As is per and is expressed in

Question 2

Transistor (i)

so Transistor is OFF, in the cut-off region.

Transistor (ii)

Transistor is ON.

Transistor is in saturation mode.

Transistor (iii)

Transistor is ON.

Transistor is in linear region.

Transistor (iv)

Transistor is ON.

Transistor is in saturation mode.

Conclusion

Transistor

state

region

1 (NMOS)

1.218

1

OFF

Cut-off

2 (PMOS)

-1.045

-2.5

-2

-1.455

ON

Saturation

3 (PMOS)

-0.8

-3

-2

-2.2

ON

Linear

4 (NMOS)

0.937

1.5

4

0.63

ON

Saturation

APPENDIX A

Technology parameters of CMOSIS 5B

1. Specification of CMOSIS5, 0.5m technology

The model parameters of PMOS and NMOS transistor which should be used in your calculation are listed below.

Model cmos NMOS level3:

Vto=0.6566V, kn=196.47A/V2, n=546.2cm2/Vs,

Cox=3.6e-03F/m2, Cj=5.62e-04F/m2,

Cjsw=5.0e-12F/m2, Cjgate=5.0e-12F/m2,

Cgbo=4.0239e-10F/m2, Cgdo=3.0515e-10F/m2

Cgso=3.0515e-10F/m2

Model cmosp PMOS level3:

Vto=-0.9213V, kp=48.74A/V2, p=135.52cm2/Vs,

Cox=3.6e-03F/m2,

Cj=9.35e-04F/m2,

Cjsw=289.00e-12F/m2,

Cjgate=289.00e-12F/m2

Cgbo=3.7579e-10F/m2,

Cgdo=2.3922e-10F/m2

Cgso=2.3922e-10F/m2

VDD = 3.3 voltage

APPENDIX B

Cgaten=(W x L)n x Cox

Cgatep=(W x L)p x Cox

Cgd= Cgbo * 2L + Cgdo * W + Cgso * W

Cdbn, Cdbp are junction capacitance of present level

Cdb= Cj * Area + Cjsw * (W +2L) + Cjgate * W

Maxime SCHNEIDER (ID: 6718809)

Due date: October 15th 2014

COEN 451 - Assignment 3

A CMOS inverter shown above was designed using CMOSIS 5B technology. Process parameters are given in the appendix. The following design parameters were used in the design:

Ln = Lp = Lmin

Wn = 4 Lmin

Wp= 2Wn

VDD = 3.8 V

Determine, VIL,max, Vth, VOH,min and the Noise Margins high and Low of this inverter.

You may assume, LD, W and are all zero. Also you may assume that VOL,min= 0 and VOH,max=VDD.

Determination of

P-MOS is in linear region and N-MOS is saturated. Thus, leads to

(1)

For P-MOS: and

For N-MOS: and

Substituting in (1),

(2)

(3)

In this region II of inverter VTC: and

And from design parameters:

Substituting in (3),

(4)

From design parameters: and

And from CMOS 5B Datasheet,

N-MOS: and V

P-MOS: and V

Substituting in (2),

(5)

Substituting in (4),

(6)

Back-substituting (6) in (5),

Determination of

P-MOS and N-MOS are both saturated. Thus, leads to

(7)

For P-MOS: and

For N-MOS: and

Substituting in (7), and solving for ,

(8)

Since

From design parameters:

In our case (region III of VTC), is as it is where

Thus,

(9)

N.A.

Finally,

Determination of

P-MOS is saturated and N-MOS is in linear region. Thus, leads to

(10)

For P-MOS: and

For N-MOS: and

Substituting in (10),

(11)

(12)

In this region IV of inverter VTC: and

Substituting in (12),

(13)

From design parameters: and

And from CMOS 5B Datasheet,

N-MOS: and V

P-MOS: and V

Substituting in (13),

(14)

Substituting in (11),

(15)

Back-substituting (14) in (15),

Noise Margins High and Low

Noise Margin Low

=1.84 V

Noise Margin High

APPENDIX : CMOSIS 5 SPICE Parameters

*CMOSIS5 Design Kit V2.1 for Cadence Analog Artist

*MOS3 models for use in spectre

#ifdef n5bo

.MODEL CMOSN mos3 type=n

+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1

+VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E 04

+UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976

+NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 ETA=3.7180E-02

+KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10

+CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11

+MJSW=0.521 PB=0.99

+XW=4.108E-07

+CAPMOD=bsim XQC=0.5 XPART=0.5

*Weff = Wdrawn - Delta_W

*The suggested Delta_W is 4.1080E-07

.MODEL CMOSP mos3 type=p

+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1

+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5

+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673

+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02

+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10

+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10

MJSW=0.505 PB=0.99

+XW=3.622E-07

+CAPMOD=bsim XQC=0.5 XPART=0.5

*Weff = Wdrawn Delta_W

*The suggested Delta_W is 3.220E-07

#endif

Maxime SCHNEIDER (ID: 6718809)

Due date: October 22nd 2014

COEN 451 - Assignment 4

A CMOS inverter (INV1), with a physical layout shown in Fig.1, drives a similar inverter, and operates at a supply voltage of 3.3V.

a. Determine the delay of the inverter INV1.

b. What will be the maximum speed of operation of INV1 if it drives ten similar inverters?

c. One of the methods to speed up the operation is to increase the size of the driver. Determine the W/Ls of the PMOS and the NMOS transistors of INV1 so that the speed in part (b) is doubled, assuming that the supply voltage has been reduced by 10%. (Hint: Use twice the diffusion capacitance of Fig.1).

d. Determine the dynamic power dissipation of the inverter (INV1) for part c.

Use CMC technology parameters CMOSIS5B

Fig. 1 Inverter for design

a/ Delay of inverter

We have:

As a first step, we have to determine the Total Load Capacitance (), that is computed summing the Gate Capacitances, the Diffusion Capacitances and the Wire Capacitance:

Assumption: We ignore , the capacitance of the wire.

Diffusion Capacitances

Area of the drain is

Perimeter of drain is

Thus,

N.A.

For P-MOS,

and

For N-MOS,

and

F

Gate Capacitances

Assumption: We ignore and

As , we get:

N.A.

For P-MOS,

and

For N-MOS,

and

N.A.

As a second step, we have to determine and coefficients. In most cases, it is done doing SPICE simulations. Another way to calculate and can be done using the following formula for :

Knowing that , we get:

N.A.

And this formula for :

Knowing that , we get:

N.A.

Finally, we can calculate that is given by:

N.A.

b/

The maximum speed of operation is given by:

Since the circuits changes while using 10 inverters, changes: we now have to pass through 10 inverters and therefore Diffusion capacitances have to be taken into account ten times. This leads to:

So,

N.A.

and are computed using the following formulas:

where

where

N.A.

For rising time,

for falling time,

And finally,

c/

The maximum speed of operation is given by:

Hence,

Lets calculate .

Finally,

d/

Dynamic Power Dissipation is given by:

N.A.

Appendix B: SPICE Parameters

.MODEL CMOSN mos3 type=n

+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1

+VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E 04

+UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976

+NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 ETA=3.7180E-02

+KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10

+CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11

+MJSW=0.521 PB=0.99

+XW=4.108E-07

+CAPMOD=bsim XQC=0.5 XPART=0.5

*Weff = Wdrawn - Delta_W

*The suggested Delta_W is 4.1080E-07

.MODEL CMOSP mos3 type=p

+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1

+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5

+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673

+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02

+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10

+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10

MJSW=0.505 PB=0.99

+XW=3.622E-07

+CAPMOD=bsim XQC=0.5 XPART=0.5

*Weff = Wdrawn Delta_W

Maxime SCHNEIDER (ID: 6718809)

Due date: November 5th 2014

COEN 451 - Assignment 5

1. Design a 3 input CMOS static NAND gate for:

a) Minimum area;

b) Minimum propagation delay;

c) Equal rise and fall time;

d) Determine the worst-case rise and fall time if the NAND gate is driving a 0.1 pF load.

2. Design a gate to implement the function F (A, B, C, D) = (AB + CD) in Pseudo NMOS.

Analyze the circuit for valid operation at logic high and logic

Problem 1

a/ 3 input CMOS NAND for minimum area.

Parameters of Minimum Area CMOS are:

Thus, for a 3 input CMOS NAND with minimum area, we have:

b/ 3 input CMOS NAND for minimum propagation delay.

We have:

Equivalent inverter

3 input NAND

Thus, for a 3 input CMOS NAND with minimum area, we have:

Length is kept unchanged:

c/ 3 input CMOS NAND for equal rise and fall times.

To get equal and we need to have equal and .We have:

Equivalent inverter

3 input NAND

Thus, for a 3 input CMOS NAND with equal rise and fall times, we have:

Length is kept unchanged:

d/ Worst-case rise time and fall time with a 0.1 pF Load Capacitance.

Rise time

Worst-case rise time occurs when one input is LOW and the two others are HIGH, with top two NMOS at HIGH state.

Thus, to study worst-case rise time, we have:

A

B

C

OUT

1

1

0

1

We have:

Assuming that

Assuming that ,

Then, we have:

Fall time

Worst-case fall time occurs when the three inputs are HIGH, leading to LOW output state.

Thus, to study worst-case fall time, we have:

A

B

C

OUT

1

1

1

0

We have:

Assuming that

Assuming that ,

Then, we have:

Problem 2

(A, B, C, D) = (AB + CD)

Pseudo NMOS circuit

Equivalent inverter

Assuming:

we neglect

PMOS is saturated:

NMOS is linear:

As , we have,

We have:

Then,

Assuming

Smallest Width is . So we choose

And then

Finally, we get

Length is kept unchanged:

Use the following SPICE parameters for this assignment.

SPICE Transistor Parameters

Parameter

NMOS

PMOS

Units

Source

Description

VTO

KP

GAMMA

PHI

LAMBDA

RD

RS

CBD

CBS

IS

PB

CGSO

CGDO

CGBO

RSH

CJ

MJ

CJSW

MJSW

JS

TOX

NSUB

NSS

NFS

TPG

XJ

LD

UO

VMAX

0.7

40E-6

1.1

0.6

0.01

(40)

(40)

0.7

3.0E-10

3.0E-10

5.0E-10

25

4.4E-10

0.5

4.0E-10

0.3

1.0E-5

5.0E-8

1.7E16

0

0

1

6.0E-7

3.5E-7

775

1.0E5

-0.8

12E-6

0.6

0.6

0.03

(100)

(100)

0.6

2.5E-10

2.5E-10

5.0E-10

80

1.5E-4

0.6

4.0E-10

0.6

1.0E-5

5.0E-8

5.0E15

0

0

1

5.0E-7

2.5E-7

250

0.7E5

V

(A/V2)

(V0.5)

V

1/V

ohms

ohms

F

F

A

V

F/m

F/m

F/m

Ohms/sq.

(F/m2)

-

F/m

-

(A/m2)

m

(1/cm3)

(1/cm2)

(1/cm2)

-

m

m

(cm2/Vs)

(1)

(5)

(1)

(3)

(5)

(2)

(2)

(2)

(2)

(2)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(3)

(3)

(3)

(1)

(1)

(1)

(1)

-zero bias threshold voltage

-transconductance parameter

-bulk threshold parameter

-surface potential

-channel-length modulation

-drain ohmic resistance (w=6)

-source ohmic resistance()

-zero bias B-D juction cap.

-zero bias B-S juction cap.

-bulk junction sat.current

-bulk junction potential;

-G-S overlap capacitance

-G-D overlap capacitance

-G-bulk overlap capacitance

-diffusion sheet resistance

-zero bias bulk junction cap.

-bulk junction sidewall cap.

-bulk jinction sat.current

-oxide thickness

-substrate doping

-surface state density

-fast surface state density

-type of gate material

-metallurgical junction depth

-lateral diffusion

-surface mobility

-maximum drift velocity m/s

SPICE Level 3 Parameters

Parameter

NMOS

PMOS

Units

Source

Description

THETA

KAPPA

ETA

0.11

1.0

0.05

0.13

1.0

0.3

1/V

-

-

(1)

(1)

(1)

-mobility modulation

-saturation field factor

-static feedback

Other Electrical Parameters

Capacitance

(pF/m2)

Edge Component

(pF/m)

Source

Gate (Cox)

Metal1 Field

Metal1 Poly

Metal1 Diffusion

Poly Field

Metal2 Field

Metal2 Diffusion

Metal2 Poly

Metal2 Metal1

Capacitor P + - Poly

(0.1%/V linearity)

6.9E-4

2.7E-5

5.0E-5

5.0E-5

6.0E-5

1.4E-5

1.6E-5

2.0E-5

2.5E-5

6.9E-4

0.5E-4

0.4E-4

0.2E-4

2.0E-5

0.5E-4

(1)

(1)

(1)

(1)

(1)

(4)

(4)

(4)

(4)

(*)

(1)

Resistance

(ohms/sq.)

Source

N+ Diffusion

P+ Diffusion

N+ Poly

Capacitor P+

P-well

Metal1

Metal2

3 3 metal1 P + Diffusion Contact

3 3 metal1 N + Diffusion Contact

3 3 metal1 N + Poly Contact

25

80

18

300

4K

0.035

0.030

121

44

25

(1)

(1)

(5)

(1)

(1)

(4)

(4)

(5)

(5)

(5)

Maximum operating voltage: 5 volts.

Sources: (1) D. Smith of NTE, presented at CMC Workshop June 6-7, 1985.

Maxime SCHNEIDER (ID: 6718809)

Due date: November 19th 2014

COEN 451 - Assignment 6

1. The CMOS inverter shown in Figure 1a consists of two PMOS transistors connected in parallel and one NMOS transistor. All transistors (PMOS and NMOS) have the same dimensions with a layout shown in Figure 1b.(Note: the transistors are connected so that the output capacitance is minimized)

a. Determine the inverters switching voltage (Vx) and the supply current at Vo=Vx

b. Calculate the output capacitance.

c. If the inverter is driving a load equivalent to10 similar inverters, what will be the rise delay (tPLH)of the driving inverter?

d. During the implementation of the circuit, one of the PMOS transistors was accidentally disconnected, what will be the impact on the dc behavior of the circuit. In your analysis you need to address all critical parameters (VOH, VOL, VIH, VIL, Vx) and noise margin of the circuit. (Note: no calculations are required)

The transistors have the following parameters:

NMOS:

VTO=0.75V, Cox = 1.5fF/m2, Cjsw = 0.7fF/m, Cj=0.5fF/m2, n=500cm2/V-sec, =0. 0

PMOS:

VTO=-0.75V, Cox = 1.5fF/m2, Cjsw = 0.7fF/m, Cj=0.5fF/m2, p=250cm2/V-sec, =0. 0

Fig. 1

2. An engineer wishes to submit the layout shown in Fig. 2 for fabrication using N-well three- layer metal process:

a. Draw the vertical cross section B-B showing all layers and material involved.

b. List the sequence of steps up the formation of metal contacts required to fabricate the PMOS transistor in the targeted technology.

c. How many layers of metal appear in the layout of Fig. 2?

d. The engineer made four layout errors. Identify these errors

B

P+ Layer

N-well

Active

VDD

Contact

Active+

Via

Metal 2

Poly

Active

N+ Layer

Active

P+ Layer

Metal 1

VSS

B

Fig. 2

Question 1

a/

Inverters switching voltage is given by:

From the layout,

Two PMOS are in parallel so

then and

N.A.

Supply current at

At both NMOS and PMOS currents are opposite and in their saturation region. We have:

i.e. we have:

N.A.

b/ Output capacitance is calculated as following:

Assuming that

And knowing that

We finally get:

N.A.

c/

If the inverter is driving a load equivalent to10 similar inverters, load capacitance would be:

Since

and as we get

from previous question

We have:

N.A.

Rise delay is calculated as follows:

N.A

Question 2

a/

The vertical cross section B-B is the following:

As a reminder, classical inverted is as follows:

b/

Steps involved in the fabrication of a pMOS are:

1- Photolithography step to create N-well

2- Photolithography step to create thin oxide

3- Photolithography step to deposit Poly

4- Photolithography step to diffuse P+ Silicon creating active area

5- Photolithography step to deposit SiO2

6- Photolithography step to remove SiO2 where contacts are made open contact area

c/

There are two metal layers appearing in the layout of Fig. 2.

d/

Errors the engineer has made are:1- Via should be entirely on Metal 2

2- contact for nMOS bulk is missing

3- Gate extension for P transistor is missing

4- substrate connection to VDD should be n+

Maxime SCHNEIDER (ID: 6718809)

Due date: November 26th 2014

COEN 451 - Assignment 7

For the following exercises use CMOSIS5 parameters given in the class.

Exercise 1

Determine the capacitance of a 1mm metal1 wire with width of 0.6. Determine the ratio of the fringing capacitance to the parallel plate capacitance. Using the same process parameters determine the same ratio if the width was reduced to 0.3

Excersie 2

Determine the capacitance between 100 m length of metal_1 wire, width 4m and an equal dimension metal_2 wire placed directly above it.

Exercise 3

Estimate the delay of metal_1 wire having length of 1000m and width of 2

a) Use distributed rc method.

b) Use lumped RC method

c) Determine a relation between a & b above.

Exercise 4

Estimate the minimum width of metal_1 wire that can supply 30 mA of current. How many vias are required to connect this metal wire to metal_2 wire? What is the resistance presented by the via? You may assume Jm = 05mA/m2 , M_1 thickness is 0.5m and metal_2 thickness is o.6m. Assume each contact of 1um * 1um can carry 0.5mA safely or 0.1mA/um of periphery.

Exercise 5

A buffer Wn = 2 and Wp=6 is driving 100 long wire of metal_2, 4 wide. The metal_2 wire is feeding 8 Flip flops through 20 long metal_1 wire, width = 2. Each metal_1 wire is feeding gates of the flip flops through 10 long poly wire, 1 wide. Each flip flop gate has 10 fFcapacitance. Use CMOSIS5B parameters if needed.

a) Determine Cinterconnect,

b) Determine the rise and fall times if the input pulse has tr=tf= 0.05ns

Assume k=3.4 and area of drain =3W and perimeter of drain is 2W+6

Exercise 1

From the manual,

Since this is a single line, there is no line-to-line capacitance.

Wires capacitance is the sum of Fringing capacitance and Parallel plate capacitance:

Since

We have:

N.A.

Ratio is calculated as follows:

N.A.

If width is reduced to 0.3m, new ratio is

N.A.

Conclusion: the thiner the wire, the lower the ratio.

Exercise 2

From the manual,

Capacitance between the two metals is:

Since:

We have:

N.A.

Exercise 3

From CMOSIS5 parameters,

Since the wire is 1000 m long and 2m large, one square is 2 x 2m

=

a/

Distributed RC method Formula is

N.A.

b/

Lumped RC method Formula is:

Since

We have:

N.A.

c/

We have:

So, the ratio between these two values is:

Then,

Exercise 4

We have

However

Then,

N.A.

Furthermore, since each contact can carry 0.5mA, we need at least 60 contacts of x.

With 60 contact with a sheet resistance of for contact, we have

Exercise 5

a/

Interconnect Capacitances are the following:

Metal 1

L=100m

W= 4m

9.24

Metal 2

L=m

W=2m

18.88

Poly

L=m

W= 1m

Gates

b/

Since:

We have:

From the manual,

N.A.

Rise time Formula is:

Since

We have:

From the manual,

N.A.

Fall time Formula is:

Since

We have:

From the manual,

N.A.

For rise time and fall time:

Since:

We have:

N.A.

4V

2V

3V

0V

i.

4V

2V

1.5V

5V

ii.

2V

4V

1V

4V

iii.

1V

5V

2.5V

0.5V

iv.

Vin

Vin

Vin

Vo

2.5

Diffusion

Diffusion

Diffusion

5V

0.5

0.5

(n+ or p+)

(n+ or p+)

0.5

0.5

Polysilicon

n

3

n

2

n

1

V

DD

LED3

LED2

LED1

LED1

LED2LED3

V

e

D

G

S

B

S

in

n3n2n1

V

DD

M1M2

M3

Fig. 1a