f2mc -16lx - fujitsu€¦ · the top-level title at the top of a double spread indicates where you...

FUJITSU MICROELECTRONICS

CONTROLLER MANUAL

F2MCTM-16LX16-BIT MICROCONTROLLER

MB90495G SeriesHARDWARE MANUAL

CM44-10114-6E

FUJITSU MICROELECTRONICS LIMITED

F2MCTM-16LX16-BIT MICROCONTROLLER

MB90495G SeriesHARDWARE MANUAL

The information for microcontroller supports is shown in the following homepage.Be sure to refer to the "Check Sheet" for the latest cautions on development.

"Check Sheet" is seen at the following support page"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.

http://edevice.fujitsu.com/micom/en-support/

PREFACE

■ Manual Objectives and Readers

The MB90495G series is one of the general-purpose products in the F2MC-16LX family of 16-bit single-chip

microcontrollers that is developed by using an application-specific integrated circuit (ASIC).

This manual covers the functions and operations of the MB90495G series for engineers to develop LSIs

using this series.

■ Trademarks

F2MC is the abbreviation of FUJITSU Flexible Microcontroller.

Other system and product names in this manual are trademarks of respective companies or organizations.

The symbols TM and ® are sometimes omitted in this manual.

Copyright ©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.

• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presented solely for thepurpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSUMICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. Whenyou develop equipment incorporating the device based on such information, you must assume any responsibility arising out ofsuch use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out ofthe use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as licenseof the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSUMICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes noliability for any infringement of the intellectual property rights or other rights of third parties which would result from the use ofinformation contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for general use, includingwithout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developedand manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical lifesupport system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersiblerepeater and artificial satellite).Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims ordamages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from suchfailures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, andprevention of over-current levels and other abnormal operating conditions.

• Exportation/release of any products described in this document may require necessary procedures in accordance with theregulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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HOW TO READ THIS MANUAL

■ Page StructureEach section content can be read easily because it is mentioned within one page or double spread.

A summary under the title in each section outlines the section contents.

The top-level title at the top of a double spread indicates where you are reading without returning to the table

of contents or the chapter title page.

■ How to Find InformationTo find information in each section, use the following index in addition to general table of contents and

index.

● Register index

This index helps you find the page containing the explanation of the corresponding register from a register

name or related resource name. You can also check the mapped addresses on memory and reset values.

● Pin function index

This index helps you find the page containing the explanation or block diagram of the corresponding pin

from a pin number, pin name, or related resource name. You can also check the circuit types.

● Interrupt vector index

This index helps you find the page containing the explanation of a corresponding interrupt from a name of

resource generating the interrupt or an interrupt number. You can also check the names and addresses of

interrupt control registers (ICRs), and the interrupt vector addresses.

■ Representation of Register Name and Bit Name

● Representation of register name and bit name

Register name

By writing 1 to the sleep bit of the standby control register (STBC: SLP), .......

Bit nameAbbreviation of register name

Abbreviation of bit name

Disable the time-based timer for output of an interrupt request (TBTC: TBIE = 0).

Abbreviation of bit nameAbbreviation of register name

Set data

If an interrupt is enabled (CCR: I = 1), an interrupt can be accepted.

Abbreviation of bit nameAbbreviation of register name

Current state

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● Representation of dual-purpose pin

P41/SCK1 pin

Some pins are dual-purpose pins which functions can be switched by the setting of program. A slosh (/)

separates and represents the names corresponding to the functions of the dual-purpose pins.

■ Register Representation

The F2MC-16LX family is a CPU with a 16-bit bus width. The bit position of each control register and data

register is given in 16 bits.

In 16-bit registers, bits 15 to 8 are allocated to odd addresses and bits 7 to 0 even addresses.

Even in 8-bit registers, the position of bits allocated to odd addresses is given in bits 15 to 8.

The F2MC-16LX family enables access to 8-bit data in order to increase the efficiency of programs. So, if

odd-address registers are accessed in 8 bits, bits 7 to 0 in data correspond to bits 15 to 8 in the manual

representation.

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CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Features of MB90495G Series ........................................................................................................... 21.2 Product Lineup for MB90495G Series ................................................................................................ 51.3 Block Diagram of MB90495G Series .................................................................................................. 81.4 Pin Assignment ................................................................................................................................... 91.5 Package Dimension .......................................................................................................................... 111.6 Pin Description .................................................................................................................................. 131.7 I/O Circuit .......................................................................................................................................... 17

CHAPTER 2 HANDLING DEVICES ................................................................................ 192.1 Precautions when Handling Devices ................................................................................................ 20

CHAPTER 3 CPU ............................................................................................................ 253.1 Memory Space .................................................................................................................................. 26

3.1.1 Mapping of and Access to Memory Space .................................................................................. 283.1.2 Memory Map ................................................................................................................................ 303.1.3 Addressing ................................................................................................................................... 313.1.4 Linear Addressing ........................................................................................................................ 323.1.5 Bank Addressing ......................................................................................................................... 333.1.6 Allocation of Multi-byte Data on Memory ..................................................................................... 35

3.2 Dedicated Registers ......................................................................................................................... 373.2.1 Dedicated Registers and General-purpose Register ................................................................... 393.2.2 Accumulator (A) ........................................................................................................................... 403.2.3 Stack Pointer (USP, SSP) ........................................................................................................... 433.2.4 Processor Status (PS) ................................................................................................................. 46

3.2.4.1 Condition Code Register (PS:CCR) ......................................................................................... 473.2.4.2 Register Bank Pointer (PS:RP) ................................................................................................ 493.2.4.3 Interrupt Level Mask Register (PS:ILM) ................................................................................... 50

3.2.5 Program Counter (PC) ................................................................................................................. 513.2.6 Direct Page Register (DPR) ........................................................................................................ 523.2.7 Bank Register (PCB, DTB, USB, SSB, and ADB) ....................................................................... 53

3.3 General-purpose Register ................................................................................................................ 543.4 Prefix Codes ..................................................................................................................................... 56

3.4.1 Bank Select Prefix (PCB, DTB, ADB, and SPB) .......................................................................... 573.4.2 Common Register Bank Prefix (CMR) ......................................................................................... 593.4.3 Flag Change Inhibit Prefix (NCC) ................................................................................................ 603.4.4 Restrictions on Prefix Code ......................................................................................................... 61

3.5 Interrupt ............................................................................................................................................ 633.5.1 Interrupt Factor and Interrupt Vector ........................................................................................... 653.5.2 Interrupt Control Registers and Resources ................................................................................. 683.5.3 Interrupt Control Register (ICR00 to ICR15) ............................................................................... 703.5.4 Function of Interrupt Control Register ......................................................................................... 723.5.5 Hardware Interrupt ....................................................................................................................... 76

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3.5.6 Operation of Hardware Interrupt .................................................................................................. 793.5.7 Procedure for Use of Hardware Interrupt .................................................................................... 813.5.8 Multiple Interrupts ........................................................................................................................ 823.5.9 Software Interrupt ........................................................................................................................ 843.5.10 Interrupt by EI2OS ....................................................................................................................... 853.5.11 EI2OS Descriptor (ISD) ................................................................................................................ 873.5.12 Each Register of EI2OS Descriptor (ISD) .................................................................................... 893.5.13 Operation of EI2OS ...................................................................................................................... 923.5.14 Procedure for Use of EI2OS ........................................................................................................ 933.5.15 EI2OS Processing Time ............................................................................................................... 943.5.16 Exception Processing Interrupt .................................................................................................... 963.5.17 Time Required to Start Interrupt Processing ............................................................................... 973.5.18 Stack Operation for Interrupt Processing .................................................................................... 993.5.19 Program Example of Interrupt Processing ................................................................................. 100

3.6 Reset .............................................................................................................................................. 1043.6.1 Reset Factors and Oscillation Stabilization Wait Time .............................................................. 1063.6.2 External Reset Pin ..................................................................................................................... 1083.6.3 Reset Operation ........................................................................................................................ 1093.6.4 Reset Factor Bit ......................................................................................................................... 1113.6.5 State of Each Pin at Reset ........................................................................................................ 113

3.7 Clocks ............................................................................................................................................. 1143.7.1 Block Diagram of Clock Generation Section ............................................................................. 1163.7.2 Register in Clock Generation Section ........................................................................................ 1183.7.3 Clock Select Register (CKSCR) ................................................................................................ 1193.7.4 Clock Mode ................................................................................................................................ 1223.7.5 Oscillation Stabilization Wait Time ............................................................................................ 1263.7.6 Connection of Oscillator and External Clock ............................................................................. 127

3.8 Low-power Consumption Mode ...................................................................................................... 1283.8.1 Block Diagram of Low-power Consumption Circuit ................................................................... 1313.8.2 Registers for Setting Low-power Consumption Modes ............................................................. 1333.8.3 Low-power Consumption Mode Control Register (LPMCR) ...................................................... 1343.8.4 CPU Intermittent Operation Mode ............................................................................................. 1373.8.5 Standby Mode ........................................................................................................................... 138

3.8.5.1 Sleep Mode ............................................................................................................................ 1403.8.5.2 Watch mode ........................................................................................................................... 1423.8.5.3 Timebase Timer Mode ............................................................................................................ 1443.8.5.4 Stop Mode .............................................................................................................................. 146

3.8.6 State Transition in Standby Mode ............................................................................................. 1493.8.7 Pin State in Standby Mode, at Reset ......................................................................................... 1503.8.8 Precautions when Using Low-power Consumption Mode ......................................................... 153

3.9 CPU Mode ...................................................................................................................................... 1563.9.1 Mode Pins (MD2 to MD0) .......................................................................................................... 1583.9.2 Mode Data ................................................................................................................................. 1603.9.3 Memory Access Mode ............................................................................................................... 1623.9.4 Selection of Memory Access Mode ........................................................................................... 164

3.10 External Access .............................................................................................................................. 1653.10.1 External Bus Pins ...................................................................................................................... 167

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3.10.2 Registers used in External Access Mode .................................................................................. 1703.10.3 Bus Control Signal Select Register (ECSR) .............................................................................. 1713.10.4 Auto Ready Function Select Register (ARSR) .......................................................................... 1733.10.5 High Address Control Register (HACR) .................................................................................... 1753.10.6 Bus Sizing Function ................................................................................................................... 1773.10.7 Ready Function ......................................................................................................................... 1783.10.8 Hold Function ............................................................................................................................ 1823.10.9 External Access Timing ............................................................................................................. 184

CHAPTER 4 I/O PORT .................................................................................................. 1874.1 Overview of I/O Port ....................................................................................................................... 1884.2 Registers of I/O Port and Assignment of Pins Serving as External Bus ......................................... 1904.3 Port 0 .............................................................................................................................................. 192

4.3.1 Registers for Port 0 (PDR0, DDR0) ........................................................................................... 1944.3.2 Operation of Port 0 .................................................................................................................... 195

4.4 Port 1 .............................................................................................................................................. 1974.4.1 Registers for Port 1 (PDR1, DDR1) ........................................................................................... 1994.4.2 Operation of Port 1 .................................................................................................................... 200




4.8 Port 5 .............................................................................................................................................. 2194.8.1 Registers for Port 5 (PDR5, DDR5, ADER) ............................................................................... 2214.8.2 Operation of Port 5 .................................................................................................................... 223


CHAPTER 5 TIMEBASE TIMER ................................................................................... 2315.1 Overview of Timebase Timer .......................................................................................................... 2325.2 Block Diagram of Timebase Timer ................................................................................................. 2345.3 Configuration of Timebase Timer ................................................................................................... 236

5.3.1 Timebase Timer Control Register (TBTC) ................................................................................. 2375.4 Timebase Timer Interrupt ............................................................................................................... 2395.5 Explanation of Operation of Timebase Timer ................................................................................. 2405.6 Precautions when Using Timebase Timer ...................................................................................... 2445.7 Program Example of Timebase Timer ............................................................................................ 245

CHAPTER 6 WATCHDOG TIMER ................................................................................ 2476.1 Overview of Watchdog Timer ......................................................................................................... 2486.2 Configuration of Watchdog Timer ................................................................................................... 249

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6.3 Watchdog Timer Registers ............................................................................................................. 2516.3.1 Watchdog Timer Control Register (WDTC) ............................................................................... 252

6.4 Explanation of Operation of Watchdog Timer ................................................................................. 2546.5 Precautions when Using Watchdog Timer ...................................................................................... 2576.6 Program Examples of Watchdog Timer .......................................................................................... 258

CHAPTER 7 16-BIT INPUT/OUTPUT TIMER ............................................................... 2597.1 Overview of 16-bit Input/Output Timer ............................................................................................ 2607.2 Block Diagram of 16-bit Input/Output Timer ................................................................................... 261

7.2.1 Block Diagram of 16-bit Free-run Timer .................................................................................... 2627.2.2 Block Diagram of Input Capture ................................................................................................ 263

7.3 Configuration of 16-bit Input/Output Timer ..................................................................................... 2657.3.1 Timer Counter Control Status Register (TCCS) (High) .............................................................. 2687.3.2 Timer Counter Control Status Register (TCCS) (Low) .............................................................. 2697.3.3 Timer Counter Data Register (TCDT) ........................................................................................ 2717.3.4 Input Capture Control Status Registers (ICS01 and ICS23) ..................................................... 2727.3.5 Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3) ............................................................. 275

7.4 Interrupts of 16-bit Input/Output Timer ............................................................................................ 2767.5 Explanation of Operation of 16-bit Free-run Timer ......................................................................... 2777.6 Explanation of Operation of Input Capture ..................................................................................... 2797.7 Precautions when Using 16-bit Input/Output Timer ........................................................................ 2827.8 Program Example of 16-bit Input/Output Timer .............................................................................. 283

CHAPTER 8 16-BIT RELOAD TIMER ........................................................................... 2858.1 Overview of 16-bit Reload Timer .................................................................................................... 2868.2 Block Diagram of 16-bit Reload Timer ............................................................................................ 2888.3 Configuration of 16-bit Reload Timer .............................................................................................. 290

8.3.1 Timer Control Status Registers (High) (TMCSR0:H, TMCSR1:H) ............................................. 2938.3.2 Timer Control Status Registers (Low) (TMCSR0:L, TMCSR1:L) ............................................... 2958.3.3 16-bit Timer Registers (TMR0, TMR1) ...................................................................................... 2978.3.4 16-bit Reload Registers (TMRLR0, TMRLR1) ........................................................................... 298

8.4 Interrupts of 16-bit Reload Timer .................................................................................................... 2998.5 Explanation of Operation of 16-bit Reload Timer ............................................................................ 300

8.5.1 Operation in Internal Clock Mode .............................................................................................. 3028.5.2 Operation in Event Count Mode ................................................................................................ 307

8.6 Precautions when Using 16-bit Reload Timer ................................................................................ 3108.7 Program Example of 16-bit Reload Timer ...................................................................................... 311

CHAPTER 9 WATCH TIMER ........................................................................................ 3159.1 Overview of Watch Timer ............................................................................................................... 3169.2 Block Diagram of Watch Timer ....................................................................................................... 3189.3 Configuration of Watch Timer ......................................................................................................... 320

9.3.1 Watch Timer Control Register (WTC) ........................................................................................ 3219.4 Watch Timer Interrupt ..................................................................................................................... 3239.5 Explanation of Operation of Watch Timer ....................................................................................... 3249.6 Program Example of Watch Timer .................................................................................................. 326

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CHAPTER 10 8-/16-BIT PPG TIMER .............................................................................. 32710.1 Overview of 8-/16-bit PPG Timer .................................................................................................... 32810.2 Block Diagram of 8-/16-bit PPG Timer ........................................................................................... 331

10.2.1 Block Diagram for 8-/16-bit PPG Timer 0 .................................................................................. 33210.2.2 Block Diagram of 8-/16-bit PPG Timer 1 ................................................................................... 334

10.3 Configuration of 8-/16-bit PPG Timer ............................................................................................. 33610.3.1 PPG0 Operation Mode Control Register (PPGC0) .................................................................... 33810.3.2 PPG1 Operation Mode Control Register (PPGC1) .................................................................... 34010.3.3 PPG0/1 Count Clock Select Register (PPG01) ......................................................................... 34210.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) .......................................................... 344

10.4 Interrupts of 8-/16-bit PPG Timer .................................................................................................... 34510.5 Explanation of Operation of 8-/16-bit PPG Timer ........................................................................... 346

10.5.1 8-bit PPG Output 2-channel Independent Operation Mode ....................................................... 34710.5.2 16-bit PPG Output Operation Mode .......................................................................................... 34910.5.3 8+8-bit PPG Output Operation Mode ........................................................................................ 352

10.6 Precautions when Using 8-/16-bit PPG Timer ................................................................................ 355

CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE .................................. 35711.1 Overview of Delayed Interrupt Generation Module ......................................................................... 35811.2 Block Diagram of Delayed Interrupt Generation Module ................................................................ 35911.3 Configuration of Delayed Interrupt Generation Module .................................................................. 360

11.3.1 Delayed Interrupt Request Generate/Cancel Register (DIRR) .................................................. 36111.4 Explanation of Operation of Delayed Interrupt Generation Module ................................................ 36211.5 Precautions when Using Delayed Interrupt Generation Module ..................................................... 36311.6 Program Example of Delayed Interrupt Generation Module ........................................................... 364

CHAPTER 12 DTP/EXTERNAL INTERRUPT ................................................................. 36512.1 Overview of DTP/External Interrupt ................................................................................................ 36612.2 Block Diagram of DTP/External Interrupt ........................................................................................ 36712.3 Configuration of DTP/External Interrupt .......................................................................................... 369

12.3.1 DTP/External Interrupt Factor Register (EIRR) ......................................................................... 37012.3.2 DTP/External Interrupt Enable Register (ENIR) ........................................................................ 37112.3.3 Detection Level Setting Register (ELVR) (High) ........................................................................ 37212.3.4 Detection Level Setting Register (ELVR) (Low) ........................................................................ 373

12.4 Explanation of Operation of DTP/External Interrupt ....................................................................... 37412.4.1 External Interrupt Function ........................................................................................................ 37712.4.2 DTP Function ............................................................................................................................. 378

12.5 Precautions when Using DTP/External Interrupt ............................................................................ 37912.6 Program Example of DTP/External Interrupt Function ................................................................... 381

CHAPTER 13 8-/10-BIT A/D CONVERTER .................................................................... 38513.1 Overview of 8-/10-bit A/D Converter ............................................................................................... 38613.2 Block Diagram of 8-/10-bit A/D Converter ...................................................................................... 38713.3 Configuration of 8-/10-bit A/D Converter ........................................................................................ 390

13.3.1 A/D Control Status Register (High) (ADCS:H) ........................................................................... 39213.3.2 A/D Control Status Register (Low) (ADCS:L) ............................................................................ 39413.3.3 A/D Data Register (High) (ADCR:H) .......................................................................................... 397

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13.3.4 A/D Data Register (Low) (ADCR:L) ........................................................................................... 39913.3.5 Analog Input Enable Register (ADER) ...................................................................................... 400

13.4 Interrupt of 8-/10-bit A/D Converter ................................................................................................ 40213.5 Explanation of Operation of 8-/10-bit A/D Converter ...................................................................... 403

13.5.1 Single-shot Conversion Mode ................................................................................................... 40413.5.2 Continuous Conversion Mode ................................................................................................... 40613.5.3 Pause-conversion Mode ............................................................................................................ 40813.5.4 Conversion Using EI2OS Function ............................................................................................ 41013.5.5 A/D-converted Data Protection Function ................................................................................... 411

13.6 Precautions when Using 8-/10-bit A/D Converter ........................................................................... 413

CHAPTER 14 UART0 ...................................................................................................... 41514.1 Overview of UART0 ........................................................................................................................ 41614.2 Block Diagram of UART0 ................................................................................................................ 41814.3 Configuration of UART0 .................................................................................................................. 421

14.3.1 Serial Control Register 0 (SCR0) .............................................................................................. 42314.3.2 Serial Mode Register 0 (SMR0) ................................................................................................. 42514.3.3 Serial Status Register 0 (SSR0) ................................................................................................ 42714.3.4 Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0) .................. 42914.3.5 Communication Prescaler Control Register 0 (CDCR0) ............................................................ 43114.3.6 Serial Edge Select Register 0 (SES0) ....................................................................................... 432

14.4 Interrupt of UART0 .......................................................................................................................... 43314.4.1 Generation of Receive Interrupt and Timing of Flag Set ........................................................... 43514.4.2 Generation of Transmit Interrupt and Timing of Flag Set .......................................................... 437

14.5 Baud Rate of UART0 ...................................................................................................................... 43814.5.1 Baud Rate by Dedicated Baud Rate Generator ........................................................................ 44014.5.2 Baud Rate by Internal Timer 0 (16-bit Reload Timer) ................................................................ 44314.5.3 Baud Rate by External Clock ..................................................................................................... 445

14.6 Operation of UART0 ....................................................................................................................... 44614.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ...................................................... 44814.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) ..................................................... 45214.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) .......................................... 45514.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) ....................................... 457

14.7 Precautions when Using UART0 .................................................................................................... 460

CHAPTER 15 UART1 ...................................................................................................... 46115.1 Overview of UART1 ........................................................................................................................ 46215.2 Block Diagram of UART1 ................................................................................................................ 46415.3 Configuration of UART1 .................................................................................................................. 467

15.3.1 Serial Control Register 1 (SCR1) .............................................................................................. 46915.3.2 Serial Mode Register 1 (SMR1) ................................................................................................. 47115.3.3 Serial Status Register 1 (SSR1) ................................................................................................ 47315.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1) .................. 47515.3.5 Communication Prescaler Control Register 1 (CDCR1) ............................................................ 477

15.4 Interrupt of UART1 .......................................................................................................................... 47915.4.1 Generation of Receive Interrupt and Timing of Flag Set ........................................................... 48115.4.2 Generation of Transmit Interrupt and Timing of Flag Set .......................................................... 483

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15.5 Baud Rate of UART1 ...................................................................................................................... 48415.5.1 Baud Rate by Dedicated Baud Rate Generator ........................................................................ 48615.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) ................................................................... 48915.5.3 Baud Rate by External Clock ..................................................................................................... 491

15.6 Explanation of Operation of UART1 ............................................................................................... 49215.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ...................................................... 49415.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) ..................................................... 49815.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) .......................................... 50115.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) ....................................... 503

15.7 Precautions when Using UART1 .................................................................................................... 50615.8 Program Example for UART1 ......................................................................................................... 507

CHAPTER 16 CAN CONTROLLER ................................................................................ 50916.1 Overview of CAN Controller ............................................................................................................ 51016.2 Block Diagram of CAN Controller ................................................................................................... 51116.3 Configuration of CAN Controller ..................................................................................................... 515

16.3.1 Control Status Register (High) (CSR:H) .................................................................................... 51916.3.2 Control Status Register (Low) (CSR:L) ..................................................................................... 52116.3.3 Last Event Indicate Register (LEIR) .......................................................................................... 52416.3.4 Receive/Transmit Error Counter (RTEC) ................................................................................... 52616.3.5 Bit Timing Register (BTR) .......................................................................................................... 52816.3.6 Message Buffer Valid Register (BVALR) ................................................................................... 53216.3.7 IDE Register (IDER) .................................................................................................................. 53416.3.8 Transmission Request Register (TREQR) ................................................................................ 53616.3.9 Transmission RTR Register (TRTRR) ....................................................................................... 53816.3.10 Remote Frame Receiving Wait Register (RFWTR) ................................................................... 54016.3.11 Transmission Cancel Register (TCANR) ................................................................................... 54216.3.12 Transmission Complete Register (TCR) .................................................................................... 54416.3.13 Transmission Complete Interrupt Enable Register (TIER) ........................................................ 54616.3.14 Reception Complete Register (RCR) ........................................................................................ 54816.3.15 Reception RTR Register (RRTRR) ............................................................................................ 55016.3.16 Reception Overrun Register (ROVRR) ...................................................................................... 55216.3.17 Reception Complete Interrupt Enable Register (RIER) ............................................................. 55416.3.18 Acceptance Mask Select Register (AMSR) ............................................................................... 55616.3.19 Acceptance Mask Register (AMR) ............................................................................................ 55816.3.20 Message Buffers ........................................................................................................................ 56016.3.21 ID Register (IDRx, x = 7 to 0) .................................................................................................... 56116.3.22 DLC Register (DLCR) ................................................................................................................ 56416.3.23 Data Register (DTR) .................................................................................................................. 565

16.4 Interrupts of CAN Controller ........................................................................................................... 56616.5 Explanation of Operation of CAN Controller ................................................................................... 568

16.5.1 Transmission ............................................................................................................................. 56916.5.2 Reception .................................................................................................................................. 57216.5.3 Procedures for Transmitting and Receiving .............................................................................. 57616.5.4 Setting Multiple Message Receiving .......................................................................................... 583

16.6 Precautions when Using CAN Controller ........................................................................................ 58516.7 Program Example of CAN Controller .............................................................................................. 586

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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION ................................. 58917.1 Overview of Address Match Detection Function ............................................................................. 59017.2 Block Diagram of Address Match Detection Function .................................................................... 59117.3 Configuration of Address Match Detection Function ...................................................................... 592

17.3.1 Address Detection Control Register (PACSR) .......................................................................... 59317.3.2 Detect Address Setting Registers (PADR0 and PADR1) .......................................................... 595

17.4 Explanation of Operation of Address Match Detection Function .................................................... 59717.4.1 Example of using Address Match Detection Function ............................................................... 598

17.5 Program Example of Address Match Detection Function ............................................................... 603

CHAPTER 18 MIRRORING FUNCTION SELECT MODULE .......................................... 60518.1 Overview of ROM Mirroring Function Select Module ...................................................................... 60618.2 ROM Mirroring Function Select Register (ROMM) ......................................................................... 608

CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY ........................................................ 60919.1 Overview of 512 Kbit/1 Mbit Flash Memory .................................................................................... 61019.2 Registers and Sector Configuration of Flash Memory .................................................................... 61119.3 Flash Memory Control Status Register (FMCS) ............................................................................. 61219.4 How to Start Automatic Algorithm of Flash Memory ....................................................................... 61519.5 Check the Execution State of Automatic Algorithm ........................................................................ 617

19.5.1 Data Polling Flag (DQ7) ............................................................................................................ 61919.5.2 Toggle Bit Flag (DQ6) ................................................................................................................ 62119.5.3 Timing Limit Over Flag (DQ5) .................................................................................................... 62219.5.4 Sector Erase Timer Flag (DQ3) ................................................................................................. 62319.5.5 Toggle Bit 2 Flag (DQ2) ............................................................................................................. 624

19.6 Details of Programming/Erasing Flash Memory ............................................................................. 62619.6.1 Read/Reset State in Flash Memory ........................................................................................... 62719.6.2 Data programming to flash memory .......................................................................................... 62819.6.3 Data Erase from Flash Memory (Chip Erase) ........................................................................... 63019.6.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................ 63119.6.5 Sector Erase Suspension .......................................................................................................... 63319.6.6 Sector Erase Resumption .......................................................................................................... 634

19.7 Sample Program for 512 Kbit Flash Memory .................................................................................. 635

CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION ................................. 63920.1 Basic Configuration of Serial Programming Connection for F2MC-16LX MB90F497G/F498G ...... 64020.2 Connection Example in Single-chip Mode (User Power Supply) .................................................... 64320.3 Connection Example in Single-chip Mode (Writer Power Supply) .................................................. 64520.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply) ..... 64720.5 Example of Minimum Connection to Flash Microcontroller Programmer (Writer Power Supply) ... 649

APPENDIX ......................................................................................................................... 651APPENDIX A Instructions ........................................................................................................................... 652

A.1 Instruction Types ............................................................................................................................ 653A.2 Addressing ..................................................................................................................................... 654A.3 Direct Addressing ........................................................................................................................... 656A.4 Indirect Addressing ........................................................................................................................ 662

xii

A.5 Execution Cycle Count ................................................................................................................... 670A.6 Effective address Field ................................................................................................................... 673A.7 How to Read the Instruction List .................................................................................................... 674A.8 F2MC-16LX Instruction List ............................................................................................................ 677A.9 Instruction Map ............................................................................................................................... 691

APPENDIX B Register Index ...................................................................................................................... 713APPENDIX C Pin Function Index ............................................................................................................... 723APPENDIX D Interrupt Vector Index .......................................................................................................... 726

xiii

xv

Main changes in this edition

The vertical lines marked in the left side of the page show the changes.

Page Changes (For details, refer to main body.)

652 to 712 Changed the entire part of "APPENDIX A Instructions"

CHAPTER 1OVERVIEW

This chapter describes the features and basic specifications of the MB90495G series.

1.1 "Features of MB90495G Series"

1.2 "Product Lineup for MB90495G Series"

1.3 "Block Diagram of MB90495G Series"

1.4 "Pin Assignment"

1.5 "Package Dimension"

1.6 "Pin Description"

1.7 "I/O Circuit"

1

CHAPTER 1 OVERVIEW

1.1 Features of MB90495G Series

The MB90495G series is a general-purpose, high-performance 16-bit microcontroller designed for control of processors such as consumer products requiring high-speed real-time processing. This series has a full CAN interface and flash ROM.

The instruction system is based on the architecture of the F2MC family and provides additional high-level language instructions, extended addressing modes, enhanced multiply/divide instructions, and enriched bit processing instructions. A 32-bit accumulator enables long-word data (32 bits) processing.

■ Features of MB90495G Series

● Clock

• Built-in PLL clock multiplying circuit

• Machine clock (PLL clock) selectable from 1/2 frequency of oscillation clock or 1 to 4-multiplied

oscillation clock (4 MHz to 16 MHz when oscillation clock is 4 MHz)

• Subclock operation (8.192 kHz)

• Minimum instruction execution time: 62.5 ns (4-MHz oscillation clock, 4-multiplied PLL clock, and

VCC = 5.0 V)

● 16-MB CPU memory space

• Internal 24-bit addressing

• External access by selection between 18-bit and 16-bit bus widths (external bus mode)

● Instruction system optimized for controllers

• Various data types (bit, byte, word, long word)

• 23 types of addressing modes

• Enhanced signed instructions of multiplication/division and RETI

• High-accuracy operations enhanced by 32-bit accumulator

● Instruction system for high-level language (C language)/multitask

• System stack pointer

• Enhanced pointer indirect instructions

• Barrel shift instructions

● Higher execution speed

• 4-byte instruction queue

● Powerful interrupt function

• Powerful interrupt function with 8 levels and 34 factors

2

CHAPTER 1 OVERVIEW

● CPU-independent automatic data transfer function

• Extended intelligent I/O service (EI2OS): Maximum 16 channels

● Lower-power consumption (standby) modes

• Sleep mode (stops CPU clock)

• Timebase timer mode (operates only oscillation clock and subclock, timebase timer and watch timer)

• Watch mode (operates only subclock and watch timer)

• Stop mode (stops oscillation clock and subclock)

• CPU Intermittent operation mode

● Process

• CMOS Technology

● I/O ports

• General-purpose I/O ports (CMOS output): 49

● Timers

• Timebase timer, watch timer, watchdog timer: 1 channel

• 8/16-bit PPG timer: 8 bits × 4 channels or 16 bits × 2 channels

• 16-bit reload timer: 2 channels

• 16-bit I/O timer

- 16-bit free-run timer: 1 channel

- 16-bit input capture (ICU): 4 channels

By detecting the edge of the pin input, the count value of the 16-bit free-run timer is latched to generate an

interrupt request.

● CAN Controller: 1 channel

• Conforms to CAN Specification Ver. 2.0A and Ver. 2.0B.

• Built-in 8 message buffers

• Transfer rate: 10 Kbps to 1 Mbps (at 16-MHz machine clock frequency)

● UART0 (SCI) and UART1 (SCI): 2 channels

• Full-duplex double buffer

• Clock asynchronous or clock synchronous serial transfer

● DTP/external interrupt: 8 channels

• External input to start EI2OS and external interrupt generation module

● Delayed interrupt generation module

• Generates interrupt request for task switching

3

CHAPTER 1 OVERVIEW

● 8-/10-bit A/D converter: 8 channels

• 8-bit and 10-bit resolutions

• Start by external trigger input

• Conversion time: 6.13μs (including sampling time at 16-MHz machine clock frequency)

● Program patch function

• Detects address match for two address pointers

● Clock output function

4

CHAPTER 1 OVERVIEW

1.2 Product Lineup for MB90495G Series

The MB90495G series is available in four types. This section provides the product lineup, CPU, and resources.

■ Product Lineup for MB90495G Series

Table 1.2-1 Product Lineup for MB90495G Series

MB90V495G MB90F497G MB90497G MB90F498G

Classification Evaluation product Flash ROM Mask ROM Flash ROM

ROM Size -- 64 KB 128 KB

RAM Size 6 KB 2 KB

Process CMOS

Package PGA256 LQFP-64 (with 0.65-mm pin pitch),QFP-64 (with 1.00-mm pin pitch)

Operating supply voltage 4.5 V to 5.5 V

Power supply for emulator * Not provided --

*: Setting of DIP Switch (S2) when using emulation pod (MB2145-507). For details, refer to the MB2145-507 Hardware Manual (Section 2.7 Emulator-specific Power Supply).

5

CHAPTER 1 OVERVIEW

■ CPU and Resources for MB90495G Series

Table 1.2-2 CPU and Resources for MB90495G Series (1/2)


CPU Function Basic instruction count: 351Instruction bit length: 8 or 16 bitsInstruction length: 1 to 7 bytesData bit length: 1, 8, or 16 bits

Minimum instruction execution time: 62.5 ns (at 16-MHz machine clock frequency)

Interrupt processing time: 1.5 μs (at 16-MHz machine clock frequency)

Low-power consumption (standby) modes

Sleep mode, timer mode, timebase timer mode, stop mode, CPU intermittent operation mode

I/O Ports General-purpose I/O ports (CMOS output): 49

Timebase timer 18-bit free-run counterInterrupt cycle: 1.024, 4.096, 16.834, 131.072 ms

(at 4-MHz oscillation clock frequency)

Watchdog timer Reset cycle: 3.58, 14.33, 57.23, 458.75 ms (at 4-MHz oscillation clock frequency)

16-bit I/O timers 16-bit free-run timer

Channel count: 1Overflow interrupt

Input capture Channel count: 4Free-run timer values saved by pin input (rising edge, falling edge, both edges)

16-bit reload timer Channel count: 2Operation of 16-bit reload timerCount clock cycle: 0.25μs, 0.5μs, 2.0μs (at 16-MHz machine clock frequency)External event countable

Watch timer 15-bit free-run counterInterrupt cycle: 31.25, 62.5, 12, 250, 500 ms, and 1.0 s, 2.0 s (at 8.192-kHz subclock

frequency)

8-/16-bit PPG timer Channel count: 2 (operable with 8 bits x 2 channels)PPG operable with 8 bits x 2 channels or 16 bits x 1 channelPulse waveform output at arbitrary cycle and dutyCount clock: 62.5 ns to 1μs (at 16-MHz machine clock frequency)

Module for generating delayed interrupt generating module

Interrupt generation module for switching taskUsed for Real-time OS

DTP/external interrupt Input count: 8Start on rising or falling edges and by High- or Low-level inputs

External interrupts or (EI2OS)

6

CHAPTER 1 OVERVIEW

8-/10-bit A/D converter Channel count: 8Resolution: 10 or 8 bitsConversion time: 6.13μs (including sampling time at 16-MHz machine clock

frequency)Two or more continuous channels can be converted sequentially (up to 8 channels)Single conversion mode: Selected channel converted once onlyContinuous conversion mode: Selected channel converted continuouslyStop conversion mode: Selected channel converted and temporary stopped alternately

UART 0(SCI) Channel count: 1Clock synchronous transfer: 62.5 Kbps to 2 MbpsClock asynchronous transfer: 1,202 bps to 62,500 bpsTwo-way serial communication function, master/slave-connected communication

UART 1(SCI) Channel count: 2Clock synchronous transfer: 62.5 Kbps to 2 MbpsClock asynchronous transfer: 9,615 bps to 500KbpsTwo-way serial communication function, master/slave-connected communication

CAN Conforms to CAN Specification Ver. 2.0A and Ver. 2.0BTransmit/receive message buffer: 8Transfer bit rate: 10 Kbps to 1 Mbps (at 16-MHz machine clock)

Table 1.2-2 CPU and Resources for MB90495G Series (2/2)


7

CHAPTER 1 OVERVIEW

1.3 Block Diagram of MB90495G Series

Block diagram of the MB90495G series is shown in the figure below.

■ Block Diagram of MB90495G Series

Figure 1.3-1 Block Diagram of MB90495G Series

FRCK

IN0 to IN3RAM

Clock control circuit

Watch timer

CPUF2MC-16LX core

Time-base timer

ROM/FLASH

AD00 to AD15

INT0 to INT7

CLK

ALERD

A16 to A23

RXTX

WRLWRHHRQHAKRDY

PPG0 to PPG3

TIN0, TIN1

TOT0, TOT1

X0A,X1ARST

X0,X1

SCK1SOT1

SIN1

AVcc

AN0 to AN7

AVss

AVR

ADTG

SCK0SOT0

SIN0

UART1

Prescaler

Prescaler

UART0

8-/10-bitA/D converter

(8 ch)

CAN

DTP/external interrupt

16-bit reload timer(2 ch)

External bus

Inte

rnal

dat

a bu

s

16-bit free-run timer

16-bit PPG timer(2 ch)

Input capture(4 ch)

8

CHAPTER 1 OVERVIEW

1.4 Pin Assignment

Pin assignment of the MB90495G series is shown in the figure below.

■ Pin Assignment (FPT-64P-M06)

Figure 1.4-1 Pin Assignment (FPT-64P-M06)

P30

/SO

T0/

ALE

VS

S

P27

/INT

7/A

23P

26/IN

T6/

A22

P25

/INT

5/A

21P

24/IN

T4/

A20

P23

/TO

T1/

A19

P22

/TIN

1/A

18P

21/T

OT

0/A

17P

20/T

IN0/

A16

P17

/PP

G3/

AD

15P

16/P

PG

2/A

D14

P15

/PP

G1/

AD

13P

14/P

PG

0/A

D12

P13

/IN3/

AD

11P

12/IN

2/A

D10

P11

/IN1/

AD

09P

10/IN

0/A

D08

P07

/AD

07

P44/R

XP

61/INT

1P

62/INT

2P

50/AN

0P

51/AN

1P

52/AN

2P

53/AN

3P

54/AN

4P

55/AN

5P

56/AN

6P

57/AN

7A

VC

C

AV

RA

VS

S

P60/IN

T0

X0A

X1A

P63/IN

T3

MD

0

P06/AD06P05/AD05P04/AD04P03/AD03P02/AD02P01/AD01P00/AD00VSSX1X0MD2MD1RST

P31/SCK0/RDP32/SIN0/WRL

52

58

64

101 19

20

26

32

334251

P33/WRLP34/HRQP35/HAK

VCCC

P36/FRCK/RDYP37/ADTG/CLK

P40/SIN1P41/SCK1P42/SOT1

P43/TX

QFP-64FPT-64P-M06

9

CHAPTER 1 OVERVIEW

■ Pin Assignment (FPT-64-M09)

Figure 1.4-2 Pin Assignment (FPT-64P-M09)

P27

/INT

7/A

23P

26/IN

T6/

A22

P25

/INT

5/A

21P

24/IN

T4/

A20

P23

/TO

T1/

A19

P22

/TIN

1/A

18P

21/T

OT

0/A

17P

20/T

IN0/

A16

P17

/PP

G3/

AD

15P

16/P

PG

2/A

D14

P15

/PP

G1/

AD

13P

14/P

PG

0/A

D12

P13

/IN3/

AD

11P

12/IN

2/A

D10

P11

/IN1/

AD

09P

10/IN

0/A

D08

P50/A

N0

P51/A

N1

P52/A

N2

P53/A

N3

P54/A

N4

P55/A

N5

P56/A

N6

P57/A

N7

AV

CC

AV

RA

VS

S

P60/IN

T0

X0A

X1A

P61/IN

T1

P62/IN

T2

P07/AD07P06/AD06P05/AD05P04/AD04P03/AD03P02/AD02P01/AD01P00/AD00VSSX1X0MD2MD1RSTMD0P63/INT3

49

57

64

81 16

24

17

32

334048

VSSP30/SOT0/ALEP31/SCK0/RD

P32/SIN0/WRLP33/WRHP34/FRQP35/HAK

VCCC

P36/FRCK/RDYP37/ADTG/CLK

P40/SIN1P41/SCK1P42/SOT1

P43/TXP44/RX

LQFP-64FPT-64P-M09

10

CHAPTER 1 OVERVIEW

1.5 Package Dimension

The MB90495G series is available in two types of package.The package dimensions below are for reference only. Contact Fujitsu for the nominal package dimensions.

■ Package Dimension of FPT-64P-M06

64-pin plastic QFP Lead pitch 1.00 mm

Package width ×package length

14 × 20 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 3.35 mm MAX

Code(Reference)

P-QFP64-14×20-1.00

64-pin plastic QFP(FPT-64P-M06)

(FPT-64P-M06)

C 2003 FUJITSU LIMITED F64013S-c-5-5

0.20(.008) M

18.70±0.40(.736±.016)

14.00±0.20(.551±.008)

1.00(.039)

INDEX

0.10(.004)

1 1 9

20

3252

64

3351

20.00±0.20(.787±.008)

24.70±0.40(.972±.016)

0.42±0.08(.017±.003)

0.17±0.06(.007±.002)

0~8

1.20±0.20(.047±.008)

3.00+0.35–0.20

(Mounting height).118

+.014–.008

0.25+0.15–0.20

.010+.006–.008

(Stand off)

Details of "A" part

"A"0.10(.004)

*

*

Dimensions in mm (inches).Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

11

CHAPTER 1 OVERVIEW

■ Package Dimension of FPT-64P-M09

64-pin plastic LQFP Lead pitch 0.65 mm

Package width ×package length

12 × 12 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

Code(Reference)

P-LQFP64-12×12-0.65

64-pin plastic LQFP(FPT-64P-M09)

(FPT-64P-M09)

C 2003 FUJITSU LIMITED F64018S-c-3-5

0.65(.026)

0.10(.004)

1 1 6

17

3249

64

3348

12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

INDEX

0.32±0.05(.013±.002)

M0.13(.005)

0.145±0.055(.0057±.0022)

"A"

.059 –.004+.008

–0.10+0.20

1.50

0~8%

0.25(.010)

(Mounting height)

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.10±0.10(.004±.004)

Details of "A" part

(Stand off)

0.10(.004)

*

Dimensions in mm (inches).Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.

12

CHAPTER 1 OVERVIEW

1.6 Pin Description

This section describes the I/O pins and their functions of the MB90495G series.

■ Pin Description

Table 1.6-1 Pin Description (1/4)

Pin No.Pin Name

Circuit Type

FunctionM06 M09

2 1P61

DGeneral-purpose I/O port

INT1 External interrupt input pin. This pin should be set to "input port".

3 2P62



4 to 11 3 to 10

P50 to P57

E

General-purpose I/O port

AN0 to AN7Analog input pin for A/D converter. These pins work when the analog input is set to "enable."

12 11 AVCC -- VCC power input pin for A/D converter

13 12 AVR --Power (Vref+) input pin for A/D converter. The power supply should not be input exceeding

14 13 AVSS -- VSS power input pin for A/D converter

15 14P60



16 15 X0A ALow-speed oscillation pin. This pin should be pulled down when not connected to the oscillator.

17 16 X1A ALow-speed oscillation pin. This pin should be left open when not connected to the oscillator.

18 17P63



19 18 MD0 C Input pin for selecting operation mode

20 19 RST B Input pin for external reset

21 20 MD1 C Input pin for selecting operation mode

22 21 MD2 F Input pin for selecting operation mode

23 22 X0 A High-speed oscillation pin

24 23 X1 A High-speed oscillation pin

25 24 VSS -- Power (0 V) input pin

13

CHAPTER 1 OVERVIEW

26 to 33 25 to 32

P00 to P07

D

General-purpose I/O portsThese ports are enabled only in the single-chip mode.

AD00 to AD07

External address and data bus lower 8-bit I/O pin. These pins are enabled only in the external bus mode.

34 to 37 33 to 36

P10 to P13

D

General-purpose I/O ports. These ports are enabled only in the single-chip mode.

IN0 to IN3Trigger input pins for input capture channels 0 to 3. These pins should be set to "input port".

AD08 to AD11

I/O pins for upper 4 bits of external address bus and data bus. These pins are enabled only in the external bus mode.

38 to 41 37 to 40

P14 to P17

D

General-purpose I/O ports. These ports are enabled only in the single-chip mode.

PPG0 to PPG3Output pins for PPG timers 01 and 23. These pins are enabled when the output setting is "enabled."

AD12 to AD15

I/O pins for upper 4 bits of external address bus and data bus. These pins are enabled only in the external bus mode.

42 41

P20

D

General-purpose I/O port. If the corresponding bit of the high address control register (HACR) is 1 in external bus mode, this pin functions as a general-purpose I/O port.

TIN0 Event input pin for reload timer 0. This pin should be set to "input port."

A16Output pin for external address bus (A16). In external bus mode, they are only enabled if the corresponding bit of the high address control register (HACR) is 0.

43 42

P21

D


TOT0Event output pin for reload timer 0. This pin is enabled only when the output setting is "enabled".


44 43

P22

D


TIN1 Event input pin for reload timer 1. This pin should be set to "input port."



Pin No.Pin Name

Circuit Type

FunctionM06 M09

14

CHAPTER 1 OVERVIEW

45 44

P23

D


TOT1Event output pin for reload timer 1. This pin is enabled only when the output setting is "enabled".


46 to 49 45 to 48

P24 to P27

D

General-purpose I/O port. If the corresponding bit of the high address control register (HACR) is 1 in external bus mode, these pins functions as a general-purpose I/O port.

INT4 to INT7 External interrupt input pins. These pins should be set to "input port."

A20 to A23Output pins for external address buses (A20 to A23). In external bus mode, they are only enabled if the corresponding bit of the high address control register (HACR) is 0.

50 49 VSS Power (0 V) input pin.

51 50

P30

D

General-purpose I/O port. This port is enabled only the single-chip mode.

SOT0Serial data output pin for UART0. This pin is enabled only when the serial data output setting of the UART0 is "enabled".

ALEAddress latch enable output pin. This pin is enabled only in the external bus mode.

52 51

P31

D

General-purpose I/O port. This port is enabled only in the single-chip mode.

SCK0Serial clock I/O pin for UART0. This pin functions only when the serial clock I/O setting of the UART0 is "enabled".

RDRead strobe output pin. This pin is enabled only in the external bus mode.

53 52

P32

D

General-purpose I/O port.

SIN0 Serial data input pin for UART0. This pin should be set to "input port".

WRLWrite strobe output pin for lower 8 bits of data bus. This pin is enabled only in the external bus mode and when the WRL pin output is "enabled".

54 53

P33

D


WRHWrite strobe output pin for higher 8 bits of data bus. This pin is enabled only in the external bus mode, the 16-bit bus mode, and when the WRH pin output is enabled.

55 54

P34

D


HRQHold request input pin. This pin functions only in the external bus mode and when the hold input/output is "enabled".


Pin No.Pin Name

Circuit Type

FunctionM06 M09

15

CHAPTER 1 OVERVIEW

56 55

P35

D


HAKHold acknowledge output pin. This pin is enabled only in the external bus mode and when the hold input/output is "enabled".

57 56 VCC Power (5 V) input pin.

58 57 CCapacity pin for stabilizing power supply. This pin should be connected to a ceramic capacitor of approx. 0.1μF.

59 58

P36

D


FRCKExternal clock input pin for 16-bit free-run timer. This pin should be set to "input port."

RDYExternal ready input pin. This pin is enabled only in the external bus mode and when the external ready input is "enabled".

60 59

P37

D


ADTGExternal trigger input pin for A/D converter. This pin should be set to "input port".

CLKExternal clock output pin. This pin is enabled only in the external bus mode and when the external clock output is "enabled".

61 60P40


SIN1 Serial data input pin for UART1. This pin should be set to "input port."

62 61

P41

D


SCK1Serial data input pin for UART1. This pin is enabled only when the serial clock I/O setting of the UART1 is "enabled."

63 62

P42

D


SOT1Serial data I/O pin for UART1. This pin functions only when the serial data I/O setting of the UART1 is "enabled".

64 63

P43

D


TXCAN transmission output pin. This pin is enabled only when the output setting is "enabled".

1 64P44

DGeneral-purpose I/O port.

RX CAN reception input pin. This pin should be set to "input port."


Pin No.Pin Name

Circuit Type

FunctionM06 M09

16

CHAPTER 1 OVERVIEW

1.7 I/O Circuit

I/O circuit of the MB90495G series is shown in the figure below.

■ I/O Circuit

Table 1.7-1 I/O Circuit (1/2)

Classification Circuit Remark

A • Approximately 1 MΩ high speed oscillation feedback resistor.

• Oscillation feedback resistor for low speed approximately 10 MΩ

B

C • Hysteresis input

D • CMOS hysteresis input• CMOS-level output• Standby control provided

E • CMOS hysteresis input• CMOS-level output• Also used as analog input pin• Standby control provided

X1

X1AX0

X0A

Clock input

Standby mode control signal

R

Vcc

RHysteresis input

RHysteresis input

IOL = 4 mA

R

P ch

N ch

Vcc

Vss

Hysteresis input

Digital output

Digital output

Standby mode control

IOL = 4 mAR

P ch

N ch

Vcc

Vss

Hysteresis input

Analog input

Digital output

Digital output

Standby mode control

17

CHAPTER 1 OVERVIEW

F • The pull-down resistor is optional.

Table 1.7-1 I/O Circuit (2/2)

Classification Circuit Remark

Vss

R

RHysteresis input

18

CHAPTER 2HANDLING DEVICES

This chapter describes the precautions when handling general-purpose one chip micro-controller.

2.1 "Precautions when Handling Devices"

19

CHAPTER 2 HANDLING DEVICES

2.1 Precautions when Handling Devices

This section describes the precautions against the power supply voltage of the device and processing of pin.

■ Precautions when Handling Devices

● Voltage not exceeding maximum ratings (preventing latch-up)

• For a CMOS IC, latch-up may occur when a voltage higher than VCC or a voltage lower than VSS is

impressed to the I/O pin other than medium-/high-voltage withstand I/O pins, or when a voltage that

exceeds the rated voltage is impressed between VCC and VSS.

• Latch-up may cause a sudden increase in supply current, resulting in thermal damage to the device.

Therefore, the maximum voltage ratings must not be exceeded.

• When turning the analog power supply on and off, the analog supply voltage (AVCC and AVR) and the

analog input voltage should not exceed the digital supply voltage (VCC).

● Handling not-used pins

If unused input pins remain open, a malfunction or latch-up may cause permanent damage, so take

countermeasures such as pull-up or pull-down using a 2 kΩ or larger resistor.

● Precautions of using external clock

When an external clock is used, drive only the X0 pin and open the X1 pin. Figure 2.1-1 "Example of

Using External Clock" shows an use example of external clock.

Figure 2.1-1 Example of Using External Clock

● Precautions of non-use of subclock

If an oscillator is not connected to the X0A and X1A pins, connect the X0A pin to Pull-down resistor and

leave the X1A pin open.

● Precautions during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit

even when there is no external oscillator or external clock input is stopped. Performance of this operation,

however, cannot be guaranteed.

OpenMB90495G series

X1

X0

20


● Power pins

• When plural VCC pins and VSS pins are provided, pins designed to be at the same electric potential are

internally connected to the device to prevent malfunctions such as latch-up. However, always connect

all same electric potential pins to power supply and ground outside the device to prevent decrease of

unnecessary radiation, the malfunction of the strobe signal due to a rise of ground level, and follow the

standards of total output current.

• The power pins should be connected to VCC and VSS of the MB90495G series device at the lowest

possible impedance from the current supply source.

• It is best to connect approximately 0.1μF capacitor between VCC and VSS as a bypass capacitor near the

pins of the MB90495G series device.

● Crystal oscillator circuit

• Noise near the X0 and X1 pins may cause the MB90495G series to malfunction. Design the PC board sothat the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor to ground are as

close as possible to each other, and so the wiring of the X0 and X1 pins and other wiring do not cross.

• For stable operation, the PC board is recommended to have the artwork with the X0 and X1 pins

enclosed by a ground line.

● Procedure of A/D converter/analog input power-on

• Always apply a power to the A/D converter power and the analog input (AN0 to AN7 pins) after or

concurrently with the digital power (VCC)-on.

• Always turn off the A/D converter power and the analog input before or concurrently with the digital

power-down.

• Note that AVR should not exceed AVCC at turn on or off. (The analog power and digital power can be

simultaneously turned on or off with no problem.)

● Handling pins when not using A/D converter

When not using the A/D converter, the pins should be connected so that AVCC = AVR = VCC and AVSS =

VSS.

● Precautions at power on

To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on should be

50 μs or more (between 0.2 V and 2.7 V).

● Initialization

The device has internal registers that are initialized only by a power-on reset. When initializing the device,

the power supply should be turned off and turn on again.

● Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the specified VCCsupply voltage operating range. Therefore, the VCC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values)

21


at commercial frequencies (50 to 60 Hz) fall below 10% of the standard VCC supply voltage and the

coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

● Undefined signal output from ports 0 and 1

If the RST pin is High during the stabilization waiting time (power-on reset) of the step-down circuit after

the power is turned on, undefined signals are output from ports 0 and 1. If the RST pin is Low, ports 0 and

1 enter the high-impedance state. Figure 2.1-2 "Timing Chart for Ports 0 and 1 to Output Undefined Signals

(RST Pin High)" and Figure 2.1-3 "Timing Chart for Ports 0 and 1 to Enter High-impedance State (RST

Pin Low)" show the timing of ports 0 and 1 producing outputs and entering the high-impedance state,

respectively.

Figure 2.1-2 Timing Chart for Ports 0 and 1 to Output Undefined Signals (RST Pin High)

Stabilization waiting time*2

Stabilization waiting time of step-down circuit*1

VCC (Power supply pins)

PONR (Power-on reset) signal

RST (External asynchronous reset) signal

RST (Internal reset) signal

Oscillation clock signal

KA (Internal operation clock A) signal

KB (Internal operation clock B) signal

PORT (Port output) signal

*1: Stabilization waiting time of step-down circuit

*2: Stabilization waiting time

217/oscillation clock frequency (about 8.19 ms at 16-MHz oscillation clock frequency)

218/Oscillation clock frequency (about 16.38 ms at 16-MHz oscillation clock frequency)

Undefined signal output period

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Figure 2.1-3 Timing Chart for Ports 0 and 1 to Enter High-impedance State (RST Pin Low)

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