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EEL7312 – INE5442

Digital Integrated Circuits

1


Chapter 6 – The CMOS Inverter

EEL7312 – INE5442


2

Dynamic operation - 1

M N

v I v

O

M P

C

V = 5 VDD

(a)

M N

v = 5 VI v (0+) = 5V

O

C

(b)

0 V

+ 5V

0

t

vI

0 V

+ 5V

0

t

vO

High-to-low output transition in a CMOS inverter

C: load capacitance + interconnect capacitance +

capacitances associated with the inverter transistors

Source: Jaeger

EEL7312 – INE5442


3Source: Jaeger


C: load capacitance + interconnect capacitance +

capacitances associated with the inverter transistors

M N

v I v

O

M P

C

V = 5 VDD

(a) (b)

V = 0 V I

M P

v (0+) = 0VO

C

V = 5 VDD

0 V

+ 5V

0

t

vI

0 V

+ 5V

0

t

vO

Low-to- high output transition in a CMOS inverter

EEL7312 – INE5442


4Source: Uyemura


tPHL tPLH

EEL7312 – INE5442


5


0

/ 2

out DD

PHL out DD

t V V

t t V V

= → =

= → =

Propagation

delay - 1

0 VDS(V)I D

(A)

VGS= VDD

VDDVDD/2

VGSn=VDD Vout

VDD

+

VDSn

__

ID IC

outD C

dVC

dtI I= = −

( )

/ 2

0

/ 2

/ 2

1

/ 2

PHL DD

DD

DD

DD

t V

out DDPHL

DavV

V

Dav D DS DS

DD V

D

dV CVdt C t

I

I I V dVV

I= − → =

=

∫ ∫

∫

EEL7312 – INE5442


6


( )

( )

2

2

for 2

/ 2 for

nDS

n

n DS DS DS

n

D Tn TnGS GS

D Tn TnGS GS

k WV

L

Wk V V V

L

I V V V V

I V V V V

≅ >

≅ − ≤

− −

− −

Propagation

delay - 2

( )2

/ 2 / 2;

2

DD DDPHL

nDav

n

PHL

n

n

D DDD Tn

C Ct

W

V CVt

k WI

LLkV VV

≈

= ≈

−

0 VDS(V)I D

(A)

VGS= VDD

VDDVDD/2

Let us assume that ( )2

and that 2

nDsat DD

n

Dav DD Tn Tn

k WI V

LI V V V

≅ = >>

−

In this case we have

( )/ 2

/ 2

1

/ 2

DD

DD

DDPHL

Dav

V

Dav D DS DS

DD V

CVt

I

I I V dVV

=

= ∫

VDD

Vout

Vin= VDD

CIav

Source: Rabaey

Approach 1Approach 1

EEL7312 – INE5442


7


( )2

and 2

that p

Dsat DD

p

Dav DD Tp Tp

k WI V

LI V V V

≅ = >> −

+

Propagation

delay - 3

( )2

/ 2 / 2;

2

DD DDPLH

pDav

n

PLH

p

p

D DDD Tp

C Ct

W

V CVt

k WI

LLkV VV

≈

= ≈

+

Comments:

• kn≈≈≈≈2-3 kp, kn,p=µµµµn,p ·Cox

• Increasing VDD reduces tp but power goes up

• tPLH can be ≈≈≈≈ tPHL by making (W/L)p≈≈≈≈2-3(W/L)n

BUT C is dependent on transistor dimensions

• C includes load (fan-out), wire, inverter “self-

capacitance”

• C is non linear

VDD

Vout

Vin= VDD

C

Iav

Source: Rabaey

2

PLH PHLP

t tt

+=

PHL

n

n

DD

Ct

Wk

LV

≈


EEL7312 – INE5442


8

Dynamic operation - 7 Propagation

delay - 4

Source: Rabaey

EEL7312 – INE5442


9


( )1

0DS

Don n DD Tn

nDS V

dI WR k V V

dV L

−

=

= = −

Propagation

delay - 5

Modeling capacitor discharge as in an RC circuit!

Source: Rabaey PHL

n

n

DD

Ct

Wk

LV

≈


VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

What’s Ron?

0 VDS(V)

I D(A

)

VGS= VDD

VDDVDD/2

Approach by UyemuraApproach by Uyemura

( )0

1

2on midR R R≡ +

1

oR−

Approach by RabaeyApproach by Rabaey

1

midR−

EEL7312 – INE5442


10


( )1

, ( ) ( ) ( )

( )0

( )

DS

Don n p n p DD Tn p

n pDS V

dI WR k V V

dV L

−

=

+

= = −

Propagation

delay - 6

Source: Uyemura

VDD

Vout

Vin = VDD

Ron

CL

tpHL = 0.69 Ron,nCL

tpLH = 0.69 Ron,pCL

Approach by UyemuraApproach by Uyemura

( ) ( )

0.69 1 1

2 2

PHL PLH LP

n DD Tn p DD Tp

n p

t t Ct

W Wk V V k V V

L L+

+ ⋅ = = +

−

0.69 1 1[ ]

2

LP

DDn p

n p

Ct

W WVk k

L L

⋅≈ +

EEL7312 – INE5442


11

Experimental setupDynamic operation - 10

S

GB

+

-

VPULSE

D

2

3

1

1

+

VDD = 5.0 V

-

S

GB

CL

0

0

EEL7312 – INE5442


12


Inverter Propagation Delay * this is the Propagationdelay.cir file* PMOS transistor description MP 3 2 1 1 modelp W=2u L=1u.model modelp pmos (copy description file)* NMOS transistor descriptionMN 3 2 0 0 modeln W=2u L=1u.model modeln nmos (copy description file)* dc sourcevDD 1 0 dc 5.0*load capacitanceCL 3 0 0.01p*signal source v0 2 0 dc 0 pulse 0 5 0 1ps 1ps 200ps 400ps.end

EEL7312 – INE5442


13


SpiceOpus (c) 6 -> source Propagationdelay1.cir SpiceOpus (c) 7 -> tran 1ps 500ps SpiceOpus (c) 8 -> setplot

new New plot Current tran2 Inverter Propagation Delay (Transient Analysis)

tran1 Inverter Propagation Delay (Transient Analysis) const Constant values (constants)

SpiceOpus (c) 9 -> setplot tran2 SpiceOpus (c) 10 -> plot v(2) v(3) xlabel t[s] ylabel 'Input, Output [V]'

EEL7312 – INE5442


14


Why?tPHL≈≈≈≈2.5·tPLH Why?

EEL7312 – INE5442


15


Simulate the transient response of the inverter of the previous exercise for fan-outs of one and two inverters

Exercise

EEL7312 – INE5442


16


Design for Performance

� Keep capacitances small

� Increase transistor sizes (W)

� watch out for self-loading!

� Increase VDD (????)

EEL7312 – INE5442


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� Increase VDD (????)

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(n

orm

alize

d)

* Velocity saturated

devices

Source: Rabaey

EEL7312 – INE5442


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� Increase transistor sizes (W)

� watch out for self-loading


tPLH

tPHL

tPLH0

tPHL0

Propagation delays vs. load capacitance2 4 6 8 10 12 14

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(s

ec)

(for fixed load)

Self-loading effect:Intrinsic capacitancesdominate

Source: UyemuraSource: Rabaey

min

min

W

Lmin

min

SW

L

EEL7312 – INE5442


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Source: Rabaey

Propagation delays vs. PMOS-to-NMOS

transistor ratio β=Wp/Wn

1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

4

4.5

5x 10

-11

β

t p(s

ec)

tpLHtpHL

tp

EEL7312 – INE5442


20


Source: Rabaey

t pH

L(n

sec)

0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20

Impact of Rise Time on DelayImpact of Rise Time on Delay

EEL7312 – INE5442


21

Dynamic operation – 20

Propagation delay vs. Cext/Cint ratio

Source: Rabaey

CL

CL=Cint+Cext

RW

RW

Cint – intrinsic (self-loading) output capacitance

Cext – extrinsic load capacitance (fan-out + wiring)

0

0.69

0.69 (1 / )

(1 / )

= =

+ =

+

p W L

W int ext int

p ext int

t R C

R C C C

t C C

A simple model for the propagation delay

� Symmetric inverter (rise and fall delays are identical)

� Total capacitance is linear

� Minimum length devices

Cext/Cint

tp

tp0

1. tp0 (for minimum-L devices) is

independent of the sizing (W’s) of the gate;

2. Making W infinitely large eliminates the

impact of any external load

EEL7312 – INE5442


22


Source: Rabaey

Inverter Delay• Minimum length devices• Assume that for WP = 2WN =2W

• same pull-up and pull-down currents• approx. equal resistances RN = RP

• approx. equal rise tpLH and fall tpHL delays• Analyze as an RC network

WNunit

Nunit

unit

PunitP RR

W

WR

W

WRR ==

≈

=

−− 11

tpHL = (ln 2) RNCLtpLH = (ln 2) RPCLDelay (D):

2W

W

unit

unit

gin CW

WC 3=Load for previous stage:

2Wunit

Wunit

Inverter

Unit

inverter

EEL7312 – INE5442


23


Source: Rabaey

Inverter Delay

Load

Delay

Delay = 0.69RW(Cint + Cext) = 0.69RWCint + 0.69RWCext= 0.69RW Cint(1+ Cext /Cint)= Delay (Internal) + Delay (Load)

Cint Cext

CN = Cunit

CP = 2Cunit

2W

W

Note:

RW ∝L/W

Cint∝WL

EEL7312 – INE5442


24


Source: Rabaey

Note:

RW ∝L/W

Cint∝WL

tp0∝L2 → minimum L for

minimum delay

Delay Formula

Cint = γCgin with γ ≈ 1f = Cext/Cgin - effective fanout

R = Runit/W ; Cint =WCunit

tp0 = 0.69RunitCunit

( ) ( )γ/1/1 0int ftCCCkRtpintextWp

+=+=

( )~ CCRDelayextintW

+

EEL7312 – INE5442


25


Sources: Rabaey

Weste

Cint = γCgin with γ ≈ 1f = Cext/Cgin =1

( ) ( )γ/1/1 0int ftCCCkRtpintextWp

+=+=

Ring oscillators - 1

N: (odd) number of

inverters (usually >5)

1 1

2 2= → =

osc p

p osc

f tNt Nf

Ring oscillators are used as process monitors to verify if a

chip is faster or slower than nominally expected.

Ex: 31-stage ring oscillator in a 180 nm process oscillates

at 540 MHz.

EEL7312 – INE5442


26


Source: www.keithley.com.cn/data?asset=51070

Ring oscillators - 2N: (odd) number of

inverters (usually >5)

EEL7312 – INE5442


27


Inverter chain - 1

Source: Rabaey

CL

If CL is given:

- How many stages are needed to minimize the delay?- How to size the inverters?

May need some additional constraints.

In Out

EEL7312 – INE5442


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Inverter chain - 2

Source: Rabaey

j-th inverter

Cint=γCg.

j

Cg,j

Cg,j+1

( ) ( ), 0 , 1 , 01 / 1 /+= + = +p j p g j g j p j

t t C C t fγ γ

CL

In Out

1 2 N

First inverter is minimally sized

( ), 0 , 1 , , 1

1 1

1 / ; + +

= =

= = + =∑ ∑N N

p p j p g j g j g N L

j j

t t t C C C Cγ N-1 unknowns: Cg,2, Cg,3,

….Cg,N-1, Cg,N

EEL7312 – INE5442


29


, 1 , ,1/ /+= = = NNg j g j L gf C C C C F

Inverter chain - 3

Source: Rabaey

What´s N that minimizes delay?

( ), 0 , 1 , , 1

1 1

1 / ; + +

= =

= = + =∑ ∑N N

p p j p g j g j g N L

j j

t t t C C C CγLet’s minimize

Taking the N-1 derivatives partial derivatives

and equating them to 0 we find that , , 1 , 1− +=g j g j g jC C C

Thus, each inverter is sized up by the same factor f wrt the preceding gate

The minimum delay is

( ) ( )0 0

1

1 / 1 /=

= + = +∑N

N

p p p

j

t t f Nt Fγ γ

EEL7312 – INE5442


30


( ) ( )0 0

1

1 / 1 /=

= + = +∑N

N

p p p

j

t t f Nt Fγ γ

Inverter chain - 4

Source: Rabaey

dtp/dN=0

The minimum delay is

for N obtained from

or, equivalently

( )1 ln / 0+ − =N F F Nγ( )1 /+

=f

f eγ

tpi: propagation delay of

unit inverter loaded with

another unit inverter

( ),1, ln ln /= = = L gf e N F C C

CL

In Out1 e eN-1

Cg,1

( ),1ln /=p pi L gt et C CCanonical case: γ =0

EEL7312 – INE5442


31

Dynamic operation – 30Inverter chain - 5

Source: Rabaey

Optimum effective fan-out f ( )ff γ+= 1exp

fopt = 3.6

for γ=1

EEL7312 – INE5442


32

Dynamic operation – 31Inverter chain - 6

Sources: Weste and Rabaey

Buffer Design

1 64

1 8 64

1 644 16

1 642.8 8 22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

Small area and power

and close to minimum tp

* Values normalized to tpo

EEL7312 – INE5442


33

Power, energy, and energy delay – 1

Source: Weste

� Power is drawn from a voltage source

attached to the VDD pin(s) of a chip.

� Instantaneous Power:

� Energy:

� Average Power:

( ) ( ) ( )=p t i t v t

0 0

( ) ( ) ( )= =∫ ∫T T

E p t dt i t v t dt

avg

0

1( ) ( )= = ∫

TE

P i t v t dtT T

( ) ( )=DD DD

p t i t VDelivered by the power source

EEL7312 – INE5442


34


Where Does Power Go in CMOS?

Source: Rabaey

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

EEL7312 – INE5442


35


T

vo

VI

Dynamic Power Dissipation

VDD

Cfsw

iDD(t)

VI VO

2

DD

0 0 0

( ) ( )= = = =∫ ∫ ∫DDVT T

DD DD DD DD DD o DDE i t V dt V i t dt V Cdv CV

2

0 0

2

= = =∫ ∫DDVT

DDC o C o o

VE v i dt v Cdv C

Energy delivered by the power supply (EDD) to charge C

The energy stored in the fully charged capacitor is

Where´s the other half of the energy delivered by VDD?

EEL7312 – INE5442


36


T

vo

VI


VDD

Cfsw

iDD(t)

VI VO

( ) 2 2=p DDE M CV

( ) 2 / 2N DDE M CV=

Where´s the energy delivered by VDD?

During the 1 →→→→0 transition of the output, the energy stored on C is dissipated into the n-channel transistor

HEAT

One half of the energy is stored in C whereas the other half is converted into heat in the pull-up network

EEL7312 – INE5442


37


T

vo

VI

Source: Weste


Cfsw

iDD(t)

VDD

VI VO

[ ]

dynamic

0 0

2

sw sw

1( ) ( )

T T

DDDD DD DD

DDDD DD

VP i t V dt i t dt

T T

VTf CV CV f

T

= =

= =

∫ ∫

fsw = αfck, α → activity factor

clock frequency = fck

For low power reduce C, VDD, and fsw

EEL7312 – INE5442


38


Source: Weste


2

dynamic sw 37.5 5 fJ GHz=187.5 WDDP CV f µ= = ⋅ ⋅

Example:

Cfsw

VDD VDD=2.5 V

C=6 fF

Energy delivered by the power

supply (EDD) to charge C2 2

DD 6 2.5 37.5 fJDD

E CV= = ⋅ =tp=50 ps

Assume that fck=1/4tp=5 GHz

For fsw=fck=5 GHz, the average dynamic

power dissipation is

For an activity factor of 0.1, the average

dynamic power dissipation is ~ 18 µW

One million identical inverters with the same activity factor of 0.1 would give a total power dissipation of ~ 18 W

EEL7312 – INE5442


39


Source: Rabaey

Short Circuit Currents

� When transistors switch, both nMOS and pMOS transistors may be momentarily ON at once

� Typically < 10% of dynamic power if rise/fall times are comparable for input and output

Vin Vout

CL

Vdd

I VD

D( m

A)

0.15

0.10

0.05

Vin (V)5.04.03.02.01.00.0

EEL7312 – INE5442


40


Source: Rabaey


EEL7312 – INE5442


41

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin

/tsout

Pnorm

Vdd =1.5

Vdd =2.5

Vdd =3.3


Source: Rabaey


Minimizing ShortMinimizing Short--Circuit Circuit

PowerPower

EEL7312 – INE5442


42


Source: Rabaey

Leakage →→→→ static dissipation

Sub-threshold current one of most compelling

issues in low-energy circuit design!

Vout

Vdd

Sub-Threshold

Current

Drain JunctionLeakage

ReverseReverse--Biased Diode LeakageBiased Diode Leakage

Np+ p+

Reverse Leakage Current

+

-Vdd

GATE

IDL = JS × A

EEL7312 – INE5442


43


Source: Rabaey


~ ~

EEL7312 – INE5442


44


Source: Rabaey


Subthreshold Leakage ComponentSubthreshold Leakage Component

In our simplified model, currents for VGS below VT were assumed to be zero. However, subthreshold current is very important, especially for advanced technologies (low VT’s) and can be the major component of power dissipation.

EEL7312 – INE5442


45


stat stat DDP I V=

Source: Rabaey


Static power is due to the current that flows between supply raiStatic power is due to the current that flows between supply rails in the absence ls in the absence

of switching activityof switching activity

tot stat dynP P P= +

Diode leakage + Diode leakage +

subthreshold currentsubthreshold currentCharge/discharge Cs + Charge/discharge Cs +

shortshort--circuit currentcircuit current

Ptot

Pstat

0 fsw

EEL7312 – INE5442


46


Source: Rabaey

Power-Delay Product (PDP) =Average energy consumed per switching event (0→1 or 1→0)

Energy-Delay Product (EDP) = quality metric of gate = E ×tp

2

2

DDCVPDP =

2

2

DDp p

CVEDP PDP t t= ⋅ =

VDD

Energy delay

0.5

Energy

Delay

1.5 2.52.01.0

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