integrated circuits implementation choicesfranchi/dida02/metodologie_pre.pdf · integrated circuits...

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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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Integrated Circuits Implementation ChoicesIntegrated Circuits Implementation Choices

Full-Custom

Standard Cells(withcompiled cellsand macro cells)

Cell-based

Maskprogrammable

(Gate Arrays)

Pre-wired

(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches

ASIC FPGA


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ASIC ASIC SemicustomSemicustom Design FlowDesign Flow

RTL (HDL es: VHDL)

RTL (HDL es: VHDL)

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

System specification

Des

ign

Itera

tion

Des

ign

Itera

tion

Libreriadi celle

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3

FPGA Design FlowFPGA Design Flow

RTL (HDL es: VHDL)

RTL (HDL es: VHDL)

Logic SynthesisLogic Synthesis

Programming -file

System specification

Libreriadi celle


4The Custom Approach The Custom Approach

Intel 4004

Courtesy Intel

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5Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel


6CellCell--based (or standard cells): core area and based (or standard cells): core area and pin number depend on the applicationpin number depend on the application

Pad

Core area

die

4


7CellCell--based (or standard cells) layoutbased (or standard cells) layout(old generation)(old generation)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier, …)

Routingchannel

Logic cellFeedthrough cell

Row

s of

cel

ls


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Standard Cell Standard Cell –– The New GenerationThe New Generation

Cell-structurehidden underinterconnect layers

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LibreriaLibreria di Standard Cellsdi Standard Cells

q Esempio: libreria AMS 0.35um 250 celle elementari§ Celle combinatorie:

5 inverters, 14 buffers, 8 buffer tri-state, 21 and, 21 or, 12 xor, 21 nand, 21 nor, 6 mux,28 blocchi misti (half-adder, full-adder,..)§ Celle sequenziali:

8 FF JK, 32 FF D§ IO pads:

10 Inout, 12 Inputs, 10 outputs, 6 power


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Standard Cell Standard Cell -- ExampleExample

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time

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11


12

7


13Compiled cellsCompiled cells

256×32 (or 8192 bit) SRAMGenerated by hard-macro module generator


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““Soft” Soft” MacroModulesMacroModules

Synopsys DesignCompiler

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““Intellectual Property”Intellectual Property”

A Protocol Processor for Wireless


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CellCell--based designbased designü Libreria di celle ottimizzate fino al livello di layoutü Dimensioni del die e numero I/O specifici del progettoü Possono essere inseriti moduli full-custom e macro

(es: memorie, moduli aritmetici) ottimizzate fino al livello del layout (macrocell-based design)

elevate prestazioniû Devono essere generate tutte le maschere

elevati costi NRE

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The “Design Closure” ProblemThe “Design Closure” Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)


18Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

Artwork

Netlist with Place-and-Route Info

MacromodulesFixed netlists

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19Esempi


20

90

11


21


22

12


23


24

13


25


26

14


27


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Mask-programmable(Gate Arrays)

Pre-wired(FPGA's)

Array-based

ArrayArray--based Implementationbased Implementation

ASIC

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ArrayArray basedbased: : fixedfixed I/O, I/O, fixedfixed core area core area

Pad

Core area

die

core area:array composedby a replica a basic cell


30

PrePre--diffused or Mask Programmable diffused or Mask Programmable Gate Array Gate Array —— (old generation)(old generation)

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

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31SeaSea--ofof--gates (new generation) gates (new generation)

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 µm CMOS)

Courtesy LSI Logic


32

MaskMask--programmable gateprogrammable gate--arrayarrayü Le porte logiche sono realiazzate a partire da una cella

elementare di dimensione fissata che utilizza transistori con fattore di forma predefinito

ü Dimensioni del die e numero I/O fissateü Non possono essere inseriti moduli full-custom e macro

ottimizzate fino al livello del layout (macrocell-based design)

prestazioni inferiori rispetto la metodologiaa standard-cell

û non devono essere generate tutte le maschere

costi NRE inferiori rispetto alla metodologiastandard-cell

ma è comunque necessaria interazione con la silicon foundry

Flusso di progetto uguale a quello a cell standard

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33FPGA:FPGA:A Historical Perspective: the PLAA Historical Perspective: the PLA

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1


34

TwoTwo--Level LogicLevel Logic

Inverting format (NOR-NOR) more effective

Every logic function can beexpressed in sum-of-productsformat (AND-OR)

product term

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ArrayArray--Based Programmable LogicBased Programmable Logic

PLA PROM PAL

I 5 I 4

O0

I 3 I 2 I 1 I 0

O1O2O3

Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O0

I3 I2 I1 I0

O1O2O3

Fixed AND array

ProgrammableOR array


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Programming a PROMProgramming a PROM

f0

1 X 2 X 1 X 0

f1NANA

: programmed node

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37

More Complex PAL (PLD)More Complex PAL (PLD)

From Smith97

programmable AND array (2 i 3 jk ) k macrocells

j -wide OR array

j

macrocell

productterms

D Q

A

1

j

B

CLK

OUT

C i i inputs

i inputs, j minterms/macrocell, k macrocells


38FPGAFPGA

Blocco Logicoprogrammabile

Canale di interconnessione programmabileI/O block(pad)

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39

6) File per la programmazione

FPGA


40FPGAFPGAClassification of prewired arrays (or field-programmable

devices):q Programming Interconnect Technique§ Fuse-based (program-once)§ Non-volatile EPROM/FLASH based§ RAM based

q Programmable Logic Block (LE, CLB, ..)§ Mux-based§ LUT based

q Programmable Interconnect Structure§ Array based§ Mesh based

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Programming Interconnect TechniqueProgramming Interconnect Technique

M

wire 1

wire 2

Memory M stores the gate voltageof the MOS transistor:

• SRAM • non volatile (FLASH, EEPROM)

wire 1

wire 2

Fuse based (PROM) wire 1

wire 2

oxide


42Programmable logic block Programmable logic block based on based on muxmux

FA 0

B

S

1

Configuration

A B S F=

0 0 0 00 X 1 X0 Y 1 Y0 Y X XYX 0 YY 0 XY 1 X X + Y1 0 X1 0 Y1 1 1 1

XYXY

XY

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43

Logic Cell of Logic Cell of ActelActel FuseFuse--Based FPGABased FPGA

A

B

SA Y

1

C

D

SB

1

S0S1

1


44Programmable Logic Block Programmable Logic Block based on Lookbased on Look--up Table up Table

Outln1 ln2

M e m o r y

In Out

00 0

01 1

10 1

11 0

DE

CO

DE

R

RA

M

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LUTLUT--Based Logic CellBased Logic Cell

Courtesy Xilinx

D4

C1....C4

KClock

D3

D2

D1

F4

F3

F2

F1

Logicfunction

ofD1-D4

Logicfunctionof F’, G’and H’

Logicfunction

ofF1-F4

4

HP

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

D

Y1

1

EC

QSD YQ

X

XQ

RD

D

EC

QSD

RD

Xilinx 4000 Series

F’

G’

H’LUT

Registri

mux la cui configurazioneè fissata in fase di programmazione


46(from Altera)

LUTRegistro


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LABLAB

Logic Array BlockComposti da più LE


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LABLAB

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Carry chainCarry chain

Propaga i riporti fraLE della stessa LABper realizzare la sommaaritmetica


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Cascade Cascade chainchain

Permette la distribuzione su più LE di funzionicombinatorie ad elevato numero di ingressi (FAN-IN) distribuendole su più livelli

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51(from Altera)

LUTRegistro

Cyclone Logic Element (LE) Cyclone Logic Element (LE)



52Programmable Interconnect Programmable Interconnect Structure: ArrayStructure: Array--BasedBased

Input/output pinProgrammed interconnection

Horizontaltracks

Vertical tracks

Cell

InterconnectPoint

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53Programmable Interconnect Structure: Programmable Interconnect Structure: ArrayArray--BasedBased

Input/output pinProgrammed interconnection

Horizontaltracks

Vertical tracks

CellA

B


54Programmable Interconnect Programmable Interconnect Structure: Switch box based (mesh)Structure: Switch box based (mesh)

Switch Box

Connect Box

InterconnectPoint

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

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Transistor Implementation of MeshTransistor Implementation of Mesh

Courtesy Dehon and Wawrzyniek

LogicBlock

Connect Box

Switch Box


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Transistor Implementation of MeshTransistor Implementation of Mesh

Courtesy Dehon and Wawrzyniek

A

B

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AlteraAltera MAX Interconnect ArchitectureMAX Interconnect Architecture

LAB2

PIA

LAB1

LAB6

tPIA

tPIA

row channelcolumn channel

LAB

Courtesy Altera

Array-based(MAX 3000-7000)

Mesh-based(MAX 9000)


58Xilinx 4000 Interconnect ArchitectureXilinx 4000 Interconnect Architecturedifferent length connectionsdifferent length connections

2

12

8

4

3

2

3

CLB

8 4 8 4

Quad

Single

Double

Long

DirectConnect

DirectConnect

Quad Long GlobalClock

Long Double Single GlobalClock

CarryChain

Long12 4 4

Courtesy Xilinx

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59RAMRAM--based FPGA based FPGA

Xilinx XC4000ex

Courtesy Xilinx


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FPGAFPGAü Le porte logiche sono realizzate configurando blocchi logici

programmabiliü Le interconnessioni sono programmabili e introducono un ritardo

non trascurabileü Le dimensioni del die e il numero di I/O sono fissateü Non possono essere inseriti moduli full-custom e macro

ottimizzate fino al livello del layout elevate prestazioni

minori prestazioni rispetto alle altremetodologie semi-custom

û Programmazione per via elettricaMinori costi NREMigliore time-to-market

û Il front-end del flusso di progetto è lo stesso visto per le altremetodologie semi-custom

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61

da: M.Smith, Application Specific Integrated Circuits, Addison Wesley , 1997

costo IC = NRE/volume + (costo del die +costo del package + costo del collaudo)


62

EsempiEsempi: : famigliefamiglie logichelogiche AlteraAltera

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63


64StratixStratix

512Kbit

33


65

ogni LAB contiene 10 LE


66

34


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Impact of Implementation ChoicesImpact of Implementation Choices

Ene

rgy

Effi

cien

cy (

in M

OP

S/m

W)

Flexibility(or application scope)

0.1-1

1-10

10-100

100-1000

None Fullyflexible

Somewhatflexible

Har

dwire

d cu

stom

Con

figur

able

/Par

amet

eriz

able

Dom

ain-

spec

ific

proc

esso

r(e

.g. D

SP

)

Em

bedd

ed m

icro

proc

esso

r

ASIC cell based FPGA

35


69

Heterogeneous Programmable PlatformsHeterogeneous Programmable Platforms

Xilinx Vertex-II Pro

Courtesy XilinxHigh-speed I/O

Embedded PowerPcEmbedded memories

Hardwired multipliers

FPGA Fabric


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Data path: blocco critico per le prestazioni del sistema. Metodologia di progetto: full-custom

Unità di controllo: FSM Flusso a celle standard

Memorie: strutture regolari.Specifica: ottimizzazione della cella elementare per rendere massima la densità integrazione e minimo iltempo di accesso.Metodologia full-custom e compilatori

Risc a 5 stadi di pipeline

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A Protocol Processor for Wirelesscompilatori di moduli di memoria

Microprocessore embedded e acceleratori HWStandard cell e utilizzo di IP

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