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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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Integrated Circuits Implementation ChoicesIntegrated Circuits Implementation Choices

Full-Custom

Standard Cells(withcompiled cellsand macro cells)

Cell-based

Maskprogrammable

(Gate Arrays)

Pre-wired

(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches

ASIC FPGA

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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ASIC ASIC SemicustomSemicustom Design FlowDesign Flow

RTL (HDL es: VHDL)

RTL (HDL es: VHDL)

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

System specification

Des

ign

Itera

tion

Des

ign

Itera

tion

Libreriadi celle

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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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FPGA Design FlowFPGA Design Flow

RTL (HDL es: VHDL)

RTL (HDL es: VHDL)

Logic SynthesisLogic Synthesis

Programming -file

System specification

Libreriadi celle

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

4The Custom Approach The Custom Approach

Intel 4004

Courtesy Intel

3

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

5Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

Intel 4004 (71)Intel 4004 (71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

6CellCell--based (or standard cells): core area and based (or standard cells): core area and pin number depend on the applicationpin number depend on the application

Pad

Core area

die

4

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

7CellCell--based (or standard cells) layoutbased (or standard cells) layout(old generation)(old generation)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier, )

Routingchannel

Logic cellFeedthrough cell

Row

s of

cel

ls

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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Standard Cell Standard Cell The New GenerationThe New Generation

Cell-structurehidden underinterconnect layers

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Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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LibreriaLibreria di Standard Cellsdi Standard Cells

q Esempio: libreria AMS 0.35um 250 celle elementari Celle combinatorie:

5 inverters, 14 buffers, 8 buffer tri-state, 21 and, 21 or, 12 xor, 21 nand, 21 nor, 6 mux,28 blocchi misti (half-adder, full-adder,..) Celle sequenziali:

8 FF JK, 32 FF D IO pads:

10 Inout, 12 Inputs, 10 outputs, 6 power

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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Standard Cell Standard Cell -- ExampleExample

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time

6

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

11

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

12

7

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

13Compiled cellsCompiled cells

25632 (or 8192 bit) SRAMGenerated by hard-macro module generator

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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Soft Soft MacroModulesMacroModules

Synopsys DesignCompiler

8

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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Intellectual PropertyIntellectual Property

A Protocol Processor for Wireless

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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CellCell--based designbased design Libreria di celle ottimizzate fino al livello di layout Dimensioni del die e numero I/O specifici del progetto Possono essere inseriti moduli full-custom e macro

(es: memorie, moduli aritmetici) ottimizzate fino al livello del layout (macrocell-based design)

elevate prestazioni Devono essere generate tutte le maschere

elevati costi NRE

9

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

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The Design Closure ProblemThe Design Closure Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

18Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

Artwork

Netlist with Place-and-Route Info

MacromodulesFixed netlists

10

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

19Esempi

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

20

90

11

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

21

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

22

12

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

23

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

24

13

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

25

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

26

14

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

27

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

28

Mask-programmable(Gate Arrays)

Pre-wired(FPGA's)

Array-based

ArrayArray--based Implementationbased Implementation

ASIC

15

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

29

ArrayArray basedbased: : fixedfixed I/O, I/O, fixedfixed core area core area

Pad

Core area

die

core area:array composedby a replica a basic cell

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

30

PrePre--diffused or Mask Programmable diffused or Mask Programmable Gate Array Gate Array (old generation)(old generation)

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)

16

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

31SeaSea--ofof--gates (new generation) gates (new generation)

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 m CMOS)

Courtesy LSI Logic

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

32

MaskMask--programmable gateprogrammable gate--arrayarray Le porte logiche sono realiazzate a partire da una cella

elementare di dimensione fissata che utilizza transistori con fattore di forma predefinito

Dimensioni del die e numero I/O fissate Non possono essere inseriti moduli full-custom e macro

ottimizzate fino al livello del layout (macrocell-based design)

prestazioni inferiori rispetto la metodologiaa standard-cell

non devono essere generate tutte le maschere

costi NRE inferiori rispetto alla metodologiastandard-cell

ma comunque necessaria interazione con la silicon foundry

Flusso di progetto uguale a quello a cell standard

17

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2008-2009

33FPGA:FPGA:A Historical Perspective: the PLAA Historical Perspective: the PLA

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1

Adapted from J. Rabaey et al, Digi