BRANCH: ELECTRONICS AND COMMUNICATION, 5th SEMESTER (3rd YEAR)SUBJECT-INTEGRATED CIRCUITS

PREPARED BY: REENA RANI

IMPORTANT QUESTIONSUNIT 1QUESTION 1: V1: A) Discuss, Wilson current mirror and Widlar current source. What are the advantages of Widlar current source over Wilson current mirror? 2014-15 (5)

B) Explain Widlar current source. Fig. given below shows two circuit for generating a constant current I. = 10 p,A which operate from a 10 V supply. Determine the values of the required resistor assuming that VBE is 0.7 V at a current of 1 mA and neglecting of the effect of finite p.

(2013-14)(5)

V2: What are the advantages of Widlar current source ? For the circuit shown in figure 1, assuming high p of transistors and VBE = 0.7 V at 1 mA. Find the value of R that will result in I = 101.A.

(2011-12)(10)V3: Explain the circuit of Wilson MOS current mirror. Also, discuss how it can be improved. What do you understand by base current compensated current mirror? (2010-11)(10)ANS: The Wilson current mirrorA Wilson current mirror or Wilson current source, named after George Wilson, is an improved mirror circuit configuration designed to provide a more constant current source or sink. It provides a much more accurate input to output current gain. The structure is shown in figure 11.9.

Figure 11.9 The Wilson Current Mirror.

We will be making the following two assumptions. First, all transistors have the same current gain . Second, Q1 and Q2are matched, so their collector currents are equal. Therefore, IC1 = IC2 (= IC) and IB1 = IB2 (= IB) .

The base current of Q3 is given by,

The emitter of Q3 current by,

Looking at figure 11.9, it can be seen that IE3 = IC2 + IB1 + IB2 Substituting for IC2, IB1 and IB2, IE3 = IC + 2IB

so,

Substituting for IE3

rearranging,

The current through R1 is given by, IR1 = IC1 + IB3

But, IC1 = IC2 = IC

Substituting for IC and since

we get,

Therefore,

And finally,

From the above equation we can see that if

And the output current (assuming the base-emitter voltage of all transistors to be 0.7 V) is calculated as,

Note that the output current is equal to the input current IR1 which in turn is dependent on V1 and R1. If V1 is not stable, the output current will not be stable. Thus the circuit does not act as a regulated constant current source.

In order for it to work as a constant current source, R1 must be replaced with a constant current source.

Advantages over other configurations

This circuit has the advantage of virtually eliminating the base current mismatch of the conventional BJT current mirror thereby ensuring that the output current IC3 is almost equal to the reference or input current IR1. It also has a very high output impedance due to the negative feedback through Q1 back to the base of Q3.

Widlar current source

A Widlar current source is a modification of the basic two-transistor current mirror that incorporates an emitter degeneration resistor for only the output transistor, enabling the current source to generate low currents using only moderate resistor values. This circuit is named for its inventor, Robert Widlar, and was patented in 1967.

The Widlar circuit may be used with bipolar transistors or MOS transistors. An example application is in the now famous uA741 operational amplifier, and Widlar used the circuit in many of his designs.

Analysis

Figure 11.11 A version of the Widlar current source using bipolar transistors.

Figure 11.11 is an example Widlar current source using bipolar transistors, where the emitter resistor R2 is connected in series with the emitter of output transistor Q2, and has the effect of reducing the current in Q2 relative to Q1. The key to this circuit is that the voltage drop across the resistor R2 subtracts from the base-emitter voltage of transistor Q2, thereby reducing the collector current compared to transistor Q1.

This observation is expressed by using KVL around the base emitter loop of the circuit in Fig

Where 2 is the beta of the output transistor, which may not be the same as that of the input transistor, in part because the currents in the two transistors are very different. The variable IB2 is the base current of the output transistor, VBE refers to base-emitter voltage. If we neglect the effect of finite and use the VBE equation we can obtain a useful formula for the output current:

where VT is the thermal voltage, IIN = IC1 and IOUT = IC2.

Suppose we want to create a 100uA output current from a 300uA input current as in the simulation plot of figure 11.12. VT is 26mV times ln(3) is 28.5mV. 28.5mV divided by 100uA is 285 ohms. This equation makes the approximation that the currents are both much larger than the saturation currents IS1, IS2, an approximation valid except for very low current levels. In the following the distinction between the two scale currents is dropped, although the difference can be important, for example, if the two transistors are designed with different emitter areas.

11.8.2 Output impedance

Figure 11.13 Small-signal circuit for finding output resistance of the Widlar source shown in fig.A test current I/x is applied at the output, and the output resistance is then RO = Vx / Ix.

An important property of a current source is its small signal incremental output impedance, which should ideally be infinite. The emitter degeneration resistance introduces local current feedback for transistor Q2. Any increase in the current in Q2 increases the voltage drop across R2, reducing the VBE for Q2, thereby countering the increase in current. This feedback means the output impedance of the circuit is increased, because the feedback involving R2 forces use of a larger voltage to drive a given current.

Output resistance is found using a small-signal model for the circuit, shown in Figure 11.13. The transistor Q1 is replaced by its small-signal emitter resistance rE because it is diode connected. In a diode-connected transistor the collector is short-circuited to the base, so the transistor collector-base junction has no time-varying voltage across it. As a result, the transistor behaves like the base-emitter diode, which at low frequencies has a small-signal circuit that is simply the resistor rE = VT / IE, with IE the DC Q-point emitter current. The transistor Q2 is replaced with its hybrid-pi model. A test current Ix is attached at the output.

Using the figure, the output resistance is determined using Kirchhoff's laws. Using Kirchhoff's voltage law from the ground on the left to the ground connection of R2:

Rearranging:

Using Kirchhoff's voltage law from the ground connection of R2 to the ground of the test current:

or, substituting for Ib:

Eq. 4

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According to Eq. 4, the output resistance of the Widlar current source is increased over that of the output transistor itself (which is rO) so long as R2 is large enough compared to the rp of the output transistor. (Large resistances R2 make the factor multiplying rO approach the value ( +1).) The output transistor carries a low current, making rp large, and increase in R2 tends to reduce this current further, causing a correlated increase in rp. Therefore, a goal of R2 rp can be unrealistic, and further discussion is provided below. The resistance R1 / rE usually is small because the emitter resistance rE usually is only a few ohms.

QUESTION 5: V1: Define following parameter as applied to an amp : (2013-14)(10)(i) Input bias current

(ii) Input offset current and voltage

(iii) C.M.R.R.

(iv) P.S.R.R.

(v) Slew Rate.ANS: Input bias currentThe op-amps input is a differential amplifier, which may be made of. BJT or FET. In either

case the input transistors must be biased into this linear region by supplying currents into the bases. In an ideal op-amp, no current is drawn from the input terminals. The input bias current shown on data sheets is the average value of base currents entering into the terminals of an op-amp. For 741, the bias current is 500nA or less. The smaller the input bias current, the smaller the offset at the output voltage.Input offset current

The input offset current is the difference between the two input currents driven from a common

Source |IOS| = IB + IB.

It tells you how much larger one current is than the other. Bias current compensation will work if

both bias currents IB + and IB are equal. So, the smaller the input offset current the better the OP amp. The 741 op-amps have input offset current of 20nA.Input offset voltage

Ideally, the output voltage should be zero when the voltage between the inverting and non inverting inputs is zero. In reality, the output voltage may not be zero with zero input voltage. This is due to un-avoidable imbalances, mismatches, tolerances, and so on inside the op-amp. In order to make the output voltage zero, we have to apply a small voltage at the input terminals to make output voltage zero. This voltage is called input offset voltage .i.e., input offset voltage is the voltage required to be applied at the input for making output voltage to zero volts. The 741 op-amp has input offset voltage of 5mV under no signal conditions. Therefore, we may have to apply a differential input of 5mV, to produce an output voltage of exactly zero.Common Mode Rejection Ratio (CMRR)

In an ideal different amplifier, Ad is infinite while AC must be zero. However, in a practical

differential amplifier; Ad is very large and AC is very small. ie., the differential amplifier provides very large amplification for difference signals and very small amplification for common mode signals. The ability of a differential amplifier to reject a common-mode signal is expressed by a ration called Common Mode Rejection Ratio, denoted as CMRR. CMRR is defined as the ratio of the differential voltage gain Ad to common mode voltage gain

CMRR = Ad/Ac

Ideally AC is zero. Hence, the ideal value of CMRR is .Slew rate

Slew rate is the most important because it places a severe limit on a large signals operation. Slew rate is defined as the maximum rate at which the output voltage can change. The 741 op-amp has a typical slew rate of 0.5 volts per microsecond (V/s). This is the ultimate speed of a typical 741; its output voltage can change no faster than 0.5V/s. If we drive a 741 with large step input, it takes 20s (0.5 V/sX10V) for the output voltage to change from 0 to 10V.QUESTION 6:

An op amp with unity gain bandwidth fT=2 MHz, SR=1V/s, output saturation voltage Vomax =10V is used to design a non inverting amplifier with an amplification of 10. If the input signal is a sine wave of 25 mV peak-to-peak amplitude, what is the useful frequency range of operation?

(10)ANS:

UNIT 2

QUESTION 1: V1: Draw and explain the most commonly used three Op-Amp Instrumentation Amplifier. Also, derive the expression of voltage gain.

(2010-11) (10)V2: For the circuit shown in figure 4, find Vo. (2011-12) (10)

Design a single stage amplifier to have R1= 1 MO and voltage gain hundred. Na Resistance should have value greater than 50 MO.V3: For the circuit shown in Figure 4 show that common mode gain is minimum when Ri = R3 and R2 = R4.

(2012-13) (10)

QUESTION 2: V1: A) Design the high-pass filter at a cutoff frequency of 1 kHz with a passband gain of 2.

(2010-11) (10)V2: Draw the circuit diagram of state variable filter and find the transfer function of Low pass, High pass and Band pass filter. (2011-12) (10)QUESTION 3: V1: Design a second order low pass filter at a high cut off frequency of 2 kHz using op-amp.

(2013-14) (10)V2: Draw the circuit of IP" order low pass filters and find the expression for its cut-off frequency.Design a second order low pass Butterworth filter to have cut-off frequency I kHz.

(2012-13) (10)QUESTION 4: V1: Design a wide band pass filter with lower cutoff frequency fi..= 200 Hz, higher cutoff frequency fl=1 kHz and a passband Gain=4. (2010-11) (10) V2: Design a wide band pass filter with fL = 500Hz and fH =1500Hz and pass band gain of 5, draw frequency response of the filter and find value of Q?

(2014-15) (10)QUESTION 5: V1: A) Classify active filter and write its advantages with suitable examples. (2013-14) (5) B) Compare and contrast active filters and passive filters.

(2012-13) (5)QUESTION 6: V3: Design a 2nd order Butterworth high pass filter with overall pass band gain of 3 having corner frequency 2 kHz. Also find and plot the frequency response at 100Hz, 500Hz, 1000Hz, 1500Hz, 2000Hz, and 5000Hz. (2014-15) (10)UNIT 3QUESTION 1: V1: Sketch the Logic gate symbolic representation of clocked SR Flip Flop using nand gates. Also sketch its CMOS circuit implementation and explain its operation. (2010-11) (10)V2: Give CMOS implementation of a clocked SR flip-flop and explain its working. (2011-12) (10)V3: A) Implement the following digital CMOS logic circuits: S-R flip-flop. (2012-13) (5) B) Sketch the logic gate symbolic representation of SR flip flop using CMOS NAND gates. (2014-15) (5)V4: Sketch the logic gate symbolic representation of clocked SR flip flop using NAND gate. Also sketch its CMOS circuit implementation and explain its operation. (2013-14) (10)QUESTION 2: V1: Sketch a CMOS logic circuit that realizes the function: (2014-15) (10)F1 = ABC+ DEF(use only CMOS NOR gate)

F2 =(A+B+C).(D+E+F) (use only CMOS NAND gate)

V2: expression :

(2013-14) (10)(i) Z = A(D + E) + BC(ii) Z = (D + E + A) (B + C)V3: Design CMOS logic circuit to realize the Boolean function given by : (2012-13) (10) V4: Find truth table and CMOS realization of following gates :

(2011-12) (10)(i) AND-OR-INVERT (AOI) = F = (AB + CD)

(ii) OR-AND-INVERT (OAI) F = [(A B) (C + D)

QUESTION 3: V1: Draw the D-Flip Flop using CMOS. Also draw and explain its Master slave configuration(2010-11, 13-14) (10)V2: a) Implement the following digital CMOS logic circuits: S-R flip-flop.(2012-13) (10)QUESTION 4: V1: Give the CMOS Logic Circuit that realizes the function of three inputs ODD Parity Checker specifically the Output. is to be high when an odd number (1 or 3) of the input is high.

(2010-11)(10)V2: Design CMOS logic circuit that realize the function of three input parity checker specifically the output is to high when an odd number (1 or 3) of the input is high. (2013-14)(10)QUESTION 5: V1: a) Explain the working operation of CMOS inverter with VTC characteristics. (2013-14)(10) b) Derive the formula for V11, and VIE/ of CMOS inverter. (2014-15) (10)V2: Discuss the features of CMOS circuit. Discuss the effect of Fan-in and Fan-out on propagation delay in CMOS digital logic circuit. (2012-13) (10)QUESTION 6: V1: Give two different CMOS realization of the exclusiveOR function Y = AB + AB in which the PDN and PUN are dual networks.

(2010-11)(10)UNIT 4QUESTION 1: V1: What are Precision rectifiers? Explain full wave Precision rectifier with necessary waveforms.

(2011-12) (10)

V2: Draw the circuit diagram of full wave precision rectifier and find expression for output voltage for both positive and negative half cycle of input sinusoidal waveform. (2012-13) (10)V3: What are the Precision Rectifier ? Draw and explain the operation of Half Wave Precision Rectifier.

(2013-14) (10)V4: What do you understand by precision rectifier? Explain the working of half wave precision rectifier.

(2014-15) (10)QUESTION 2: V1: Draw and explain Anti-Log Amplifier. How temperature Compensation is achieved in anti-log amplifier ? (2010-11) (10)V2: Draw the circuit diagram of Anti-log amplifier and find the expression for output voltage.

(2011-12) (10) V3: Write short note on Log and Antilog amplifier (2013-14) (10)QUESTION 3: V1: Draw the circuit diagram of triangular waveform generator using OPAMP and also find the expression for frequency of the Triangular waveform.

(2011-12) (10)V2: Explain Triangular Wave Generator.

(2010-11) (10)V3: Explain the generation of square and triangular waveforms from astable multivibrator operation using op amp. Also find expression of the time period for both cases. (2014-15)(10)QUESTION 4:

V1: Explain Schmitt Trigger.

(2010-11) (10)V2: For the Schmitt trigger shown in fig. calculate the trip points and hysteresis is V. = 13.5 V. If the resistance have a tolerance of 5%, what is the minimum hysteresis? (2013-14) (10)QUESTION 5: V1: Draw the circuit diagram of Astable multivibrator using OPAMP and find the expression for its time period. Show that ft) = 1if R, = 1.16 R2. 2 RC (2011-12) (10)QUESTION 6: V1: Design a Schmitt trigger for UTP =0.5v and LTP=-0.5V

(10)UNIT 5QUESTION 1: V1: 555 Timer as Monostable Multivibrator.

(2010-11) (10)V2: Draw the functional block diagram of IC 555 and explain its working. Draw the circuit diagram of a monostable multivibrator using 555 and find expression for quasi state period.

(2011-12) (10)V3: What is different mode of operation of IC 555? Draw the circuit diagram of a delay circuit using 555. What is maximum delay that can be provided with 555 with a capacitor of 1000 tiF?

(2012-13) (10)V4: The timer IC 555 is used as astable multivibrator. It is desired to have square wave output with 50% duty cycle of 1 kHz. The timing capacitor is of 0.01 pt.F. Find the values of resistors required and draw the circuit.

(2013-14) (10)V5: Design and implement a free running astable multivibrator using timer 555 with free running frequency of 5kHz having duty cycle of 30%.

(2014-15) (10)QUESTION 2: V1: Phase Locked Loop and its applications.

(2010-11) (10)V2: Define Lock-in-Range, Capture Range and Pull-in-Time as related to PLL. Draw the circuit diagram of Frequency multiplier using PLL and explain its working.

(2011-12) (10)V3: Draw the functional block diagram of PLL IC. Explain its working and deduce the expression for maximum frequency range of signal that can be locked. (2012-13) (10)V4: What is the principle of PLL? Explain Lock range and Capture range with block diagram. Describe PLL application as frequency translator.

(2013-14) (10)V5: Determine the free running frequency fact and the lock range fL, and the capture range fc for PLL 565 having R1=12K, C1--- 0.001F, C2=100',C3 = 0.001g, Vice = 10V? Show the graphical representation between lock frequency, capture frequency and free running frequency.

(2014-15) (10)QUESTION 3: V1: A) R-2R Ladder D/A Converter

(2010-11) (5) B) Explain working of weighted resistor D/A converter. (2014-15) (5)

V2: Draw a 4 bit binary weighted D/A converter, find the value of step size if R=10K and Rt----1.2K.What is the output voltage when all binary inputs are at 5V?(2011-12) (10)V3: Write short note on analog to digital converter.

(2012-13) (10)V4: A) Draw the circuit diagram of weighted resistor digital to analog converter and find the expression of its output analog voltage.

(2013-14) (5)B) Determine the output voltage produced by a 4 bit DAC whose output voltage is 0 to 10 V when the input binary number is 0110.

(2013-14) (5)QUESTION 4: V1: Design and implement an inverting Schmitt trigger for use as a zero crossing detector with saturation voltages of 15V, having hysteresis transition of h25mV.

(10)QUESTION 5: V1: For the R-2R ladder DAC shown in fig. , prove that the output voltages volts for a three bit digital input. Draw the necessary equivalent circuits to support your answer.

(10)QUESTION 6: For a dual slope type ADC, T1=100 ms, VREF = +1V and the analog input voltage is VA = +1V. If the clock frequency is 10 kHz, calculate the digital output of the counter. (10) 40K

=2 K

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